------------------------------------------------------------
-- Copyright: 2011 George Mason University, Virginia USA
--            http://www.iis.ee.ethz.ch/~sha3
------------------------------------------------------------
-- =====================================================================

-- Copyright © 2010-11 by Cryptographic Engineering Research Group (CERG),

-- ECE Department, George Mason University

-- Fairfax, VA, U.S.A.

-- =====================================================================


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.sha3_pkg.all;
use work.sha2_pkg.all;

entity gmu_sha2_datapath is
generic( 
	n : integer :=HASH_SIZE_256/SHA2_WORDS_NUM; 
	a :integer:=LOG_2_64 );
port(	
	clk							: in std_logic;
	rst							: in std_logic;
	wr_state					: in std_logic;
	wr_result					: in std_logic;
	wr_data						: in std_logic;
	kw_wr						: in std_logic;	
	sel							: in std_logic;	  
	sel2						: in std_logic;
	sel_gh						: in std_logic;		
	sel_gh2						: in std_logic;	 
	init_reg					: in std_logic;	  
	init_block					: in std_logic;
	rd_num						: in std_logic_vector(a-1 downto 0);
	data						: in std_logic_vector(511 downto 0);
	dataout						: out std_logic_vector(255 downto 0)
	);

end gmu_sha2_datapath;

architecture sha2_datapath_rs of gmu_sha2_datapath is	 
	type matrix 	is array (0 to STATE_REG_NUM-1) of std_logic_vector(n-1 downto 0);
	type matrix32 	is array (0 to STATE_REG_NUM-1) of std_logic_vector(31 downto 0);
	type matrix64 	is array (0 to STATE_REG_NUM-1) of std_logic_vector(63 downto 0);
	
	signal from_round			:matrix;
	signal to_round				:matrix;
	signal from_final_add		:matrix;
	signal from_mux				:matrix;
	signal result				:matrix;
	constant iv256				:matrix32 := ( SHA256_AINIT, SHA256_BINIT, SHA256_CINIT, SHA256_DINIT, SHA256_EINIT, SHA256_FINIT, SHA256_GINIT, SHA256_HINIT );  
	constant iv512				:matrix64 := ( SHA512_AINIT, SHA512_BINIT, SHA512_CINIT, SHA512_DINIT, SHA512_EINIT, SHA512_FINIT, SHA512_GINIT, SHA512_HINIT );  
	
	signal wwire				:std_logic_vector(n-1 downto 0);
	signal kwire				:std_logic_vector(n-1 downto 0);
	signal h_exception			:std_logic_vector(n-1 downto 0);

	constant zero				:std_logic_vector(n-1 downto 0) := (others => '0');
	signal kwhwire				:std_logic_vector(n-1 downto 0);
	signal kwhreg				:std_logic_vector(n-1 downto 0); 
	signal gh					:std_logic_vector(1 downto 0);
begin		 	

	stateRegProc: 
		process( rst, clk )
		begin	
			if rst = '0' then
				to_round <= matrix(iv256);
			elsif rising_edge( clk ) then	
				if init_reg = '1' then
					to_round <= matrix(iv256);
				elsif wr_state = '1' then	 						
					to_round <= from_mux;
				end if;
			end if;
		end process;
	
	
					
	kwh_reg		: regna 	generic map (n=>n, init =>zero) 
		port map (clk=>clk, en=>kw_wr, rst=>rst, input=>kwhwire, output=>kwhreg);
	
	gh <= sel_gh & sel_gh2;
	
	with gh select
	h_exception <= 	to_round(6) when "00",
					to_round(6) when "01",
					to_round(7) when "10",
					result(6) when OTHERS;
			
	round: 	entity work.sha2_round_rs(basic) 
			generic map (n=>n)		
			port map (
			sel_gh=>sel_gh, kw=>kwhreg, kwire=>kwire, wwire=>wwire,	ain=>to_round(0), bin=>to_round(1), 
			cin=>to_round(2), din=>to_round(3), ein=>to_round(4), fin=>to_round(5), gin=>to_round(6), 
			hin=>h_exception, kwhwire=>kwhwire, aout=>from_round(0),bout=>from_round(1), cout=>from_round(2),	
			dout=>from_round(3), eout=>from_round(4), fout=>from_round(5), gout=>from_round(6), hout=>from_round(7));  	  
			
	mux0_gen: for i in 0 to STATE_REG_NUM-1 generate
		from_mux(i) <= from_final_add(i) when sel='1' else from_round(i);	
	end generate; 
		
		from_final_add(0) <= to_round(0) +  result(3);
		from_final_add(1) <= result(0);
		from_final_add(2) <= result(1);
		from_final_add(3) <= result(2);
		from_final_add(4) <= to_round(4) +  result(7);
		from_final_add(5) <= result(4);
		from_final_add(6) <= result(5);
		from_final_add(7) <= result(6);
	
	resultRegProc: 
		process( rst, clk )
		begin	
			if rst = '0' then					
				result <= matrix(iv256);
			elsif rising_edge( clk ) then	
				if init_reg = '1' then
					result <= matrix(iv256);
				elsif wr_result = '1' then	
					result <= from_final_add;
				end if;
			end if;
		end process;
		
	dc	: entity work.sha2_msg_scheduler(mod_mc_evoy) 
		generic map (n=>n)	
		port map (clk=>clk, rst=>rst, init=>init_block, sel=>sel2, wr_data=>wr_data, data=>data, w=>wwire);
							
	const:entity work.sha2_cons(sha2_cons) generic map (n=>n, a=>a)
		port map (address=>rd_num, output=>kwire);
					  
	dataoutGen: for i in 0 to STATE_REG_NUM-1 generate
		dataout(n*(STATE_REG_NUM-i)-1 downto n*(STATE_REG_NUM-i-1)) <=result(i);	
	end generate;
end sha2_datapath_rs;