------------------------------------------------------------ -- Copyright: 2011 George Mason University, Virginia USA -- http://www.iis.ee.ethz.ch/~sha3 ------------------------------------------------------------ -- ===================================================================== -- Copyright © 2010-11 by Cryptographic Engineering Research Group (CERG), -- ECE Department, George Mason University -- Fairfax, VA, U.S.A. -- ===================================================================== library ieee; use ieee.std_logic_1164.all; use work.sha3_pkg.all; use work.sha2_pkg.all; entity gmu_sha2_top is port ( ClkxCI: in std_logic; -- Rising Edge Triggered Clock RstxRBI: in std_logic; -- Active-low, asynchronous Reset Signal InWrEnxSI: in std_logic; -- Input Enable FinBlockxSI: in std_logic; -- Final Block DataxDI: in std_logic_vector(511 downto 0); -- Input Data ScanInxTI: in std_logic; ScanEnxTI: in std_logic; ScanOutxTO: out std_logic; OutWrEnxSO: out std_logic; -- Output Enable PenUltCyclexSO: out std_logic; -- Penultimate Cycle DataxDO: out std_logic_vector(255 downto 0) -- Output Data ); end gmu_sha2_top; architecture rs_arch of gmu_sha2_top is constant a : integer := LOG_2_64; signal sel2_reg :std_logic; signal sel_reg :std_logic; signal init_block_wire :std_logic; signal wr_data_reg :std_logic; signal wr_state_reg :std_logic; signal wr_result_reg :std_logic; signal kr_wr_wire :std_logic; signal sel_gh_reg :std_logic; signal sel_gh_reg2 :std_logic; signal OutWrEnxSO_s :std_logic; signal init_reg :std_logic; signal rd_num :std_logic_vector(a-1 downto 0); begin datapathInst: entity work.gmu_sha2_datapath(sha2_datapath_rs) generic map (n=>BLOCK_SIZE_512/SHA2_WORDS_NUM, a=>LOG_2_64 ) port map ( clk => ClkxCI, rst => RstxRBI, data => DataxDI, dataout => DataxDO, wr_state=>wr_state_reg, wr_result=>wr_result_reg, wr_data=>wr_data_reg, kw_wr=> kr_wr_wire, sel=>sel_reg, init_block=>init_block_wire, init_reg=>init_reg, sel2=>sel2_reg, sel_gh=>sel_gh_reg, sel_gh2=>sel_gh_reg2, rd_num=>rd_num); OutWrEnxSO <= OutWrEnxSO_s; ctrlInst: entity work.gmu_sha2_control(asic_controller) generic map ( a=>LOG_2_64 ) port map( clk=>ClkxCI, rst=>RstxRBI, InWrEnxSI => InWrEnxSI, FinBlockxSI => FinBlockxSI, OutWrEnxSO => OutWrEnxSO_s, PenUltCyclexSO => PenUltCyclexSO, sel2=>sel2_reg, sel=>sel_reg, sel_gh=>sel_gh_reg, wr_data=>wr_data_reg, rd_num=>rd_num, init_block=>init_block_wire, init_reg=>init_reg, sel_gh2=>sel_gh_reg2, kw_wr=> kr_wr_wire, wr_state=>wr_state_reg, wr_result=>wr_result_reg ); end rs_arch;