------------------------------------------------------------
-- Copyright: 2011 George Mason University, Virginia USA
--            http://www.iis.ee.ethz.ch/~sha3
------------------------------------------------------------
-- =====================================================================

-- Copyright © 2010-11 by Cryptographic Engineering Research Group (CERG),

-- ECE Department, George Mason University

-- Fairfax, VA, U.S.A.

-- =====================================================================


library ieee;
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
use work.sha3_pkg.all;
use work.sha2_pkg.all;

entity sha2_msg_scheduler is 
generic(n : integer :=HASH_SIZE_256/SHA2_WORDS_NUM);
port(
	clk			: in std_logic;	 
	rst			: in std_logic;
	sel			: in std_logic;	
	init		: in std_logic;
	wr_data		: in std_logic;
	data		: in std_logic_vector(511 downto 0);
	w			: out std_logic_vector(n-1 downto 0));
end sha2_msg_scheduler;

architecture mod_mc_evoy of sha2_msg_scheduler is				 

type matrix is array (0 to 15) of std_logic_vector(n-1 downto 0);
signal wires			: matrix;	  
signal wires_in			: matrix;				 			
signal wires_in0_mux	: std_logic_vector(n-1 downto 0);
signal wwires			: std_logic_vector(n-1 downto 0);
signal d_one_wire 		: std_logic_vector(n-1 downto 0);
signal d_zero_wire		: std_logic_vector(n-1 downto 0);  
signal first_stage		: std_logic_vector(n-1 downto 0);  
signal to_second_stage	: std_logic_vector(n-1 downto 0);  
signal second_stage		: std_logic_vector(n-1 downto 0);  
signal to_third_stage	: std_logic_vector(n-1 downto 0); 			
constant zero 			: std_logic_vector(n-1 downto 0):=(others=>'0');
begin										  
							   
	wires_in0_mux <= wwires when sel = '1' else wires(15);
	wires_in(0) <= data(511 downto 480) when init = '1' else wires_in0_mux;
											
	inputGen: for j in 15 downto 1 generate											
		wires_in(j) <= data(n*j-1 downto n*(j-1)) when init = '1' else wires(j-1);
	end generate;

	regGen: 
		for i in 0 to 15 generate
		regProc: 
			process(rst, clk)
			begin		
				if (rst = '0' ) then
					wires(i) <= (others => '0');
				elsif rising_edge( clk )  then
					if (wr_data = '1') then
						wires(i) <= wires_in(i);
					end if;
				end if;   
			end process;	  
		end generate;	
	
	a32: if n=ARCH_32 generate
	d0	: entity work.sha2_sigma_func(sha2_sigma_func)  	generic map (n=>n, func=>"ms", a=>ARCH32_MS0_1, b=>ARCH32_MS0_2, c=>ARCH32_MS0_3) port map (x=>wires(12), o=>d_zero_wire);
	d1	: entity work.sha2_sigma_func(sha2_sigma_func)  	generic map (n=>n, func=>"ms", a=>ARCH32_MS1_1, b=>ARCH32_MS1_2, c=>ARCH32_MS1_3) port map (x=>wires(1), o=>d_one_wire);
	end generate;
	
	a64: if n=ARCH_64 generate
	d0	: entity work.sha2_sigma_func(sha2_sigma_func)  	generic map (n=>n, func=>"ms", a=>ARCH64_MS0_1, b=>ARCH64_MS0_2, c=>ARCH64_MS0_3) port map (x=>wires(12), o=>d_zero_wire);
	d1	: entity work.sha2_sigma_func(sha2_sigma_func)  	generic map (n=>n, func=>"ms", a=>ARCH64_MS1_1, b=>ARCH64_MS1_2, c=>ARCH64_MS1_3) port map (x=>wires(1), o=>d_one_wire);
	end generate;
	
	first_stage <= d_zero_wire + wires(13);
	
	reg01	: entity work.regna(struct) 
		generic map (n=>n, init=>zero) 
		port map(clk=>clk, en=>wr_data, rst=>rst, input=>first_stage, output=>to_second_stage);
	
	second_stage <= to_second_stage + wires(5);
	
	reg02	: entity work.regna(struct) 
		generic map (n=>n, init=>zero) 
		port map(clk=>clk, en=>wr_data, rst=>rst, input=>second_stage, output=>to_third_stage);
	
	wwires <= to_third_stage + d_one_wire;
	
	w <= wires(0);										 
end mod_mc_evoy;