------------------------------------------------------------ -- Copyright: 2011 George Mason University, Virginia USA -- http://www.iis.ee.ethz.ch/~sha3 ------------------------------------------------------------ -- ===================================================================== -- Copyright © 2010-2011 by Cryptographic Engineering Research Group (CERG), -- ECE Department, George Mason University -- Fairfax, VA, U.S.A. -- ===================================================================== -- Possible generics values: -- h = {HASH_SIZE_256, HASH_SIZE_512} -- adder_type = {SCCA_BASED, CLA_BASED, FCCA_BASED} -- -- adder_type : Type of adders being used in the critical paths. They are : -- SCCA_BASED => Standard Carry Chain Addition in FPGA. This is a simple '+' sign. -- FCCA_BASED => Fast Carry Chain Adder which utilizes special property of 6-input LUT FPGA (Applicable only to certain families of FPGA) -- CLA_BASED => Carry Look-Ahead Adder library ieee; use ieee.std_logic_1164.all; use work.sha3_skein_package.all; use work.sha3_pkg.all; entity gmu_skein_top is generic ( h : integer := HASH_SIZE_256; adder_type : integer := SCCA_BASED ); port ( ClkxCI : in std_logic; -- Rising Edge Triggered Clock RstxRBI : in std_logic; -- Active-low, asynchronous Reset Signal ScanInxTI : in std_logic; ScanOutxTO : out std_logic; ScanEnxTI : in std_logic; InEnxSI : in std_logic; -- Input Enable FinBlockxSI : in std_logic; -- Final Block DataxDI : in std_logic_vector(511 downto 0); -- Input Data MsgLenxDI : in std_logic_vector(63 downto 0); OutEnxSO : out std_logic; -- Output Enable PenUltCyclexSO : out std_logic; -- Penultimate Cycle 1 downto 0) -- Output Data ); end gmu_skein_top; architecture structure of gmu_skein_top is signal er, sf : std_logic; signal slast, snb, sfinal : std_logic; begin datapathInst : entity work.gmu_skein_datapath(struct) generic map ( adder_type => adder_type, h => h ) port map ( clk => ClkxCI, rst=>RstxRBI, er=>er, sf=>sf, slast=>slast, snb=>snb, sfinal=>sfinal, din=>DataxDI, dout=>DataxDO, tw_position64 => MsgLenxDI ); controlInst : entity work.gmu_skein_control(beh) port map ( clk => ClkxCI, rst => RstxRBI, er => er, sf => sf, slast => slast, snb => snb, sfinal => sfinal, InEnxSI => InEnxSI, FinBlockxSI => FinBlockxSI, OutEnxSO => OutEnxSO, PenUltCyclexSO => PenUltCyclexSO ); end structure;