#!/bin/sh

############################################################
## Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich
##            http://www.iis.ee.ethz.ch/~sha3
############################################################

# sample script to run gatelevel simulation with sdf timings  
#
# >>> Adapt it for your design !!! <<<  (see README.postlayout)
#

vsim-6.5a -t 1ps -lib gate \
          -L fsd0a_a_generic_core_verilog -L fod0a_b25_t25_generic_io_verilog \
          -sdftyp mutinst=../encounter/out/groestl_small.sdf.gz +sdf_verbose \
          -v2k_int_delays +no_glitch_msg\
          groestltb

# use:
#
#   vsim-6.5a -help 
#
# to see available options

 #         -do "run 200 ns; vcd file ../modelsim/vcd/groestl_small.vcd; vcd add -r /groestltb/mutinst/*; run 6216 ns; quit -f" \