------------------------------------------------------------
-- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;

entity GFSM is

  port (
    ClkxCI      : in  std_logic;
    RstxRBI     : in  std_logic;
    EnxEI       : in  std_logic;
    CntxDO      : out unsigned(7 downto 0);
    PQxSO       : out std_logic;
    SetOupxSO   : out std_logic;
    ModexSO     : out std_logic;
    NewMsgxSO   : out std_logic;
    OutputEnxSO : out std_logic);

end GFSM;

architecture rtl of GFSM is

  type   state is (idle, roundP, roundQ, inter, check, omegaP, omegaQ);
  signal StatexDP, StatexDN   : state;
  signal TENcntxDP, TENcntxDN : unsigned(7 downto 0);
  
begin  -- rtl

  p_fsm : process (EnxEI, StatexDP, TENcntxDP)
  begin  -- process p_fsm

    StatexDN    <= StatexDP;
    TENcntxDN   <= (others => '0');
    PQxSO     <= '0';
    SetOupxSO   <= '0';
    ModexSO     <= '0';
    NewMsgxSO   <= '0';
    OutputEnxSO <= '0';
    CntxDO      <= TENcntxDP;

    case StatexDP is
      -------------------------------------------------------------------------
      when idle =>
        if EnxEI = '1' then
          StatexDN <= roundQ;
          NewMsgxSO <= '1';
        end if;

        -------------------------------------------------------------------------
      when roundP =>

        TENcntxDN <= TENcntxDP;
        StatexDN  <= roundQ;

        -------------------------------------------------------------------------  
      when roundQ =>

        PQxSO <= '1';

        if TENcntxDP = 9 then
          TENcntxDN <= TENcntxDP;
          StatexDN  <= inter;
        else
          
          if TENcntxDP < 9 then
            TENcntxDN <= TENcntxDP+1;
            StatexDN  <= roundP;
          else
            StatexDN <= idle;
          end if;
        end if;

        -------------------------------------------------------------------------
      when inter =>
        SetOupxSO <= '1';
        StatexDN  <= check;

        -------------------------------------------------------------------------
      when check =>
        if EnxEI = '1' then
          StatexDN <= roundQ;
        else
          ModexSO  <= '1';
          StatexDN <= omegaQ;
        end if;

        -------------------------------------------------------------------------
      when omegaP =>

        ModexSO   <= '1';
        TENcntxDN <= TENcntxDP;
        StatexDN  <= omegaQ;

        -------------------------------------------------------------------------
      when omegaQ =>
        
        ModexSO <= '1';
        PQxSO <= '1';

        if TENcntxDP = 9 then
          SetOupxSO   <= '1';
          OutputEnxSO <= '1';
          StatexDN    <= idle;
        else
          if TENcntxDP < 9 then
            TENcntxDN <= TENcntxDP+1;
          end if;
          StatexDN <= omegaP;
        end if;

        -------------------------------------------------------------------------
      when others => StatexDN <= idle;
                     
    end case;
    
  end process p_fsm;

  p_mem : process (ClkxCI, RstxRBI)
  begin  -- process p_mem
    if RstxRBI = '0' then               -- asynchronous reset (active low)
      StatexDP  <= idle;
      TENcntxDP <= (others => '0');
      
    elsif ClkxCI'event and ClkxCI = '1' then  -- rising clock edge
      StatexDP  <= StatexDN;
      TENcntxDP <= TENcntxDN;
      
    end if;
  end process p_mem;

end rtl;