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-- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;

entity FSM is

  port (
    ClkxCI      : in  std_logic;
    RstxRBI     : in  std_logic;
    EnxEI       : in  std_logic;
    CntxDO      : out unsigned(7 downto 0);
    SetOupxSO   : out std_logic;
    NewMsgxSO   : out std_logic;
    ModexSO     : out std_logic;
    LastxSO     : out std_logic;
    OutputEnxSO : out std_logic);

end FSM;

architecture rtl of FSM is

  type   state is (idle, round, check, outputtransform);
  signal StatexDP, StatexDN   : state;
  signal TENcntxDP, TENcntxDN : unsigned(7 downto 0);
  
begin  -- rtl
  
  CntxDO <= TENcntxDP;

  p_fsm : process (EnxEI, StatexDP, TENcntxDP)
  begin  -- process p_fsm

    StatexDN    <= StatexDP;
    TENcntxDN   <= (others => '0');
    SetOupxSO   <= '0';
    NewMsgxSO   <= '0';
    ModexSO     <= '0';
    OutputEnxSO <= '0';
    LastxSO     <= '0';
    
    case StatexDP is
      -------------------------------------------------------------------------
      when idle =>

        if EnxEI = '1' then
          NewMsgxSO <= '1';
          StatexDN  <= round;
          
        end if;

      -------------------------------------------------------------------------
      when round =>  
      
        if TENcntxDP = 159 then
          SetOupxSO <= '1';

          if EnxEI = '0' then
            LastxSO  <= '1';
            StatexDN <= outputtransform;
            
          end if;
          
        else
          TENcntxDN <= TENcntxDP+1;
          
        end if;

      -------------------------------------------------------------------------
      when outputtransform =>
          
        ModexSO <= '1';
        
        if TENcntxDP = 79 then
          SetOupxSO   <= '1';
          OutputEnxSO <= '1';
          StatexDN    <= idle;
          
        else
          TENcntxDN <= TENcntxDP+1;
            
        end if;
        
      -------------------------------------------------------------------------
      when others => StatexDN <= idle;
                     
    end case;
    
  end process p_fsm;

  p_mem : process (ClkxCI, RstxRBI)
  begin  -- process p_mem
    if RstxRBI = '0' then               -- asynchronous reset (active low)
      StatexDP  <= idle;
      TENcntxDP <= (others => '0');
            
    elsif ClkxCI'event and ClkxCI = '1' then  -- rising clock edge
      StatexDP  <= StatexDN;
      TENcntxDP <= TENcntxDN;
            
    end if;
  end process p_mem;

end rtl;