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-- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity gf4imapaffine_2 is
  port (
    AhxDI : in  std_logic_vector(3 downto 0);
    AlxDI : in  std_logic_vector(3 downto 0);
    AxDO  : out std_logic_vector(7 downto 0));

end gf4imapaffine_2;

architecture rtl of gf4imapaffine_2 is

begin  -- rtl

  AxDO(0) <= AlxDI(0) xor AhxDI(0) xor not(AhxDI(3)) xor AhxDI(1) xor AlxDI(2);
  AxDO(1) <= not(AhxDI(0)) xor AhxDI(1) xor AhxDI(3) xor AlxDI(0) xor AlxDI(1) xor AlxDI(2) xor AlxDI(3);
  AxDO(2) <= AhxDI(0) xor AhxDI(1) xor AlxDI(0) xor AlxDI(3);
  AxDO(3) <= AlxDI(2) xor AlxDI(0) xor AhxDI(3) xor AhxDI(0) xor AhxDI(2);
  AxDO(4) <= AlxDI(3) xor AlxDI(0) xor AlxDI(1) xor AhxDI(3) xor AhxDI(0) xor AhxDI(2);
  AxDO(5) <= AhxDI(0) xor not(AhxDI(1)) xor AhxDI(2) xor AhxDI(3) xor AlxDI(1) xor AlxDI(2) xor AlxDI(3);
  AxDO(6) <= AhxDI(0) xor not(AhxDI(2)) xor AhxDI(3);
  AxDO(7) <= AhxDI(2) xor AhxDI(0) xor AlxDI(1) xor AhxDI(3) xor AlxDI(2);
  
end rtl;

Generated on Fri Sep 24 10:39:12 CEST 2010
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