------------------------------------------------------------ -- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich -- http://www.iis.ee.ethz.ch/~sha3 ------------------------------------------------------------ library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; entity groestl is port ( ClkxCI : in std_logic; RstxRBI : in std_logic; EnxEI : in std_logic; OutputEnxSO : out std_logic; MsgInxDI : in std_logic_vector(511 downto 0); HashOutxDO : out std_logic_vector(255 downto 0)); end groestl; architecture rtl of groestl is component GFSM port ( ClkxCI : in std_logic; RstxRBI : in std_logic; EnxEI : in std_logic; CntxDO : out unsigned(7 downto 0); PQxSO : out std_logic; SetOupxSO : out std_logic; ModexSO : out std_logic; NewMsgxSO : out std_logic; OutputEnxSO : out std_logic); end component; component subbytes_groestl is port ( ClkxCI : in std_logic; RstxRBI : in std_logic; DxDI : in std_logic_vector(7 downto 0); DxDO : out std_logic_vector(7 downto 0)); end component; type statearray is array (0 to 7, 0 to 7) of std_logic_vector (7 downto 0); signal CntxD : unsigned(7 downto 0); signal SetOupxS, ModexS, PQxS, NewMsgxS : std_logic; signal MStatexDP, MStatexDN, HStatexDP, HStatexDN : statearray; signal InitStatexD, InitHStatexD : statearray; signal PipeStatexDP, PipeStatexDN, HxD : statearray; signal Temp1, Temp2 : statearray; signal ap, bp, cp, dp, ep, fp, gp, hp, dp1, ep1, gp1, hp1 : statearray; begin -- rtl controller : GFSM port map ( ClkxCI => ClkxCI, RstxRBI => RstxRBI, EnxEI => EnxEI, CntxDO => CntxD, PQxSO => PQxS, SetOupxSO => SetOupxS, ModexSO => ModexS, NewMsgxSO => NewMsgxS, OutputEnxSO => OutputEnxSO); subwolki: for i in 0 to 7 generate subwolkj: for j in 0 to 7 generate sub : subbytes_groestl port map ( ClkxCI => ClkxCI, RstxRBI => RstxRBI, DxDI => temp2(i, ((j+i) mod 8)), DxDO => PipeStatexDN(i, j)); end generate subwolkj; end generate subwolki; -- INITIALIZATION ----------------------------------------------------------------------------- HxD(6, 7) <= x"01" when NewMsgxS = '1' else HStatexDP (6, 7); hrow : for i in 0 to 5 generate hcol : for j in 0 to 7 generate HxD(i, j) <= x"00" when NewMsgxS = '1' else HStatexDP (i, j); end generate hcol; end generate hrow; hline6 : for i in 0 to 6 generate HxD(6, i) <= x"00" when NewMsgxS = '1' else HStatexDP (6, i); end generate hline6; hline7 : for i in 0 to 7 generate HxD(7, i) <= x"00" when NewMsgxS = '1' else HStatexDP (7, i); end generate hline7; -- ROUND -------------------------------------------------------------------------------- Temp1 <= InitStatexD when CntxD = 0 and PQxS = '0' else MStatexDP; Temp2(0, 0) <= std_logic_vector(CntxD) xor Temp1(0, 0) when PQxS = '0' else Temp1(0, 0); --addroundconstant P Temp2(7, 0) <= std_logic_vector(CntxD) xor x"ff" xor Temp1(7, 0) when PQxS = '1' else Temp1(7, 0); --Addroundconstant Q line07 : for i in 1 to 7 generate Temp2(0, i) <= Temp1(0, i); Temp2(7, i) <= Temp1(7, i); end generate; row : for i in 1 to 6 generate column : for j in 0 to 7 generate Temp2(i, j) <= Temp1(i, j); end generate column; --j end generate row; --i mixrow : for i in 0 to 7 generate --mixbytes mixcol : for j in 0 to 7 generate 7) xor HxD(i, j) when ModexS = '0' else HxD(i, j); --setinitstateP MStatexDN(i, j) <= MsgInxDI(511-8*i-64*j downto 511-8*i-64*j-7) when CntxD = 0 and PQxS = '0' else (ap(i, j) xor bp(i, j)) xor (cp(i, j) xor dp(i, j)) xor (ep(i, j) xor fp(i, j)) xor (gp(i, j) xor hp(i, j)); -- The subshiftbytes operation is now carried out with the subbytes compontent -- and directly writen to the PipeState-Register ap(i, j) <= PipeStatexDP(i, j)(6 downto 0)&'0' when PipeStatexDP(i, j)(7) = '0' else PipeStatexDP(i, j)(6 downto 0)&'0' xor x"1b"; bp(i, j) <= PipeStatexDP(((i+1) mod 8), j)(6 downto 0)&'0' when PipeStatexDP(((i+1) mod 8), j)(7) = '0' else PipeStatexDP(((i+1) mod 8), j)(6 downto 0)&'0' xor x"1b"; cp(i, j) <= (PipeStatexDP(((i+2) mod 8), j)(6 downto 0)&'0') xor PipeStatexDP(((i+2) mod 8), j) when PipeStatexDP(((i+2) mod 8), j)(7) = '0' else ((PipeStatexDP(((i+2) mod 8), j)(6 downto 0)&'0') xor PipeStatexDP(((i+2) mod 8), j)) xor x"1b"; dp1(i, j) <= PipeStatexDP(((i+3) mod 8), j)(5 downto 0)&'0'&'0'; dp(i, j) <= dp1(i, j) when PipeStatexDP(((i+3) mod 8), j)(7) = '0' and PipeStatexDP(((i+3) mod 8), j)(6) = '0' else dp1(i, j) xor x"36" when PipeStatexDP(((i+3) mod 8), j)(7) = '1' and PipeStatexDP(((i+3) mod 8), j)(6) = '0' else dp1(i, j) xor x"1b" when PipeStatexDP(((i+3) mod 8), j)(7) = '0' and PipeStatexDP(((i+3) mod 8), j)(6) = '1' else dp1(i, j) xor x"2d"; ep1(i, j) <= (PipeStatexDP(((i+4) mod 8), j)(5 downto 0)&'0'&'0') xor PipeStatexDP(((i+4) mod 8), j); ep(i, j) <= ep1(i, j) when PipeStatexDP(((i+4) mod 8), j)(7) = '0' and PipeStatexDP(((i+4) mod 8), j)(6) = '0' else ep1(i, j) xor x"36" when PipeStatexDP(((i+4) mod 8), j)(7) = '1' and PipeStatexDP(((i+4) mod 8), j)(6) = '0' else ep1(i, j) xor x"1b" when PipeStatexDP(((i+4) mod 8), j)(7) = '0' and PipeStatexDP(((i+4) mod 8), j)(6) = '1' else ep1(i, j) xor x"2d"; fp(i, j) <= (PipeStatexDP(((i+5) mod 8), j)(6 downto 0)&'0') xor PipeStatexDP(((i+5) mod 8), j) when PipeStatexDP(((i+5) mod 8), j)(7) = '0' else ((PipeStatexDP(((i+5) mod 8), j)(6 downto 0)&'0') xor PipeStatexDP(((i+5) mod 8), j)) xor x"1b"; gp1(i, j) <= PipeStatexDP(((i+6) mod 8), j)(5 downto 0)&'0'&'0' xor PipeStatexDP(((i+6) mod 8), j); gp(i, j) <= gp1(i, j) when PipeStatexDP(((i+6) mod 8), j)(7) = '0' and PipeStatexDP(((i+6) mod 8), j)(6) = '0' else gp1(i, j) xor x"36" when PipeStatexDP(((i+6) mod 8), j)(7) = '1' and PipeStatexDP(((i+6) mod 8), j)(6) = '0' else gp1(i, j) xor x"1b" when PipeStatexDP(((i+6) mod 8), j)(7) = '0' and PipeStatexDP(((i+6) mod 8), j)(6) = '1' else gp1(i, j) xor x"2d"; hp1(i, j) <= (PipeStatexDP(((i+7) mod 8), j)(6 downto 0)&'0') xor (PipeStatexDP(((i+7) mod 8), j)(5 downto 0)&'0'&'0') xor PipeStatexDP(((i+7) mod 8), j); hp(i, j) <= hp1(i, j) when PipeStatexDP(((i+7) mod 8), j)(7) = '0' and PipeStatexDP(((i+7) mod 8), j)(6) = '0' else hp1(i, j) xor x"2d" when PipeStatexDP(((i+7) mod 8), j)(7) = '1' and PipeStatexDP(((i+7) mod 8), j)(6) = '0' else hp1(i, j) xor x"1b" when PipeStatexDP(((i+7) mod 8), j)(7) = '0' and PipeStatexDP(((i+7) mod 8), j)(6) = '1' else hp1(i, j) xor x"36"; --Compression HStatexDN(i, j) <= MStatexDN(i, j) xor MStatexDP(i, j) xor HStatexDP(i, j) when SetOupxS = '1' and ModexS = '0' else MStatexDN(i, j) xor HStatexDP(i, j) when SetOupxS = '1' and ModexS = '1' else HxD(i, j); end generate mixcol; --j end generate mixrow; --i --Output atosrow : for j in 4 to 7 generate atoscol : for i in 0 to 7 generate HashOutxDO(255-i*8-64*(j-4) downto 255-i*8-64*(j-4)-7) <= HStatexDN(i, j); end generate atoscol; end generate atosrow; -- Memory ----------------------------------------------------------------------------- p_mem : process (ClkxCI, RstxRBI) begin -- process p_mem if RstxRBI = '0' then -- asynchronous reset (active low) MStatexDP <= (others => (others => (others => '0'))); HStatexDP <= (others => (others => (others => '0'))); PipeStatexDP <= (others => (others => (others => '0'))); elsif ClkxCI'event and ClkxCI = '1' then -- rising clock edge MStatexDP <= MStatexDN; HStatexDP <= HStatexDN; PipeStatexDP <= PipeStatexDN; end if; end process p_mem; end rtl;