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-- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;

entity controller is

  port (
    ClkxCI          : in  std_logic;
    RstxRBI         : in  std_logic;
    FinBlockxSI     : in  std_logic;
    INENxEI         : in  std_logic;
    OUTENxEO        : out std_logic;
    TruncENxEO      : out std_logic;
    LastIterxSO     : out std_logic;
    PermInputSelxSO : out std_logic;
    ChainValSelxSO  : out std_logic;
    RcntxDO         : out unsigned(2 downto 0);
    CntxDO          : out unsigned(2 downto 0));


end controller;

architecture rtl of controller is

  type   state is (idle, round, finalround);
  signal StatexDP, StatexDN : state;
  signal RcntxDP, RcntxDN   : unsigned(2 downto 0);
  signal CntxDP, CntxDN     : unsigned(2 downto 0);

  
begin  -- rtl

  p_fsm: process (CntxDP, FinBlockxSI, INENxEI, RcntxDP, StatexDP)
  begin  -- process p_fsm

    StatexDN        <= StatexDP;
    RcntxDN         <= (others => '0');
    CntxDN          <= (others => '0');
    RcntxDO         <= RcntxDP;
    CntxDO          <= CntxDP;
    OUTENxEO        <= '0';
    TruncENxEO      <= '0';
    LastIterxSO     <= '0';
    PermInputSelxSO <= '0';
    ChainValSelxSO  <= '1';
    

    case StatexDP is
      -------------------------------------------------------------------------
      when idle =>

        if INENxEI = '1' then
          StatexDN       <= round;
          ChainValSelxSO <= '0';
          
        end if;

      -------------------------------------------------------------------------
      when round =>

        PermInputSelxSO <= '1';
        ChainValSelxSO <= '1';

        if CntxDP = 7 then
          if RcntxDP = 2 then
            PermInputSelxSO <= '0';
            TruncENxEO      <= '1';
            if FinBlockxSI = '1' then
              StatexDN <= finalround;

            end if;  

          else
            RcntxDN <= RcntxDP + 1;
            
          end if;
        else
          CntxDN  <= CntxDP + 1;
          RcntxDN <= RcntxDP;
          
        end if;

      -------------------------------------------------------------------------
      when finalround =>

        PermInputSelxSO <= '1';
        LastIterxSO     <= '1';

        if CntxDP = 7 then
          if RcntxDP = 5 then
            TruncENxEO <= '1';
            OUTENxEO <= '1';
            StatexDN <= idle;

          else
            RcntxDN <= RcntxDP + 1;
            
          end if;
        else
          CntxDN  <= CntxDP + 1;
          RcntxDN <= RcntxDP;
        end if;
        
       

      -------------------------------------------------------------------------
      when others => StatexDN <= idle;
                     
    end case;
    
  end process p_fsm;

  p_mem : process (ClkxCI, RstxRBI)
  begin  -- process p_mem
    if RstxRBI = '0' then               -- asynchronous reset (active low)
      StatexDP <= idle;
      RcntxDP  <= (others => '0');
      CntxDP   <= (others => '0');
      
    elsif ClkxCI'event and ClkxCI = '1' then  -- rising clock edge
      StatexDP <= StatexDN;
      RcntxDP  <= RcntxDN;
      CntxDP   <= CntxDN;
      
    end if;
  end process p_mem;

end rtl;