------------------------------------------------------------ -- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich -- http://www.iis.ee.ethz.ch/~sha3 ------------------------------------------------------------ library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; use work.hamsipkg.all; entity diff256 is port ( AxDI : in std_logic_vector(31 downto 0); BxDI : in std_logic_vector(31 downto 0); CxDI : in std_logic_vector(31 downto 0); DxDI : in std_logic_vector(31 downto 0); AxDO : out std_logic_vector(31 downto 0); BxDO : out std_logic_vector(31 downto 0); CxDO : out std_logic_vector(31 downto 0); DxDO : out std_logic_vector(31 downto 0)); end diff256; architecture rtl of diff256 is signal T1xD, T2xD, T3xD, T4xD,T5xD, T6xD, T7xD, T8xD : std_logic_vector(31 downto 0); begin -- rtl T1xD <= AxDI(31-13 downto 0) & AxDI (31 downto 31-13+1); T2xD <= CxDI(31-3 downto 0) & CxDI (31 downto 31-3+1); T3xD <= BxDI xor T1xD xor T2xD; T4xD <= DxDI xor T2xD xor (T1xD(31-3 downto 0) & "000"); T5xD <= T3xD(31-1 downto 0) & T3xD(31); T6xD <= T4xD(31-7 downto 0) & T4xD(31 downto 31-7+1); T7xD <= T1xD xor T5xD xor T6xD; T8xD <= T2xD xor T6xD xor (T5xD(31-7 downto 0) & "0000000"); AxDO <= T7xD(31-5 downto 0) & T7xD(31 downto 31-5+1); CxDO <= T8xD(31-22 downto 0) & T8xD(31 downto 31-22+1); BxDO <= T5xD; DxDO <= T6xD; end rtl;