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-- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich
-- http://www.iis.ee.ethz.ch/~sha3
------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use work.hamsipkg.all;
entity hamsi is
port (
ClkxCI : in std_logic;
RstxRBI : in std_logic;
FinBlockxSI : in std_logic;
INENxEI : in std_logic;
OUTENxEO : out std_logic;
DxDI : in std_logic_vector(31 downto 0);
DxDO : out std_logic_vector(HWIDTH-1 downto 0));
end hamsi;
architecture rtl of hamsi is
component controller
port (
ClkxCI : in std_logic;
RstxRBI : in std_logic;
FinBlockxSI : in std_logic;
INENxEI : in std_logic;
OUTENxEO : out std_logic;
TruncENxEO : out std_logic;
LastIterxSO : out std_logic;
PermInputSelxSO : out std_logic;
ChainValSelxSO : out std_logic;
RcntxDO : out unsigned(2 downto 0));
end component;
component diff256
port (
AxDI : in std_logic_vector(31 downto 0);
BxDI : in std_logic_vector(31 downto 0);
CxDI : in std_logic_vector(31 downto 0);
DxDI : in std_logic_vector(31 downto 0);
AxDO : out std_logic_vector(31 downto 0);
BxDO : out std_logic_vector(31 downto 0);
CxDO : out std_logic_vector(31 downto 0);
DxDO : out std_logic_vector(31 downto 0));
end component;
signal PermInputSelxS : std_logic;
signal LastIterxS : std_logic;
signal ChainValSelxS : std_logic;
signal InChainvalxD : halfstate;
signal OutChainValxD : halfstate;
signal OldChainValxD : halfstate;
signal SBOXOutPermxD : sbox;
signal SBOXxDN, SBOXxDP : sbox;
signal SBOXxD : sbox;
signal SBOXOutAlphaxD : sbox;
signal RcntxD : unsigned(2 downto 0);
signal SBOXOutXorCntxD : sbox;
signal SBOXOutSubxD : sbox;
signal DINxD : data;
signal T1xD, T2xD, T3xD, T4xD, T5xD, T6xD, T7xD : sboxrow;
signal Td01xD, Td02xD, Td03xD, Td04xD, Td05xD, Td06xD, Td07xD, Td08xD : std_logic_vector(31 downto 0);
signal Td11xD, Td12xD, Td13xD, Td14xD, Td15xD, Td16xD, Td17xD, Td18xD : std_logic_vector(31 downto 0);
signal Td21xD, Td22xD, Td23xD, Td24xD, Td25xD, Td26xD, Td27xD, Td28xD : std_logic_vector(31 downto 0);
signal Td31xD, Td32xD, Td33xD, Td34xD, Td35xD, Td36xD, Td37xD, Td38xD : std_logic_vector(31 downto 0);
signal TruncENxE : std_logic;
signal TT0xD, TT1xD, TT2xD, TT3xD : std_logic_vector(255 downto 0);
begin -- rtl
p_inputstruct: for i in 0 to 3 generate
DINxD(i) <= DxDI((4-i)*8-1 downto (3-i)*8);
end generate p_inputstruct;
u_controller : controller
port map (
ClkxCI => ClkxCI,
RstxRBI => RstxRBI,
FinBlockxSI => FinBlockxSI,
INENxEI => INENxEI,
OUTENxEO => OUTENxEO,
TruncENxEO => TruncENxE,
PermInputSelxSO => PermInputSelxS,
LastIterxSO => LastIterxS,
ChainValSelxSO => ChainValSelxS,
RcntxDO => RcntxD);
u_diff256_0: diff256
port map (
AxDI => SBOXOutSubxD(0,0),
BxDI => SBOXOutSubxD(1,1),
CxDI => SBOXOutSubxD(2,2),
DxDI => SBOXOutSubxD(3,3),
AxDO => SBOXOutPermxD(0,0),
BxDO => SBOXOutPermxD(1,1),
CxDO => SBOXOutPermxD(2,2),
DxDO => SBOXOutPermxD(3,3));
u_diff256_1: diff256
port map (
AxDI => SBOXOutSubxD(0,1),
BxDI => SBOXOutSubxD(1,2),
CxDI => SBOXOutSubxD(2,3),
DxDI => SBOXOutSubxD(3,0),
AxDO => SBOXOutPermxD(0,1),
BxDO => SBOXOutPermxD(1,2),
CxDO => SBOXOutPermxD(2,3),
DxDO => SBOXOutPermxD(3,0));
u_diff256_2: diff256
port map (
AxDI => SBOXOutSubxD(0,2),
BxDI => SBOXOutSubxD(1,3),
CxDI => SBOXOutSubxD(2,0),
DxDI => SBOXOutSubxD(3,1),
AxDO => SBOXOutPermxD(0,2),
BxDO => SBOXOutPermxD(1,3),
CxDO => SBOXOutPermxD(2,0),
DxDO => SBOXOutPermxD(3,1));
u_diff256_3: diff256
port map (
AxDI => SBOXOutSubxD(0,3),
BxDI => SBOXOutSubxD(1,0),
CxDI => SBOXOutSubxD(2,1),
DxDI => SBOXOutSubxD(3,2),
AxDO => SBOXOutPermxD(0,3),
BxDO => SBOXOutPermxD(1,0),
CxDO => SBOXOutPermxD(2,1),
DxDO => SBOXOutPermxD(3,2));
-- Expansion and Concatenation
-----------------------------------------------------------------------------
TT0xD <= T256(0, to_integer(unsigned(DINxD(0))));
TT1xD <= T256(1, to_integer(unsigned(DINxD(1))));
TT2xD <= T256(2, to_integer(unsigned(DINxD(2))));
TT3xD <= T256(3, to_integer(unsigned(DINxD(3))));
SBOXxD(0,0) <= TT0xD(255 downto 224) xor TT1xD(255 downto 224) xor TT2xD(255 downto 224) xor TT3xD(255 downto 224);
SBOXxD(0,1) <= TT0xD(223 downto 192) xor TT1xD(223 downto 192) xor TT2xD(223 downto 192) xor TT3xD(223 downto 192);
SBOXxD(1,2) <= TT0xD(191 downto 160) xor TT1xD(191 downto 160) xor TT2xD(191 downto 160) xor TT3xD(191 downto 160);
SBOXxD(1,3) <= TT0xD(159 downto 128) xor TT1xD(159 downto 128) xor TT2xD(159 downto 128) xor TT3xD(159 downto 128);
SBOXxD(2,0) <= TT0xD(127 downto 96) xor TT1xD(127 downto 96) xor TT2xD(127 downto 96) xor TT3xD(127 downto 96);
SBOXxD(2,1) <= TT0xD( 95 downto 64) xor TT1xD( 95 downto 64) xor TT2xD( 95 downto 64) xor TT3xD( 95 downto 64);
SBOXxD(3,2) <= TT0xD( 63 downto 32) xor TT1xD( 63 downto 32) xor TT2xD( 63 downto 32) xor TT3xD( 63 downto 32);
SBOXxD(3,3) <= TT0xD( 31 downto 0) xor TT1xD( 31 downto 0) xor TT2xD( 31 downto 0) xor TT3xD( 31 downto 0);
SBOXxD(0, 2) <= InChainValxD(0);
SBOXxD(0, 3) <= InChainValxD(1);
SBOXxD(1, 0) <= InChainValxD(2);
SBOXxD(1, 1) <= InChainValxD(3);
SBOXxD(2, 2) <= InChainValxD(4);
SBOXxD(2, 3) <= InChainValxD(5);
SBOXxD(3, 0) <= InChainValxD(6);
SBOXxD(3, 1) <= InChainValxD(7);
-- Permutation
-----------------------------------------------------------------------------
p_permutation : process (LastIterxS, RcntxD, SBOXOutAlphaxD, SBOXxDP)
variable LASTITER : integer := 0;
begin -- process p_round
-- Addition of Constant and Counter
if LastIterxS = '1' then
LASTITER := 1;
else
LASTITER := 0;
end if;
for r in 0 to 3 loop
for c in 0 to ArrLen-1 loop
SBOXOutAlphaxD(r,c) <= SBOXxDP(r,c) xor ALPHA(LASTITER,r,c);
end loop; -- c
end loop; -- r'
SBOXOutXorCntxD <= SBOXOutAlphaxD;
SBOXOutXorCntxD(0,1)(2 downto 0) <= SBOXOutAlphaxD(0,1)(2 downto 0) xor std_logic_vector(RcntxD);
end process p_permutation;
p_subst :for i in 0 to ArrLen-1 generate
T1xD(i) <= (SBOXOutXorCntxD(0, i) and SBOXOutXorCntxD(2, i)) xor SBOXOutXorCntxD(3, i);
SBOXOutSubxD(0, i) <= SBOXOutXorCntxD(2, i) xor SBOXOutXorCntxD(1, i) xor T1xD(i); -- XOR(2,1),XOR(2,0)
T3xD(i) <= (SBOXOutXorCntxD(3, i) or SBOXOutXorCntxD(0, i)) xor SBOXOutXorCntxD(1, i);
T4xD(i) <= SBOXOutXorCntxD(0, i) xor SBOXOutSubxD(0, i); -- XOR(4,2)
SBOXOutSubxD(1, i) <= (T3xD(i) or T4xD(i)) xor T1xD(i); -- OR(3,4),XOR(3,0)
T6xD(i) <= T1xD(i) and T3xD(i); -- AND(0,1)
T7xD(i) <= T4xD(i) xor T6xD(i); -- XOR(4,0)
SBOXOutSubxD(2, i) <= T3xD(i) xor SBOXOutSubxD(1, i) xor T7xD(i); -- XOR(1,3),XOR(1,4)
SBOXOutSubxD(3, i) <= not T7xD(i);
end generate p_subst;
-- Truncation
-------------------------------------------------------------------------------
p_truncation: process (OldChainValxD, SBOXOutPermxD, TruncENxE)
variable CHAINVAL : halfstate;
begin -- process p_truncation
if TruncENxE = '1' then
for i in 0 to ArrLen-1 loop
OutChainValxD(i) <= OldChainValxD(i) xor SBOXOutPermxD(0, i);
OutChainValxD(i+4) <= OldChainValxD(i+ArrLen) xor SBOXOutPermxD(2, i);
end loop; -- i
else
for i in 0 to 7 loop
OutChainValxD(i) <= OldChainValxD(i);
end loop; -- i
end if;
end process p_truncation;
-- Chain value select
-----------------------------------------------------------------------------
InChainValxD <= IV256 when ChainValSelxS = '0' else OutChainValxD;
-- Permutation chain value select
-----------------------------------------------------------------------------
SBOXxDN <= SBOXxD when PermInputSelxS = '0' else SBOXOutPermxD;
-- Output Unform
-----------------------------------------------------------------------------
p_outext: for i in 0 to 7 generate
DxDO((HWIDTH/8)*(8-i)-1 downto (HWIDTH/8)*(8-i)-32) <= OutChainValxD(i)(31 downto 0);
end generate p_outext;
-- Memory
-----------------------------------------------------------------------------
p_mem : process (ClkxCI, RstxRBI)
begin -- process p_mem
if RstxRBI = '0' then -- asynchronous reset (active low)
SBOXxDP <= (others => (others => (others => '0')));
OldChainValxD <= (others => (others => '0'));
elsif ClkxCI'event and ClkxCI = '1' then -- rising clock edge
SBOXxDP <= SBOXxDN;
OldChainValxD <= InChainValxD;
end if;
end process p_mem;
end rtl;