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-- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
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library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use work.hamsipkg.all;

entity subst256 is
  
  port (
    AxDI : in  std_logic_vector(31 downto 0);
    BxDI : in  std_logic_vector(31 downto 0);
    CxDI : in  std_logic_vector(31 downto 0);
    DxDI : in  std_logic_vector(31 downto 0);
    AxDO : out std_logic_vector(31 downto 0);
    BxDO : out std_logic_vector(31 downto 0);
    CxDO : out std_logic_vector(31 downto 0);
    DxDO : out std_logic_vector(31 downto 0));

end subst256;

architecture rtl of subst256 is

  signal T1xD, T2xD, T3xD, T4xD, T5xD, T6xD, T7xD : std_logic_vector(31 downto 0);

begin  -- rtl

   T1xD <= (AxDI and CxDI) xor DxDI;
   T2xD <= CxDI xor BxDI xor T1xD;
   T3xD <= (DxDI or AxDI) xor BxDI;
   T4xD <= AxDI xor T2xD;
   T5xD <= (T3xD or T4xD) xor T1xD;
   T6xD <= T1xD and T3xD;
   T7xD <= T4xD xor T6xD;
   AxDO <= T2xD;
   BxDO <= T5xD;
   CxDO <= T3xD xor T5xD xor T7xD;
   DxDO <= not T7xD;
             
end rtl;