#!/bin/sh ############################################################ ## Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich ## http://www.iis.ee.ethz.ch/~sha3 ############################################################ # sample script to run gatelevel simulation with sdf timings # # >>> Adapt it for your design !!! <<< (see README.postlayout) # vsim-6.5a -t 1ps -lib gate \ -L fsd0a_a_generic_core_verilog -L fod0a_b25_t25_generic_io_verilog \ -sdftyp mutinst=../encounter/out/jh_small.sdf.gz +sdf_verbose \ -do "run 497.77 ns; vcd file ../modelsim/vcd/jh_small.vcd; vcd add -r /jhtb/mutinst/*; run 4977.7 ns; quit -f" \ -v2k_int_delays +no_glitch_msg \ jhtb # use: # # vsim-6.5a -help # # to see available options # -do "run 8.554 ns; vcd file ../modelsim/vcd/jh_small.vcd; vcd add -r /jhtb/mutinst/*; run 94.094 ns; quit -f" \