############################################################ ## Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich ## http://www.iis.ee.ethz.ch/~sha3 ############################################################ ## simple script # radical clean sh rm -rf WORK/* # Adjust according tothe num CPUs available # regular machines have just 2. Arinas have 16 !! set_host_options -max_cores 2 # less radical clean remove_design -design ## set the targets to be the worst case library to begin with set target_library [list fsd0a_a_generic_core_ss1p08v125c.db ] set link_library [list "*" dw_foundation.sldb fsd0a_a_generic_core_ss1p08v125c.db ] analyze -f vhdl { ../sourcecode/jhfsm_con.vhd \ ../sourcecode/jh_con.vhd } ## analyze -f vhdl { ../sourcecode/jhfsm_con.vhd \ ## ../sourcecode/jh_comb.vhd } ## analyze -f vhdl { ../sourcecode/jhfsm.vhd \ ## ../sourcecode/jh.vhd } ## Elaborate elaborate jh ## constraints ## we need 71.11ns for 200 Mbps set CLK 71.1 create_clock -name ClkxCI -period $CLK ClkxCI set_input_delay 0 -clock ClkxCI [remove_from_collection [all_inputs] ClkxCI] set_output_delay 0 -clock ClkxCI [all_outputs] set_ideal_network RstxRBI ## driving cell set_driving_cell -no_design_rule -library fsd0a_a_generic_core_ss1p08v125c -lib_cell BUFX8 [remove_from_collection [all_inputs] ClkxCI] # simple load set_load 0.050 [all_outputs] set_max_area 0 uniquify compile_ultra write_file -h -f ddc -o DDC/jh_small.ddc define_name_rules verilog -add_dummy_nets change_names -h -rules verilog write -h -f verilog -o netlists/jh_small.v