#
# FirstEncounter(TM) Clock Synthesis Technology File Format
#

#
# This is an example file, adapt it for your design !!!
#
# IMPORTANT: Existing buffers/inverters on the clock network(s) are NOT automatically
# removed during clock tree synthesis, so to get a nicely balanced tree you should 
# do this manually by running the command "deleteClockTree -all".
# To remove an already inserted tree, "changeClockStatus -all -noFixedBuffers"
# has to be run beforehand, otherwise the buffers can not be removed as they have
# the status "FIXED".  
#


#-- MacroModel --
#MacroModel pin      

#-- Special Route Type --
#RouteTypeName specialRoute
#TopPreferredLayer 4
#BottomPreferredLayer 3
#PreferredExtraSpace 1
#End

#-- Regular Route Type --
#RouteTypeName regularRoute
#TopPreferredLayer 4
#BottomPreferredLayer 3
#PreferredExtraSpace 1
#End

#-- Clock Group --
#ClkGroup
#+ 

#-- Nanoroute follows CTS route guide (for RouteClkNet YES) --
UseCTSRouteGuide    YES

#------------------------------------------------------------
# clock tree  (tight constraints)
#
# For (very) small trees "MaxFanout" might be useful to get 
# some more buffers and reduce the impact of (clock tree)
# routing.
#
# For the best results (but worse overall routability) the clock
# net can be routed during CTS ("RouteClkNet  YES"). To get an
# optimally balanced routing also set "UseCTSRouteGuide YES".
#------------------------------------------------------------
AutoCTSRootPin ClkxCI
#Period         3ns
MaxDelay       1.4ns
MinDelay       0ns
MaxSkew        100ps
SinkMaxTran    300ps
BufMaxTran     300ps
Buffer         BUFXLP BUFCKX1 BUFX1 BUFCKX1P BUFX1P BUFCKX2 BUFX2 BUFCKX3 BUFX3 BUFCKX4 BUFX4 BUFX5 BUFCKX6 BUFX6 BUFCKX8 BUFX8 BUFCKX12 BUFX12 BUFCKX16 BUFX16 BUFCKX20 BUFX20 INVXLP INVCKXLP INVCKX1 INVX1 INVX1P INVCKX1P INVX2 INVCKX2 INVCKX3 INVX3 INVX4 INVCKX4 INVX5 INVX6 INVCKX6 INVX8 INVCKX8 INVX12 INVCKX12 INVX16 INVCKX16 INVX20 INVCKX20 
# If you want to use low leakage buffers exclusively use the line below
#Buffer         BUFRLXLP BUFCKRLX1 BUFRLX1 BUFCKRLX1P BUFRLX1P BUFCKRLX2 BUFRLX2 BUFCKRLX3 BUFRLX3 BUFCKRLX4 BUFRLX4 BUFRLX5 BUFCKRLX6 BUFRLX6 BUFCKRLX8 BUFRLX8 BUFCKRLX12 BUFRLX12 BUFCKRLX16 BUFRLX16 BUFCKRLX20 BUFRLX20 INVRLXLP INVCKRLXLP INVCKRLX1 INVRLX1 INVRLX1P INVCKRLX1P INVRLX2 INVCKRLX2 INVCKRLX3 INVRLX3 INVRLX4 INVCKRLX4 INVRLX5 INVRLX6 INVCKRLX6 INVRLX8 INVCKRLX8 INVRLX12 INVCKRLX12 INVRLX16 INVCKRLX16 INVRLX20 INVCKRLX20 
#MaxFanout      30
#AddDriverCell BUFCKX12
NoGating       NO
DetailReport   YES
#SetDPinAsSync  NO
#SetIoPinAsSync NO
RouteClkNet     YES
#PostOpt        YES
#OptAddBuffer   NO
#RouteType      specialRoute
#LeafRouteType  regularRoute
ThroughPin
#+ i_xor/I1 O
#+ inst_ClockDivider/inst_div/CK Q_
ExcludedPin
#+ inst_ClockResetGen/inst_DontTouch_FXPLL110HC0H_APGD/FREF
#+ inst_ClockResetGen/inst_DontTouch_PllBypassMUX/B
END

#------------------------------------------------------------
# reset tree  (loose constraints)
#------------------------------------------------------------
AutoCTSRootPin RstxRBI
#Period         10ns
MaxDelay       3ns
MinDelay       0ns
MaxSkew        3ns
SinkMaxTran    2ns
BufMaxTran     2ns
Buffer         BUFXLP BUFCKX1 BUFX1 BUFCKX1P BUFX1P BUFCKX2 BUFX2 BUFCKX3 BUFX3 BUFCKX4 BUFX4 BUFX5 BUFCKX6 BUFX6 BUFCKX8 BUFX8 BUFCKX12 BUFX12 BUFCKX16 BUFX16 BUFCKX20 BUFX20 INVXLP INVCKXLP INVCKX1 INVX1 INVX1P INVCKX1P INVX2 INVCKX2 INVCKX3 INVX3 INVX4 INVCKX4 INVX5 INVX6 INVCKX6 INVX8 INVCKX8 INVX12 INVCKX12 INVX16 INVCKX16 INVX20 INVCKX20 
# If you want to use low leakage buffers exclusively use the line below
#Buffer         BUFRLXLP BUFCKRLX1 BUFRLX1 BUFCKRLX1P BUFRLX1P BUFCKRLX2 BUFRLX2 BUFCKRLX3 BUFRLX3 BUFCKRLX4 BUFRLX4 BUFRLX5 BUFCKRLX6 BUFRLX6 BUFCKRLX8 BUFRLX8 BUFCKRLX12 BUFRLX12 BUFCKRLX16 BUFRLX16 BUFCKRLX20 BUFRLX20 INVRLXLP INVCKRLXLP INVCKRLX1 INVRLX1 INVRLX1P INVCKRLX1P INVRLX2 INVCKRLX2 INVCKRLX3 INVRLX3 INVRLX4 INVCKRLX4 INVRLX5 INVRLX6 INVCKRLX6 INVRLX8 INVCKRLX8 INVRLX12 INVCKRLX12 INVRLX16 INVCKRLX16 INVRLX20 INVCKRLX20 
#MaxFanout      30
NoGating       NO
DetailReport   YES
#SetDPinAsSync  NO
#SetIoPinAsSync NO
SetASyncSRPinAsSync YES
#RouteClkNet    NO
#PostOpt        YES
#OptAddBuffer   NO
#RouteType      specialRoute
#LeafRouteType  regularRoute
ThroughPin
END

Generated on Fri Sep 24 10:39:12 CEST 2010
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