############################################################ ## Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich ## http://www.iis.ee.ethz.ch/~sha3 ############################################################ # # create logical connectivity for power/ground pins, # connect logic one/zero (1'b1/1'b0) in netlist to power/ground # clearGlobalNets globalNetConnect VCCK -type pgpin -pin VCC -inst * globalNetConnect GNDK -type pgpin -pin GND -inst * globalNetConnect VCCK -type tiehi globalNetConnect GNDK -type tielo #globalNetConnect VCCK -type pgpin -pin VCCK -sinst inst_ClockResetGen/inst_DontTouch_FXPLL110HC0H_APGD #globalNetConnect GNDK -type pgpin -pin GNDK -sinst inst_ClockResetGen/inst_DontTouch_FXPLL110HC0H_APGD