############################################################ ## Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich ## http://www.iis.ee.ethz.ch/~sha3 ############################################################ freeDesign set DESIGNNAME luffa ## Load the configuration file loadConfig src/${DESIGNNAME}.conf 0 commitConfig fit ## Make sure we have two corners. No need for MMMC in this one setTimingLibrary -max Max -min Min setDesignMode -process 90 ## floorplan floorPlan -site core_2800 -r 1 0.85 30 30 30 30 ## power routing source scripts/globalnet.tcl source scripts/power_grid.tcl ## use all CPUs (2 in my case) setMultiCpuUsage -localCpu [getMultiCpuUsage -localCpu] -cpuPerRemoteHost 1 -remoteHost 0 -keepLicense true ##place setPlaceMode -fp false placeDesign -PrePlaceOpt # Change to Physical View setDrawView place fit ## checkTiming set_global report_timing_format {instance arc cell slew load fanout delay arrival} unloadTimingCon loadTimingCon src/${DESIGNNAME}.sdc timeDesign -preCTS # Tie Cells Rep #source scripts/tiehilo.tcl #source scripts/tiehilo-remove-sp.tcl #source scripts/tiehilo-setmode-sp.tcl #source scripts/tiehilo-insert.tcl ## This will most likely be necessary optDesign -preCTS ## check the timing after this ## insert clock tree specifyClockTree -file src/${DESIGNNAME}.ctstch clockDesign -specFile src/${DESIGNNAME}.ctstch -outDir timingReports -fixedInstBeforeCTS # Time Opt optDesign -postCTS optDesign -postCTS -hold # final route setNanoRouteMode -quiet -routeTopRoutingLayer default setNanoRouteMode -quiet -routeBottomRoutingLayer default setNanoRouteMode -quiet -drouteEndIteration default setNanoRouteMode -quiet -routeWithTimingDriven false setNanoRouteMode -quiet -routeWithSiDriven false routeDesign -globalDetail ## check timing timeDesign -postRoute ## make sure there are no violations for hold timeDesign -reportOnly -postRoute -hold # Time Opt optDesign -postRoute #optDesign -postRoute -hold # Verify Connectivity #verifyConnectivity -type all -error 1000 -warning 50 # Verify Geometry #verifyGeometry # Report Gate Count reportGateCount -level 5 -limit 100 -outfile ${DESIGNNAME}.gateCount # Summary summaryReport -noHtml -outfile ${DESIGNNAME}_summary.rpt # Export Files source scripts/exportall.tcl # we are done here saveDesign save/${DESIGNNAME}.enc # Report Power set_power_analysis_mode -reset set_power_analysis_mode -method static -corner max -create_binary_db true -write_static_currents true -honor_negative_energy true -ignore_control_signals true set_power_output_dir -reset set_power_output_dir powerReports set_default_switching_activity -reset set_default_switching_activity -period 1.6 read_activity_file -reset read_activity_file -format VCD -vcd_scope luffatb/mutinst -start {} -end {} -vcd_block {} ../modelsim/vcd/${DESIGNNAME}.vcd set_power -reset set_powerup_analysis -reset set_powerup_analysis -mode accurate -ultrasim_simulation_mode ms set_dynamic_power_simulation -reset report_power -rail_analysis_format VS -outfile powerReports/${DESIGNNAME}.rpt