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-- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;

entity controller is

  port (
    ClkxCI         : in  std_logic;
    RstxRBI        : in  std_logic;
    FinBlockxSI    : in  std_logic;
    INENxEI        : in  std_logic;
    OUTENxEO       : out std_logic;
    StateRegSelxSO : out std_logic;
    StateInSelxSO  : out std_logic;
    CntxDO         : out unsigned(1 downto 0));
   
end controller;

architecture rtl of controller is

  type   state is (idle, round);
  signal StatexDP, StatexDN : state;
  signal RcntxDP, RcntxDN   : unsigned(2 downto 0);
  signal CntxDP, CntxDN     : unsigned(1 downto 0);
  
begin  -- rtl

  p_fsm: process (CntxDP, FinBlockxSI, INENxEI, RcntxDP, StatexDP)
  begin  -- process p_fsm

    StatexDN       <= StatexDP;
    RcntxDN        <= (others => '0');
    CntxDN         <= (others => '0');
    CntxDO         <= CntxDP;
    OUTENxEO       <= '0';
    StateRegSelxSO <= '1';
    StateInSelxSO  <= '1';
    
   
    case StatexDP is
      -------------------------------------------------------------------------
      when idle =>

        if INENxEI = '1' then
          StatexDN       <= round;
          StateRegSelxSO <= '0';
          StateInSelxSO  <= '0';
          
        end if;

      -------------------------------------------------------------------------
      when round =>

        StateRegSelxSO <= '1';
        StateInSelxSO  <= '1';
        
        if CntxDP = 2 then
          if RcntxDP = 7 then
            if FinBlockxSI = '1' then
              OUTENxEO <= '1';
              StatexDN <= idle;
            else
              StateRegSelxSO <= '0';
              StatexDN <= round;

            end if;  

          else
            RcntxDN <= RcntxDP + 1;
                   
          end if;
        
        else
          CntxDN  <= CntxDP + 1;
          RcntxDN <= RcntxDP;
          
        end if;
      

      -------------------------------------------------------------------------
      
      when others => StatexDN <= idle;
                     
    end case;
    
  end process p_fsm;

  p_mem : process (ClkxCI, RstxRBI)
  begin  -- process p_mem
    if RstxRBI = '0' then               -- asynchronous reset (active low)
      StatexDP <= idle;
      RcntxDP  <= (others => '0');
      CntxDP   <= (others => '0');
      
    elsif ClkxCI'event and ClkxCI = '1' then  -- rising clock edge
      StatexDP <= StatexDN;
      RcntxDP  <= RcntxDN;
      CntxDP   <= CntxDN;
                  
    end if;
  end process p_mem;
end rtl;