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-- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
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library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use work.luffapkg.all;

entity mixword is

  port (
    MxDI : in  mixdata;
    MxDO : out mixdata);

end mixword;

architecture rtl of mixword is

  signal T0xD, T1xD, T2xD, T3xD, T4xD, T5xD, T6xD : std_logic_vector(31 downto 0);

begin

  T1xD    <= MxDI(0) xor MxDI(1);
  T2xD    <= MxDI(0)(31-2 downto 0) & MxDI(0)(31 downto 30);
  T3xD    <= T2xD xor T1xD;
  T4xD    <= T1xD(31-14 downto 0) & T1xD(31 downto 31-14+1);
  T5xD    <= T4xD xor T3xD;
  T6xD    <= T3xD(31-10 downto 0) & T3xD(31 downto 31-10+1);
  MxDO(0) <= T6xD xor T5xD;
  MxDO(1) <= T5xD(31-1 downto 0) & T5xD(31);
    
end rtl;