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-- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
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library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use work.luffa512pkg.all;


entity mult2 is

  port (
    TxDI : in  data;
    TxDO : out data);

end mult2;

architecture rtl of mult2 is

  signal TmpxD : std_logic_vector(31 downto 0);
  
begin
  TmpxD   <= TxDI(7);
  TxDO(7) <= TxDI(6);
  TxDO(6) <= TxDI(5);
  TxDO(5) <= TxDI(4);
  TxDO(4) <= TxDI(3) xor TmpxD;
  TxDO(3) <= TxDI(2) xor TmpxD;
  TxDO(2) <= TxDI(1);
  TxDO(1) <= TxDI(0) xor TmpxD;
  TxDO(0) <= TmpxD;

end rtl;