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-- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
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library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use work.luffapkg.all;


entity subcrumb is

  port (
    SxDI : in  halfdata;
    SxDO : out halfdata);

end subcrumb;

architecture rtl of subcrumb is

  signal T0xD, T1xD, T2xD, T3xD, T4xD, T5xD, T6xD     : std_logic_vector(31 downto 0);
  signal T7xD, T8xD, T9xD, T10xD, T11xD, T12xD, T13xD : std_logic_vector(31 downto 0);
  signal SIxD, SOxD                                   : halfdata;

begin

--  SIxD(0) SxDI(1);
--  SIxD(1) SxDI(2);
--  SIxD(2) SxDI(3);
--  SIxD(3) SxDI(0);

  T0xD    <= SxDI(0);             --  tmp  = *a0;  | 
  T1xD    <= SxDI(0) or SxDI(1);  --  *a0 |= *a1;  | 
  T2xD    <= SxDI(2) xor SxDI(3); --  *a2 ^= *a3;  | 
  T3xD    <= not SxDI(1);         --  *a1  = ~*a1; | 
  T4xD    <= T1xD xor SxDI(3);    --  *a0 ^= *a3;  | 
  T5xD    <= SxDI(3) and T0xD;    --  *a3 &= tmp;  | 
  T6xD    <= T5xD xor T3xD;       --  *a1 ^= *a3;  | 
  T7xD    <= T5xD xor T2xD;       --  *a3 ^= *a2;  | 
  T8xD    <= T2xD and T4xD;       --  *a2 &= *a0;  | 
  T9xD    <= not T4xD;            --  *a0  = ~*a0; | 
  T10xD   <= T8xD xor T6xD;       --  *a2 ^= *a1;  | 
  T11xD   <= T6xD or T7xD;        --  *a1 |= *a3;  | 
  T12xD   <= T0xD xor T11xD;      --  tmp ^= *a1;  | 
  SxDO(3) <= T7xD xor T10xD;      --  *a3 ^= *a2;  | 
  SxDO(2) <= T10xD and T11xD;     --  *a2 &= *a1;  | 
  SxDO(1) <= T11xD xor T9xD;      --  *a1 ^= *a0;  | 
  SxDO(0) <= T12xD;               --  *a0  = tmp;  | 

--  SxDO(1) SOxD(0);
--  SxDO(2) SOxD(1);
--  SxDO(3) SOxD(2);
--  SxDO(0) SOxD(3);
  
end rtl;