############################################################ ## Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich ## http://www.iis.ee.ethz.ch/~sha3 ############################################################ # # export all relevant design data # # is the design name specified ??? if { [ info exists DESIGNNAME ] } { set NAME "$DESIGNNAME" } else { set NAME "final" } # parasitics encounter setExtractRCMode -engine detail -coupled false -reduce 0.0 extractRC #runQRC -layerMapping tech/lefdef-gds.qrc.layermap -grayData gds -rcType decoupledRc -extraConfig scripts/qrc.extra.cmd rcOut -spef out/${NAME}.spef.gz # timing setAnalysisMode -checkType setup #Write out SDF delayCal -sdf out/${NAME}.sdf.gz #NOTE: If you use memory devices sometimes statements like # the following will be written to the SDF # # (PERIOD (negedge CKB) # # This will give you problems during backannotation. # This will definetely happen if you use the two-port # Memories (SZxx). Use the fix_sdf.pl file to get # rid of these lines. # write_sdf is better, does not need the perl script, but.. # at the moment we have problems with typical values. #write_sdf -precision 4 -min_period_edges posedge -remashold out/${NAME}.sdf.gz # This netlist contains all filler cells and everything. # this can be used for LVS and for simulation saveNetlist out/${NAME}.v -excludeLeafCell -includePhysicalInst # layout setStreamOutMode -SEvianames ON -specifyViaName %t_VIA # you can set an alternative top name with -structureName # streamOut out/${NAME}.gds.gz -structureName sem01w0 streamOut out/${NAME}.gds.gz -mapFile tech/streamOut_noObs.map -outputMacros -merge { \ /usr/pack/umc-90-kgf/faraday/sp/fsd0a_a/2009Q2v2.0/GENERIC_CORE_1D2V/BackEnd/gdsii/FSD0A_A_GENERIC_CORE.all.gds \ /usr/pack/umc-90-kgf/faraday/sp/fod0a_b25/2009Q2v3.0/T25_GENERIC_IO/BackEnd/gdsii/FOD0A_B25_T25_GENERIC_IO.8m026.gds \ }