################################################ # # # FirstEncounter Input configuration file # # # ################################################ # Created by First Encounter v08.10-s372_1 on Mon Dec 14 16:12:04 2009 global rda_Input set rda_Input(import_mode) {-treatUndefinedCellAsBbox 0 -keepEmptyModule 1 -useLefDef56 1 } set rda_Input(ui_netlist) "../synopsys/netlists/shabal_small.v" set rda_Input(ui_netlisttype) {Verilog} set rda_Input(ui_rtllist) "" set rda_Input(ui_ilmdir) "" set rda_Input(ui_ilmlist) "" set rda_Input(ui_ilmspef) "" set rda_Input(ui_settop) {0} set rda_Input(ui_topcell) {} set rda_Input(ui_celllib) "" set rda_Input(ui_iolib) "" set rda_Input(ui_areaiolib) "" set rda_Input(ui_blklib) "" set rda_Input(ui_kboxlib) "" set rda_Input(ui_gds_file) "" set rda_Input(ui_oa_oa2lefversion) {} set rda_Input(ui_view_definition_file) {} set rda_Input(ui_timelib,min) "tech/lib/fsd0a_a_generic_core_ff1p32vm40c.eclib" set rda_Input(ui_timelib,max) "tech/lib/fsd0a_a_generic_core_ss1p08v125c.eclib" set rda_Input(ui_timelib) "" set rda_Input(ui_smodDef) "" set rda_Input(ui_smodData) "" set rda_Input(ui_dpath) "" set rda_Input(ui_tech_file) "" set rda_Input(ui_io_file) "" set rda_Input(ui_timingcon_file,full) "" set rda_Input(ui_timingcon_file) "src/shabal_small.sdc" set rda_Input(ui_latency_file) "" set rda_Input(ui_scheduling_file) "" set rda_Input(ui_buf_footprint) {} set rda_Input(ui_delay_footprint) {} set rda_Input(ui_inv_footprint) {} set rda_Input(ui_leffile) "tech/lef/header8m026_V57.lef tech/lef/fsd0a_a_generic_core.lef tech/lef/FSD0A_A_GENERIC_CORE_ANT_V55.lef" set rda_Input(ui_cts_cell_footprint) {} set rda_Input(ui_cts_cell_list) {} set rda_Input(ui_core_cntl) {aspect} set rda_Input(ui_aspect_ratio) {1.0} set rda_Input(ui_core_util) {0.8} set rda_Input(ui_core_height) {} set rda_Input(ui_core_width) {} set rda_Input(ui_core_to_left) {} set rda_Input(ui_core_to_right) {} set rda_Input(ui_core_to_top) {} set rda_Input(ui_core_to_bottom) {} set rda_Input(ui_max_io_height) {0} set rda_Input(ui_row_height) {} set rda_Input(ui_isHorTrackHalfPitch) {0} set rda_Input(ui_isVerTrackHalfPitch) {1} set rda_Input(ui_ioOri) {R0} set rda_Input(ui_isOrigCenter) {0} set rda_Input(ui_isVerticalRow) {0} set rda_Input(ui_exc_net) "" set rda_Input(ui_delay_limit) {1000} set rda_Input(ui_net_delay) {1000.0ps} set rda_Input(ui_net_load) {0.5pf} set rda_Input(ui_in_tran_delay) {100.0ps} set rda_Input(ui_captbl_file) "tech/UMCL90_8m026.capTbl" set rda_Input(ui_defcap_scale) {1.0} set rda_Input(ui_detcap_scale) {1.0} set rda_Input(ui_xcap_scale) {1.0} set rda_Input(ui_res_scale) {1.0} set rda_Input(ui_shr_scale) {1.0} set rda_Input(ui_rel_c_thresh) {0.03} set rda_Input(ui_tot_c_thresh) {5.0} set rda_Input(ui_time_unit) {none} set rda_Input(ui_cap_unit) {} set rda_Input(ui_oa_reflib) "" set rda_Input(ui_oa_abstractname) {} set rda_Input(ui_oa_layoutname) {} set rda_Input(ui_sigstormlib) "" set rda_Input(ui_cdb_file,min) "" set rda_Input(ui_cdb_file,max) "" set rda_Input(ui_cdb_file) "" set rda_Input(ui_echo_file,min) "" set rda_Input(ui_echo_file,max) "" set rda_Input(ui_echo_file) "" set rda_Input(ui_xtwf_file) "" set rda_Input(ui_qxtech_file) "tech/G-DF-LOGIC90N-1P9M2T1F-LOW_K_POLY1.5K_FIRE_AND_ICE-LPE-T.3-P2.RCgen.tch" set rda_Input(ui_qxlayermap_file) "" set rda_Input(ui_qxlib_file) "" set rda_Input(ui_qxconf_file) "" set rda_Input(ui_pwrnet) {VCCK} set rda_Input(ui_gndnet) {GNDK} set rda_Input(flip_first) {1} set rda_Input(double_back) {1} set rda_Input(assign_buffer) {1} set rda_Input(ui_pg_connections) "" set rda_Input(ui_gen_footprint) {0} ## aditions for power flow set_rail_analysis_mode -method static -power_switch_eco false -accuracy accurate \ -power_grid_library {tech/cl/fsd0a_a_generic_core.8m026.cl tech/cl/fod0a_b25_t25_generic_io.8m026.cl} \ -em_models tech/EM.8m026.models -vsrc_search_distance 50 \ -report_via_current_direction false set ::Eps::option(epsCommaPwrLib) {tech/cl/fsd0a_a_generic_core.8m026.cl tech/cl/fod0a_b25_t25_generic_io.8m026.cl}