Checking out Encounter license ...
Encounter_Digital_Impl_Sys_XL 10.1 license checkout succeeded.
You can run 2 CPU jobs with the base license that is currently checked out.
If required, use the setMultiCpuUsage command to enable multi-CPU processing.
This Encounter release has been compiled with OA version 22.04-p011.
*******************************************************************
* Copyright (c) Cadence Design Systems, Inc. 1996 - 2011. *
* All rights reserved. *
* *
* *
* *
* This program contains confidential and trade secret information *
* of Cadence Design Systems, Inc. and is protected by copyright *
* law and international treaties. Any reproduction, use, *
* distribution or disclosure of this program or any portion of it,*
* or any attempt to obtain a human-readable version of this *
* program, without the express, prior written consent of *
* Cadence Design Systems, Inc., is strictly prohibited. *
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*******************************************************************
@(#)CDS: Encounter v10.12-s181_1 (64bit) 07/28/2011 22:52 (Linux 2.6)
@(#)CDS: NanoRoute v10.12-s010 NR110720-1815/10_10_USR2-UB (database version 2.30, 124.2.1) {superthreading v1.15}
@(#)CDS: CeltIC v10.12-s013_1 (64bit) 07/27/2011 04:14:35 (Linux 2.6.9-89.0.19.ELsmp)
@(#)CDS: AAE 10.12-s001 (64bit) 07/28/2011 (Linux 2.6.9-89.0.19.ELsmp)
@(#)CDS: CTE 10.12-s010_1 (64bit) Jul 18 2011 22:58:43 (Linux 2.6.9-89.0.19.ELsmp)
@(#)CDS: CPE v10.12-s007
--- Starting "Encounter v10.12-s181_1" on Thu Sep 29 11:20:20 2011 (mem=60.0M) ---
--- Running on aotearoa.ee.ethz.ch (x86_64 w/Linux 2.6.18-238.5.1.el5) ---
This version was compiled on Thu Jul 28 22:52:33 PDT 2011.
Set DBUPerIGU to 1000.
Set net toggle Scale Factor to 1.00
Set Shrink Factor to 1.00000
Sourcing ./enc.tcl
Sourcing tcl/tk file "./enc.tcl" ...
setDelayCalMode -engine signalStorm
set_global report_timing_format {instance arc cell slew load delay arrival}
set_global timing_defer_mmmc_object_updates true
setDoAssign on -buffer BUFM2W
setDesignMode -process 65
Applying the recommended capacitance filtering threshold values for 65nm process node: total_c_th=0, relative_c_th=1 and coupling_c_th=0.1.
These values will be used by all post-route extraction engines, including TQRC, IQRC and QRC extraction.
Capacitance filtering mode(-capFilterMode option of the setExtractRCMode) is 'relAndCoup' for all engines.
The accuracy mode for detail extraction will be set to 'high'.
Default value for EffortLevel(-effortLevel option of the setExtractRCMode) in postRoute extraction mode will be 'medium' if QRC technology file is specified else 'low'.
win
setTrialRouteMode -useM1 true
setMultiCpuUsage -localCpu max
loadConfig ./src/shabziger.conf 0
Reading config file - ./src/shabziger.conf
**WARN: (ENCSYT-709): The next major release of EDI (11.1) will use the
Multi-Mode/Multi-Corner (MMMC) architecture exclusively for configuration and
control of some software features. The current configuration will continue to
work in this release. But for compatibility with the future releases you
should migrate your design to an MMMC style configuration. You can refer to
the What's New document for this release for additional information on the
11.1 migration to MMMC. In addition, you can run loadConfig with the
-showEolWarnings option to identify specific command and configuration
options that will no longer be supported.
create_library_set -name best_libs -timing {tech/lib/u065gioll25mvir_25_bc.lib tech/lib/uk65lscllmvbbl_132c0_bc.lib tech/lib/uk65lscllmvbbr_132c0_bc.lib tech/lib/uk65lscllmvbbh_132c0_bc.lib tech/lib/SHKA65_16384X32X1CM16_BC.lib tech/lib/SHKA65_2048X32X1CM4_BC.lib tech/lib/SYKA65_2048X32X1CM8_BC.lib}
create_library_set -name worst_libs -timing {tech/lib/u065gioll25mvir_25_wc.lib tech/lib/uk65lscllmvbbl_108c125_wc.lib tech/lib/uk65lscllmvbbr_108c125_wc.lib tech/lib/uk65lscllmvbbh_108c125_wc.lib tech/lib/SHKA65_16384X32X1CM16_WC.lib tech/lib/SHKA65_2048X32X1CM4_WC.lib tech/lib/SYKA65_2048X32X1CM8_WC.lib}
create_rc_corner -name rc_worst -cap_table tech/u65ll_RCMAX.captbl
create_rc_corner -name rc_best -cap_table tech/u65ll_RCMIN.captbl
create_delay_corner -name best_corn -library_set best_libs -rc_corner rc_best
create_delay_corner -name worst_corn -library_set worst_libs -rc_corner rc_worst
create_constraint_mode -name ${mode}_mode -sdc_files [list src/shabziger_mmmc_${mode}.sdc src/shabziger_mmmc_shared.sdc ]
create_analysis_view -name ${mode}_slow_view -constraint_mode ${mode}_mode -delay_corner worst_corn
create_constraint_mode -name ${mode}_mode -sdc_files [list src/shabziger_mmmc_${mode}.sdc src/shabziger_mmmc_shared.sdc ]
create_analysis_view -name ${mode}_slow_view -constraint_mode ${mode}_mode -delay_corner worst_corn
create_constraint_mode -name ${mode}_mode -sdc_files [list src/shabziger_mmmc_${mode}.sdc src/shabziger_mmmc_shared.sdc ]
create_analysis_view -name ${mode}_slow_view -constraint_mode ${mode}_mode -delay_corner worst_corn
create_constraint_mode -name ${mode}_mode -sdc_files [list src/shabziger_mmmc_${mode}.sdc src/shabziger_mmmc_shared.sdc ]
create_analysis_view -name ${mode}_slow_view -constraint_mode ${mode}_mode -delay_corner worst_corn
create_constraint_mode -name ${mode}_mode -sdc_files [list src/shabziger_mmmc_${mode}.sdc src/shabziger_mmmc_shared.sdc ]
create_analysis_view -name ${mode}_slow_view -constraint_mode ${mode}_mode -delay_corner worst_corn
create_constraint_mode -name ${mode}_mode -sdc_files [list src/shabziger_mmmc_${mode}.sdc src/shabziger_mmmc_shared.sdc ]
create_analysis_view -name ${mode}_slow_view -constraint_mode ${mode}_mode -delay_corner worst_corn
create_constraint_mode -name ${mode}_mode -sdc_files [list src/shabziger_mmmc_${mode}.sdc src/shabziger_mmmc_shared.sdc ]
create_analysis_view -name ${mode}_slow_view -constraint_mode ${mode}_mode -delay_corner worst_corn
create_constraint_mode -name ${mode}_mode -sdc_files [list src/shabziger_mmmc_${mode}.sdc src/shabziger_mmmc_shared.sdc ]
create_analysis_view -name ${mode}_slow_view -constraint_mode ${mode}_mode -delay_corner worst_corn
create_constraint_mode -name ${mode}_mode -sdc_files [list src/shabziger_mmmc_${mode}.sdc src/shabziger_mmmc_shared.sdc ]
create_analysis_view -name ${mode}_slow_view -constraint_mode ${mode}_mode -delay_corner worst_corn
create_constraint_mode -name ${mode}_mode -sdc_files [list src/shabziger_mmmc_${mode}.sdc src/shabziger_mmmc_shared.sdc ]
create_analysis_view -name ${mode}_slow_view -constraint_mode ${mode}_mode -delay_corner worst_corn
create_constraint_mode -name ${mode}_mode -sdc_files [list src/shabziger_mmmc_${mode}.sdc src/shabziger_mmmc_shared.sdc ]
create_analysis_view -name ${mode}_slow_view -constraint_mode ${mode}_mode -delay_corner worst_corn
create_constraint_mode -name ${mode}_mode -sdc_files [list src/shabziger_mmmc_${mode}.sdc src/shabziger_mmmc_shared.sdc ]
create_analysis_view -name ${mode}_slow_view -constraint_mode ${mode}_mode -delay_corner worst_corn
create_constraint_mode -name ${mode}_mode -sdc_files [list src/shabziger_mmmc_${mode}.sdc src/shabziger_mmmc_shared.sdc ]
create_analysis_view -name ${mode}_slow_view -constraint_mode ${mode}_mode -delay_corner worst_corn
create_constraint_mode -name ${mode}_mode -sdc_files [list src/shabziger_mmmc_${mode}.sdc src/shabziger_mmmc_shared.sdc ]
create_analysis_view -name ${mode}_slow_view -constraint_mode ${mode}_mode -delay_corner worst_corn
create_constraint_mode -name ${mode}_mode -sdc_files [list src/shabziger_mmmc_${mode}.sdc src/shabziger_mmmc_shared.sdc ]
create_analysis_view -name ${mode}_slow_view -constraint_mode ${mode}_mode -delay_corner worst_corn
create_constraint_mode -name ${mode}_mode -sdc_files [list src/shabziger_mmmc_${mode}.sdc src/shabziger_mmmc_shared.sdc ]
create_analysis_view -name ${mode}_slow_view -constraint_mode ${mode}_mode -delay_corner worst_corn
create_constraint_mode -name ${mode}_mode -sdc_files [list src/shabziger_mmmc_${mode}.sdc src/shabziger_mmmc_shared.sdc ]
create_analysis_view -name ${mode}_slow_view -constraint_mode ${mode}_mode -delay_corner worst_corn
create_analysis_view -name hold_fast_view -constraint_mode test_mode -delay_corner best_corn
set_analysis_view -setup $view_list -hold {hold_fast_view}
commitConfig
Loading Lef file tech/lef/u65ll_8m1t0f1u_V56.lef...
WARNING (LEFPARS-2007): NAMESCASESENSITIVE statement is obsolete in version 5.6 and later.
The LEF parser will ignore this statement.
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file tech/lef/u65ll_8m1t0f1u_V56.lef at line 24.
WARNING (LEFPARS-2009): USEMINSPACING PIN statement is obsolete in version 5.6 or later.
The USEMINSPACING PIN statement will be ignored. See file tech/lef/u65ll_8m1t0f1u_V56.lef at line 41.
Loading Lef file tech/lef/uk65lscllmvbbr.lef...
**WARN: (ENCLF-246): The 'UNITS' attribute should be set
in the first lef file (technology lef). There is an attempt to set it
in subsequent lef files which will be ignored.
**WARN: (ENCLF-108): There is no overlap layer defined in any lef file
so you are unable to create rectilinear partition in a hierarchical flow.
Set DBUPerIGU to M2 pitch 200.
Loading Lef file tech/lef/uk65lscllmvbbl.lef...
**WARN: (ENCLF-246): The 'UNITS' attribute should be set
in the first lef file (technology lef). There is an attempt to set it
in subsequent lef files which will be ignored.
Loading Lef file tech/lef/uk65lscllmvbbh.lef...
**WARN: (ENCLF-246): The 'UNITS' attribute should be set
in the first lef file (technology lef). There is an attempt to set it
in subsequent lef files which will be ignored.
Loading Lef file tech/lef/u065gioll25mvir_8m1t0f1u.lef...
Loading Lef file tech/lef/SHKA65_16384X32X1CM16.lef...
Loading Lef file tech/lef/SHKA65_2048X32X1CM4.lef...
Loading Lef file tech/lef/SYKA65_2048X32X1CM8.lef...
**WARN: (ENCLF-200): Pin 'ANAIOC' in macro 'DI_GC' has no ANTENNAGATEAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (ENCLF-200): Pin 'ANAIO' in macro 'DI_GIO' has no ANTENNAGATEAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (ENCLF-200): Pin 'ANAIOC' in macro 'DI_PC' has no ANTENNAGATEAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (ENCLF-200): Pin 'ANAIO' in macro 'DI_PIO' has no ANTENNAGATEAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (ENCLF-200): Pin 'ANAIO' in macro 'IANAIO' has no ANTENNAGATEAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (ENCLF-200): Pin 'ANAIOC' in macro 'IANAIOC' has no ANTENNAGATEAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (ENCLF-200): Pin 'A' in macro 'ANTS' has no ANTENNAGATEAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (ENCLF-200): Pin 'A' in macro 'ANTW' has no ANTENNAGATEAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (ENCLF-200): Pin 'A' in macro 'ANTR' has no ANTENNAGATEAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
Power Planner/ViaGen version 8.1.46 promoted on 02/17/2009.
viaInitial starts at Thu Sep 29 11:20:43 2011
viaInitial ends at Thu Sep 29 11:20:43 2011
Reading netlist ...
Backslashed names will retain backslash and a trailing blank character.
Reading verilog netlist '../synopsys/netlists/shabziger_chip.v'
Inserting buffer (BUFM2W) to remove assignment statements.
*** Memory Usage v#8 (Current mem = 428.730M, initial mem = 59.977M) ***
*** End netlist parsing (cpu=0:00:03.0, real=0:00:04.0, mem=428.7M) ***
Top level cell is shabziger_chip.
Reading common timing library 'tech/lib/u065gioll25mvir_25_wc.lib' ...
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'OUTPUT' of cell 'ICLOCK' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_capacitance' on 'output/inout' pin 'VDD' of cell 'ICLOCK' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'VDD' of cell 'ICLOCK' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_capacitance' on 'output/inout' pin 'VSS' of cell 'ICLOCK' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'VSS' of cell 'ICLOCK' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'XO' of cell 'IOSC' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'XOUT' of cell 'IOSC' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_capacitance' on 'output/inout' pin 'VDD' of cell 'IOSC' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'VDD' of cell 'IOSC' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_capacitance' on 'output/inout' pin 'VSS' of cell 'IOSC' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'VSS' of cell 'IOSC' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_capacitance' on 'output/inout' pin 'VDDIO' of cell 'IOSC' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'VDDIO' of cell 'IOSC' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_capacitance' on 'output/inout' pin 'VSSIO' of cell 'IOSC' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'VSSIO' of cell 'IOSC' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'DI' of cell 'IUMA' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'PAD' of cell 'IUMA' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_capacitance' on 'output/inout' pin 'VDD' of cell 'IUMA' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'VDD' of cell 'IUMA' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_capacitance' on 'output/inout' pin 'VSS' of cell 'IUMA' is not defined in the library.
Message has exceeded the message display limit of '20'. setMessageLimit/set_message_limit sets the limit. unsetMessageLimit/unset_message_limit can be used to reset this.
read 42 cells in library 'u065gioll25mvir_25_wc'
Reading common timing library 'tech/lib/uk65lscllmvbbl_108c125_wc.lib' ...
No function defined for cell 'FILEP64W'. The cell will only be used for analysis.
No function defined for cell 'FILEP32W'. The cell will only be used for analysis.
No function defined for cell 'FILEP16W'. The cell will only be used for analysis.
No function defined for cell 'FILEP8W'. The cell will only be used for analysis.
No function defined for cell 'FILE64W'. The cell will only be used for analysis.
No function defined for cell 'FILE32W'. The cell will only be used for analysis.
No function defined for cell 'FILE16W'. The cell will only be used for analysis.
No function defined for cell 'FILE8W'. The cell will only be used for analysis.
No function defined for cell 'FILE6W'. The cell will only be used for analysis.
No function defined for cell 'FILE4W'. The cell will only be used for analysis.
No function defined for cell 'FILE3W'. The cell will only be used for analysis.
No function defined for cell 'ANTW'. The cell will only be used for analysis.
read 1077 cells in library 'uk65lscllmvbbl_108c125_wc'
Reading common timing library 'tech/lib/uk65lscllmvbbr_108c125_wc.lib' ...
No function defined for cell 'FILEP64R'. The cell will only be used for analysis.
No function defined for cell 'FILEP32R'. The cell will only be used for analysis.
No function defined for cell 'FILEP16R'. The cell will only be used for analysis.
No function defined for cell 'FILEP8R'. The cell will only be used for analysis.
No function defined for cell 'FILE64R'. The cell will only be used for analysis.
No function defined for cell 'FILE32R'. The cell will only be used for analysis.
No function defined for cell 'FILE16R'. The cell will only be used for analysis.
No function defined for cell 'FILE8R'. The cell will only be used for analysis.
Message has exceeded the message display limit of '20'. setMessageLimit/set_message_limit sets the limit. unsetMessageLimit/unset_message_limit can be used to reset this.
read 1077 cells in library 'uk65lscllmvbbr_108c125_wc'
Reading common timing library 'tech/lib/uk65lscllmvbbh_108c125_wc.lib' ...
read 1077 cells in library 'uk65lscllmvbbh_108c125_wc'
Reading common timing library 'tech/lib/SHKA65_16384X32X1CM16_WC.lib' ...
read 1 cells in library 'SHKA65_16384X32X1CM16_WC'
Reading common timing library 'tech/lib/SHKA65_2048X32X1CM4_WC.lib' ...
read 1 cells in library 'SHKA65_2048X32X1CM4_WC'
Reading common timing library 'tech/lib/SYKA65_2048X32X1CM8_WC.lib' ...
read 1 cells in library 'SYKA65_2048X32X1CM8_WC'
*** End library_loading (cpu=3.46min, mem=260.0M, fe_cpu=3.57min, fe_mem=688.9M) ***
Starting recursive module instantiation check.
No recursion found.
Building hierarchical netlist for Cell shabziger_chip ...
*** Netlist is unique.
** info: there are 3368 modules.
** info: there are 253560 stdCell insts.
** info: there are 60 Pad insts.
** info: there are 3 macros.
*** Memory Usage v#8 (Current mem = 879.883M, initial mem = 59.977M) ***
CTE reading timing constraint file '.constr.9079.pt' ...
Number of path exceptions in the constraint file = 4
Number of paths exceptions after getting compressed = 2
INFO (CTE): constraints read successfully
*** Read timing constraints (cpu=0:00:18.2 mem=990.4M) ***
Total number of combinational cells: 2004
Total number of sequential cells: 1182
Total number of tristate cells: 45
Total number of level shifter cells: 0
Total number of power gating cells: 0
Total number of isolation cells: 0
Total number of power switch cells: 0
Total number of pulse generator cells: 0
Total number of always on buffers: 0
Total number of retention cells: 0
List of usable buffers: BUFM2S BUFM4S BUFM3S BUFM6S BUFM5S BUFM8S BUFM10S BUFM12S BUFM14S BUFM16S BUFM18S BUFM22SA BUFM20S BUFM24S BUFM26SA BUFM32SA BUFM40SA BUFM48SA CKBUFM2S CKBUFM1S CKBUFM4S CKBUFM3S CKBUFM6S CKBUFM8S CKBUFM12S CKBUFM16S CKBUFM20S CKBUFM22SA CKBUFM24S CKBUFM26SA CKBUFM32S CKBUFM40S CKBUFM48S BUFM2R BUFM4R BUFM3R BUFM6R BUFM5R BUFM8R BUFM10R BUFM12R BUFM14R BUFM16R BUFM18R BUFM22RA BUFM20R BUFM24R BUFM26RA BUFM32RA BUFM40RA BUFM48RA CKBUFM2R CKBUFM1R CKBUFM4R CKBUFM3R CKBUFM6R CKBUFM8R CKBUFM12R CKBUFM16R CKBUFM20R CKBUFM22RA CKBUFM24R CKBUFM26RA CKBUFM32R CKBUFM40R CKBUFM48R DEL1M4R BUFM2W BUFM4W BUFM3W BUFM6W BUFM5W BUFM8W BUFM10W BUFM12W BUFM14W BUFM16W BUFM18W BUFM22WA BUFM20W BUFM24W BUFM26WA BUFM32WA BUFM40WA BUFM48WA CKBUFM2W CKBUFM1W CKBUFM4W CKBUFM3W CKBUFM6W CKBUFM8W CKBUFM12W CKBUFM16W CKBUFM20W CKBUFM22WA CKBUFM24W CKBUFM26WA CKBUFM32W CKBUFM40W CKBUFM48W DEL1M1W DEL1M4W
Total number of usable buffers: 102
List of unusable buffers:
Total number of unusable buffers: 0
List of usable inverters: CKINVM2S CKINVM1S CKINVM4S CKINVM3S CKINVM6S CKINVM8S CKINVM12S CKINVM16S CKINVM20S CKINVM22SA CKINVM24S CKINVM26SA CKINVM32S CKINVM40S CKINVM48S INVM2S INVM1S INVM4S INVM3S INVM6S INVM5S INVM8S INVM10S INVM12S INVM14S INVM16S INVM18S INVM20S INVM22SA INVM24S INVM26SA INVM32S INVM40S INVM48S CKINVM2R CKINVM1R CKINVM4R CKINVM3R CKINVM6R CKINVM8R CKINVM12R CKINVM16R CKINVM20R CKINVM22RA CKINVM24R CKINVM26RA CKINVM32R CKINVM40R CKINVM48R INVM2R INVM1R INVM4R INVM3R INVM6R INVM5R INVM8R INVM10R INVM12R INVM14R INVM16R INVM18R INVM20R INVM22RA INVM24R INVM26RA INVM32R INVM40R INVM48R CKINVM2W CKINVM1W CKINVM4W CKINVM3W CKINVM6W CKINVM8W CKINVM12W CKINVM16W CKINVM20W CKINVM22WA CKINVM24W CKINVM26WA CKINVM32W CKINVM40W CKINVM48W INVM2W INVM1W INVM4W INVM3W INVM6W INVM5W INVM8W INVM10W INVM12W INVM14W INVM16W INVM18W INVM20W INVM22WA INVM24W INVM26WA INVM32W INVM40W INVM48W
Total number of usable inverters: 102
List of unusable inverters: REGKM2S REGKM1S REGKM4S REGKM2R REGKM1R REGKM4R REGKM2W REGKM1W REGKM4W INVM0S INVM0R INVM0W
Total number of unusable inverters: 12
List of identified usable delay cells: DEL1M1S DEL1M4S DEL2M1S DEL2M4S DEL3M1S DEL3M4S DEL4M1S DEL4M4S DEL1M1R DEL2M1R DEL2M4R DEL3M1R DEL3M4R DEL4M1R DEL4M4R DEL2M1W DEL2M4W DEL3M1W DEL3M4W DEL4M1W DEL4M4W
Total number of identified usable delay cells: 21
List of identified unusable delay cells:
Total number of identified unusable delay cells: 0
*info: set bottom ioPad orient R0
Reading IO assignment file "src/shabziger.io" ...
Set Using Default Delay Limit as 1000.
Set Default Net Delay as 1000 ps.
Set Default Net Load as 0.5 pF.
Set Input Pin Transition Delay as 0.1 ps.
PreRoute Cap Scale Factor : 1.00
PreRoute Res Scale Factor : 1.00
PostRoute Cap Scale Factor : 1.00
PostRoute Res Scale Factor : 1.00
PostRoute XCap Scale Factor : 1.00
PreRoute Clock Cap Scale Factor : 1.00 [Derived from postRoute_cap (effortLevel low)]
PreRoute Clock Res Scale Factor : 1.00 [Derived from postRoute_res (effortLevel low)]
PostRoute Clock Cap Scale Factor : 1.00 [Derived from postRoute_cap (effortLevel low)]
PostRoute Clock Res Scale Factor : 1.00 [Derived from postRoute_res (effortLevel low)]
Set XCapacitance Thresholds: total_c_threshold to 5.00 [fF], and relative_c_threshold to 0.03
Pre-connect netlist-defined P/G connections...
**WARN: (ENCDB-1256): Power pin VDDIO of instance pad_DataOut15 is connected to non-p/g net VDDIO. Mark the net as power net and create associated snet.
**WARN: (ENCDB-1257): Ground pin VSSIO of instance pad_DataOut15 is connected to non-p/g net VSSIO. Mark the net as ground net and create associated snet.
Updated 60 instances.
DC Corner worst_corn, is equivalent to worst_corn.
DC Corner worst_corn, is equivalent to worst_corn.
DC Corner worst_corn, is equivalent to worst_corn.
DC Corner worst_corn, is equivalent to worst_corn.
DC Corner worst_corn, is equivalent to worst_corn.
DC Corner worst_corn, is equivalent to worst_corn.
DC Corner worst_corn, is equivalent to worst_corn.
DC Corner worst_corn, is equivalent to worst_corn.
DC Corner worst_corn, is equivalent to worst_corn.
DC Corner worst_corn, is equivalent to worst_corn.
DC Corner worst_corn, is equivalent to worst_corn.
DC Corner worst_corn, is equivalent to worst_corn.
DC Corner worst_corn, is equivalent to worst_corn.
DC Corner worst_corn, is equivalent to worst_corn.
DC Corner worst_corn, is equivalent to worst_corn.
DC Corner worst_corn, is equivalent to worst_corn.
Mem message Memory info before deleting aae data base (MEM=905.5M)
Mem message Memory info after deleting aae data base (MEM=905.5M)
Initializing multi-corner RC extraction with 2 active RC Corners ...
Reading Capacitance Table File tech/u65ll_RCMAX.captbl ...
Cap Table was created using Encounter 10.11-s096_1.
Process name: G_4J_LOGIC_MIXED_MODE65N_1P8M1T0F1U_LL_LOW_K_TOP_METAL32_5K_1_0_P1.
**WARN: (ENCEXT-2760): Layer M9 in the cap table is larger than max number of layers, 8, defined in the LEF file.
**WARN: (ENCEXT-2771): Top layer, M9, of Via ALVIA in the cap table is larger than max number of layers, 8, defined in the LEF file.
Allocated an empty WireEdgeEnlargement table in rc_worst [8]
**WARN: (ENCEXT-2710): Cap table for M9 is ignored, the layer is not defined in the design.
Reading Capacitance Table File tech/u65ll_RCMIN.captbl ...
Cap Table was created using Encounter 10.11-s096_1.
Process name: G_4J_LOGIC_MIXED_MODE65N_1P8M1T0F1U_LL_LOW_K_TOP_METAL32_5K_1_0_P1.
**WARN: (ENCEXT-2760): Layer M9 in the cap table is larger than max number of layers, 8, defined in the LEF file.
**WARN: (ENCEXT-2771): Top layer, M9, of Via ALVIA in the cap table is larger than max number of layers, 8, defined in the LEF file.
Allocated an empty WireEdgeEnlargement table in rc_best [8]
**WARN: (ENCEXT-2710): Cap table for M9 is ignored, the layer is not defined in the design.
Importing multi-corner RC tables ...
Summary of Active RC-Corners :
Analysis View: dummy_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: ethz_blake_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: ethz_groestl_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: ethz_jh_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: ethz_keccak_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: ethz_sha2_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: ethz_skein_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: gmu_blake_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: gmu_groestl_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: gmu_jh_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: gmu_keccak_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: gmu_sha2_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: gmu_skein_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: ram1_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: ram2_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: ram3_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: test_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: hold_fast_view
RC-Corner Name : rc_best
RC-Corner Index : 1
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMIN.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
*Info: initialize multi-corner CTS.
Reading best_libs timing library '/usr/pack/umc-65-kgf/umc/ll/u065gioll25mvir/a03/synopsys/u065gioll25mvir_25_bc.lib' ...
read 42 cells in library 'u065gioll25mvir_25_bc'
Reading best_libs timing library '/usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbl/a02/synopsys/uk65lscllmvbbl_132c0_bc.lib' ...
read 1077 cells in library 'uk65lscllmvbbl_132c0_bc'
Reading best_libs timing library '/usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbr/a02/synopsys/uk65lscllmvbbr_132c0_bc.lib' ...
read 1077 cells in library 'uk65lscllmvbbr_132c0_bc'
Reading best_libs timing library '/usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbh/a02/synopsys/uk65lscllmvbbh_132c0_bc.lib' ...
read 1077 cells in library 'uk65lscllmvbbh_132c0_bc'
Reading best_libs timing library '/usr/pack/umc-65-kgf/faraday/ll/memaker/200901.1.2/outputs.dz/SHKA65_16384X32X1CM16/SHKA65_16384X32X1CM16_BC.lib' ...
read 1 cells in library 'SHKA65_16384X32X1CM16_BC'
Reading best_libs timing library '/usr/pack/umc-65-kgf/faraday/ll/memaker/200901.1.2/outputs.dz/SHKA65_2048X32X1CM4/SHKA65_2048X32X1CM4_BC.lib' ...
read 1 cells in library 'SHKA65_2048X32X1CM4_BC'
Reading best_libs timing library '/usr/pack/umc-65-kgf/faraday/ll/memaker/200901.1.2/outputs.dz/SYKA65_2048X32X1CM8/SYKA65_2048X32X1CM8_BC.lib' ...
read 1 cells in library 'SYKA65_2048X32X1CM8_BC'
CTE reading timing constraint file 'src/shabziger_mmmc_gmu_keccak.sdc' ...
Number of path exceptions in the constraint file = 3
Number of paths exceptions after getting compressed = 2
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_gmu_skein.sdc' ...
Number of path exceptions in the constraint file = 2
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_ethz_blake.sdc' ...
Number of path exceptions in the constraint file = 2
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_ethz_sha2.sdc' ...
Number of path exceptions in the constraint file = 3
Number of paths exceptions after getting compressed = 2
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_gmu_groestl.sdc' ...
Number of path exceptions in the constraint file = 3
Number of paths exceptions after getting compressed = 2
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_ram3.sdc' ...
Number of path exceptions in the constraint file = 2
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_ethz_groestl.sdc' ...
Number of path exceptions in the constraint file = 3
Number of paths exceptions after getting compressed = 2
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_ram2.sdc' ...
Number of path exceptions in the constraint file = 2
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_dummy.sdc' ...
Number of path exceptions in the constraint file = 3
Number of paths exceptions after getting compressed = 2
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_gmu_blake.sdc' ...
Number of path exceptions in the constraint file = 2
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_gmu_sha2.sdc' ...
Number of path exceptions in the constraint file = 3
Number of paths exceptions after getting compressed = 2
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_ethz_keccak.sdc' ...
Number of path exceptions in the constraint file = 3
Number of paths exceptions after getting compressed = 2
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_ram1.sdc' ...
Number of path exceptions in the constraint file = 2
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_ethz_skein.sdc' ...
Number of path exceptions in the constraint file = 2
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_ethz_jh.sdc' ...
Number of path exceptions in the constraint file = 3
Number of paths exceptions after getting compressed = 2
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_gmu_jh.sdc' ...
Number of path exceptions in the constraint file = 3
Number of paths exceptions after getting compressed = 2
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_test.sdc' ...
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
Total number of combinational cells: 2004
Total number of sequential cells: 1182
Total number of tristate cells: 45
Total number of level shifter cells: 0
Total number of power gating cells: 0
Total number of isolation cells: 0
Total number of power switch cells: 0
Total number of pulse generator cells: 0
Total number of always on buffers: 0
Total number of retention cells: 0
List of usable buffers: BUFM2S BUFM4S BUFM3S BUFM6S BUFM5S BUFM8S BUFM10S BUFM12S BUFM14S BUFM16S BUFM18S BUFM22SA BUFM20S BUFM24S BUFM26SA BUFM32SA BUFM40SA BUFM48SA CKBUFM2S CKBUFM1S CKBUFM4S CKBUFM3S CKBUFM6S CKBUFM8S CKBUFM12S CKBUFM16S CKBUFM20S CKBUFM22SA CKBUFM24S CKBUFM26SA CKBUFM32S CKBUFM40S CKBUFM48S BUFM2R BUFM4R BUFM3R BUFM6R BUFM5R BUFM8R BUFM10R BUFM12R BUFM14R BUFM16R BUFM18R BUFM22RA BUFM20R BUFM24R BUFM26RA BUFM32RA BUFM40RA BUFM48RA CKBUFM2R CKBUFM1R CKBUFM4R CKBUFM3R CKBUFM6R CKBUFM8R CKBUFM12R CKBUFM16R CKBUFM20R CKBUFM22RA CKBUFM24R CKBUFM26RA CKBUFM32R CKBUFM40R CKBUFM48R DEL1M4R BUFM2W BUFM4W BUFM3W BUFM6W BUFM5W BUFM8W BUFM10W BUFM12W BUFM14W BUFM16W BUFM18W BUFM22WA BUFM20W BUFM24W BUFM26WA BUFM32WA BUFM40WA BUFM48WA CKBUFM2W CKBUFM1W CKBUFM4W CKBUFM3W CKBUFM6W CKBUFM8W CKBUFM12W CKBUFM16W CKBUFM20W CKBUFM22WA CKBUFM24W CKBUFM26WA CKBUFM32W CKBUFM40W CKBUFM48W DEL1M1W DEL1M4W
Total number of usable buffers: 102
List of unusable buffers:
Total number of unusable buffers: 0
List of usable inverters: CKINVM2S CKINVM1S CKINVM4S CKINVM3S CKINVM6S CKINVM8S CKINVM12S CKINVM16S CKINVM20S CKINVM22SA CKINVM24S CKINVM26SA CKINVM32S CKINVM40S CKINVM48S INVM2S INVM1S INVM4S INVM3S INVM6S INVM5S INVM8S INVM10S INVM12S INVM14S INVM16S INVM18S INVM20S INVM22SA INVM24S INVM26SA INVM32S INVM40S INVM48S CKINVM2R CKINVM1R CKINVM4R CKINVM3R CKINVM6R CKINVM8R CKINVM12R CKINVM16R CKINVM20R CKINVM22RA CKINVM24R CKINVM26RA CKINVM32R CKINVM40R CKINVM48R INVM2R INVM1R INVM4R INVM3R INVM6R INVM5R INVM8R INVM10R INVM12R INVM14R INVM16R INVM18R INVM20R INVM22RA INVM24R INVM26RA INVM32R INVM40R INVM48R CKINVM2W CKINVM1W CKINVM4W CKINVM3W CKINVM6W CKINVM8W CKINVM12W CKINVM16W CKINVM20W CKINVM22WA CKINVM24W CKINVM26WA CKINVM32W CKINVM40W CKINVM48W INVM2W INVM1W INVM4W INVM3W INVM6W INVM5W INVM8W INVM10W INVM12W INVM14W INVM16W INVM18W INVM20W INVM22WA INVM24W INVM26WA INVM32W INVM40W INVM48W
Total number of usable inverters: 102
List of unusable inverters: REGKM2S REGKM1S REGKM4S REGKM2R REGKM1R REGKM4R REGKM2W REGKM1W REGKM4W INVM0S INVM0R INVM0W
Total number of unusable inverters: 12
List of identified usable delay cells: DEL1M1S DEL1M4S DEL2M1S DEL2M4S DEL3M1S DEL3M4S DEL4M1S DEL4M4S DEL1M1R DEL2M1R DEL2M4R DEL3M1R DEL3M4R DEL4M1R DEL4M4R DEL2M1W DEL2M4W DEL3M1W DEL3M4W DEL4M1W DEL4M4W
Total number of identified usable delay cells: 21
List of identified unusable delay cells:
Total number of identified unusable delay cells: 0
floorPlan -site CORE -d 1875 1875 60 60 60 60
**WARN: (ENCFP-325): After proportional resize, all pre-routed wires will be removed.
addIoFiller -cell IFILLER30 -prefix fillperi
Added 28 of filler cell 'IFILLER30' on top side.
Added 28 of filler cell 'IFILLER30' on left side.
Added 28 of filler cell 'IFILLER30' on bottom side.
Added 28 of filler cell 'IFILLER30' on right side.
addIoFiller -cell IFILLER20 -prefix fillperi
Added 0 of filler cell 'IFILLER20' on top side.
Added 0 of filler cell 'IFILLER20' on left side.
Added 0 of filler cell 'IFILLER20' on bottom side.
Added 0 of filler cell 'IFILLER20' on right side.
addIoFiller -cell IFILLER10 -prefix fillperi
Added 0 of filler cell 'IFILLER10' on top side.
Added 0 of filler cell 'IFILLER10' on left side.
Added 0 of filler cell 'IFILLER10' on bottom side.
Added 0 of filler cell 'IFILLER10' on right side.
addIoFiller -cell IFILLER5 -prefix fillperi
Added 2 of filler cell 'IFILLER5' on top side.
Added 2 of filler cell 'IFILLER5' on left side.
Added 2 of filler cell 'IFILLER5' on bottom side.
Added 2 of filler cell 'IFILLER5' on right side.
addIoFiller -cell IFILLER1 -prefix fillperi
Added 6 of filler cell 'IFILLER1' on top side.
Added 6 of filler cell 'IFILLER1' on left side.
Added 6 of filler cell 'IFILLER1' on bottom side.
Added 6 of filler cell 'IFILLER1' on right side.
addIoFiller -cell IFILLER0 -prefix fillperi
Added 14 of filler cell 'IFILLER0' on top side.
Added 14 of filler cell 'IFILLER0' on left side.
Added 14 of filler cell 'IFILLER0' on bottom side.
Added 14 of filler cell 'IFILLER0' on right side.
redraw
fit
setObjFPlanBox Instance top/i_RAM3 168.0 1110.975 790.36 1710.2
setObjFPlanBox Instance top/i_RAM2 1481.65 1373.375 1696.051 1710.2
setObjFPlanBox Instance top/i_RAM1 1081.19 1517.33 1419.899 1710.2
addHaloToBlock 10 10 10 10 top/i_RAM1
selectInst top/i_RAM1
dbSet selected.pStatus fixed
addHaloToBlock 10 10 10 10 top/i_RAM2
selectInst top/i_RAM2
dbSet selected.pStatus fixed
addHaloToBlock 10 10 10 10 top/i_RAM3
selectInst top/i_RAM3
dbSet selected.pStatus fixed
createObstruct 148.8 1101.0 158.0 1110.975
createObstruct 148.8 1709.4 158.0 1720.2
createObstruct 1710.8 1711.0 1726.2 1720.2
createObstruct 1710.8 1363.375 1726.2 1374.6
cutRow
redraw
deleteAllPowerPreroutes
clearDrc
clearGlobalNets
Pre-connect netlist-defined P/G connections...
Updated 60 instances.
globalNetConnect VDD -type pgpin -pin VDD -inst *
globalNetConnect VSS -type pgpin -pin VSS -inst *
globalNetConnect VDD -type pgpin -pin VCC -inst i_RAM*
globalNetConnect VSS -type pgpin -pin GND -inst i_RAM*
globalNetConnect VDD -type tiehi
globalNetConnect VSS -type tielo
addRing -spacing_top 2 -spacing_bottom 2 -spacing_right 2 -spacing_left 2 -width_top 12 -width_bottom 12 -width_right 12 -width_left 12 -offset_top 2 -offset_bottom 2 -offset_right 2 -offset_left 2 -layer_top ME1 -layer_bottom ME1 -layer_right ME2 -layer_left ME2 -stacked_via_top_layer metal8 -stacked_via_bottom_layer metal1 -around core -follow core -use_wire_group 1 -nets {VSS VDD VSS VDD}
The power planner has cut rows, and such rows will be considered to be placement objects.
The power planner created 16 wires.
*** Ending Ring Generation (totcpu=0:00:00.0, real=0:00:00.0, mem=1565.9M) ***
addRing -spacing_top 2 -spacing_bottom 2 -spacing_right 2 -spacing_left 2 -width_top 12 -width_bottom 12 -width_right 12 -width_left 12 -offset_top 2 -offset_bottom 2 -offset_right 2 -offset_left 2 -layer_top ME3 -layer_bottom ME3 -layer_right ME4 -layer_left ME4 -stacked_via_top_layer metal8 -stacked_via_bottom_layer metal1 -around core -follow core -use_wire_group 1 -nets {VSS VDD VSS VDD}
The power planner has cut rows, and such rows will be considered to be placement objects.
The power planner created 16 wires.
*** Ending Ring Generation (totcpu=0:00:00.1, real=0:00:00.0, mem=1565.9M) ***
addRing -spacing_top 2 -spacing_bottom 2 -spacing_right 2 -spacing_left 2 -width_top 12 -width_bottom 12 -width_right 12 -width_left 12 -offset_top 2 -offset_bottom 2 -offset_right 2 -offset_left 2 -layer_top ME5 -layer_bottom ME5 -layer_right ME6 -layer_left ME6 -stacked_via_top_layer metal8 -stacked_via_bottom_layer metal1 -around core -follow core -use_wire_group 1 -nets {VSS VDD VSS VDD}
The power planner has cut rows, and such rows will be considered to be placement objects.
The power planner created 16 wires.
*** Ending Ring Generation (totcpu=0:00:00.1, real=0:00:00.0, mem=1565.9M) ***
addRing -spacing_top 2 -spacing_bottom 2 -spacing_right 2 -spacing_left 2 -width_top 12 -width_bottom 12 -width_right 12 -width_left 12 -offset_top 2 -offset_bottom 2 -offset_right 2 -offset_left 2 -layer_top ME7 -layer_bottom ME7 -layer_right ME8 -layer_left ME8 -stacked_via_top_layer metal8 -stacked_via_bottom_layer metal1 -around core -follow core -use_wire_group 1 -nets {VSS VDD VSS VDD}
**WARN: (ENCPP-193): The currently specified left spacing 2.0000 might create min enclosed area violation. The required min enclosed area for layer ME8 is 9.0000. To correct the violation, please increase the spacing to around 3.0500
**WARN: (ENCPP-193): The currently specified left spacing 2.0000 might create min enclosed area violation. The required min enclosed area for layer ME8 is 9.0000. To correct the violation, please increase the spacing to around 3.0500
**WARN: (ENCPP-193): The currently specified left spacing 2.0000 might create min enclosed area violation. The required min enclosed area for layer ME8 is 9.0000. To correct the violation, please increase the spacing to around 3.0500
**WARN: (ENCPP-193): The currently specified right spacing 2.0000 might create min enclosed area violation. The required min enclosed area for layer ME8 is 9.0000. To correct the violation, please increase the spacing to around 3.0500
**WARN: (ENCPP-193): The currently specified right spacing 2.0000 might create min enclosed area violation. The required min enclosed area for layer ME8 is 9.0000. To correct the violation, please increase the spacing to around 3.0500
**WARN: (ENCPP-193): The currently specified right spacing 2.0000 might create min enclosed area violation. The required min enclosed area for layer ME8 is 9.0000. To correct the violation, please increase the spacing to around 3.0500
The power planner has cut rows, and such rows will be considered to be placement objects.
The power planner created 16 wires.
*** Ending Ring Generation (totcpu=0:00:00.1, real=0:00:00.0, mem=1565.9M) ***
selectInst top/i_RAM3
addRing -spacing_top 2 -spacing_bottom 2 -spacing_right 2 -spacing_left 2 -width_top 3 -width_bottom 3 -width_right 3 -width_left 3 -offset_top 1 -offset_bottom 1 -offset_right 1 -offset_left 1 -layer_top ME1 -layer_bottom ME1 -layer_right ME2 -layer_left ME2 -stacked_via_top_layer ME8 -stacked_via_bottom_layer ME1 -bl 1 -rt 1 -around selected -jog_distance 0.1 -threshold 0.1 -type block_rings -use_wire_group 1 -nets {VSS VDD}
The power planner has cut rows, and such rows will be considered to be placement objects.
**WARN: (ENCPP-241): The wire segment at 792.96 1106.97 792.96 1714.20 cannot be extended because of a short or violation with instances/rows.
**WARN: (ENCPP-241): The wire segment at 797.96 1101.97 797.96 1719.20 cannot be extended because of a short or violation with instances/rows.
**WARN: (ENCPP-241): The wire segment at 1703.41 1369.38 1703.41 1714.20 cannot be extended because of a short or violation with instances/rows.
**WARN: (ENCPP-241): The wire segment at 1708.41 1364.38 1708.41 1719.20 cannot be extended because of a short or violation with instances/rows.
**WARN: (ENCPP-241): The wire segment at 1417.54 1513.33 1417.54 1714.20 cannot be extended because of a short or violation with instances/rows.
**WARN: (ENCPP-241): The wire segment at 1422.54 1508.33 1422.54 1719.20 cannot be extended because of a short or violation with instances/rows.
The power planner created 24 wires.
*** Ending Ring Generation (totcpu=0:00:00.1, real=0:00:00.0, mem=1567.7M) ***
selectInst top/i_RAM2
addRing -spacing_top 2 -spacing_bottom 2 -spacing_right 2 -spacing_left 2 -width_top 3 -width_bottom 3 -width_right 3 -width_left 3 -offset_top 1 -offset_bottom 1 -offset_right 1 -offset_left 1 -layer_top ME1 -layer_bottom ME1 -layer_right ME2 -layer_left ME2 -stacked_via_top_layer ME8 -stacked_via_bottom_layer ME1 -br 1 -lt 1 -around selected -jog_distance 0.1 -threshold 0.1 -type block_rings -use_wire_group 1 -nets {VSS VDD}
The power planner has cut rows, and such rows will be considered to be placement objects.
*** Ending Ring Generation (totcpu=0:00:00.1, real=0:00:00.0, mem=1567.7M) ***
selectInst top/i_RAM1
addRing -spacing_top 2 -spacing_bottom 2 -spacing_right 2 -spacing_left 2 -width_top 3 -width_bottom 3 -width_right 3 -width_left 3 -offset_top 1 -offset_bottom 1 -offset_right 1 -offset_left 1 -layer_top ME1 -layer_bottom ME1 -layer_right ME2 -layer_left ME2 -stacked_via_top_layer ME8 -stacked_via_bottom_layer ME1 -rt 1 -lt 1 -around selected -jog_distance 0.1 -threshold 0.1 -type block_rings -use_wire_group 1 -nets {VSS VDD}
The power planner has cut rows, and such rows will be considered to be placement objects.
*** Ending Ring Generation (totcpu=0:00:00.0, real=0:00:00.0, mem=1567.7M) ***
sroute -connect { padPin } -padPinPortConnect { allPort preferLayer } -padPinLayerRange {ME2 ME6} -allowJogging 1 -allowLayerChange 1 -targetViaTopLayer ME6 -crossoverViaTopLayer ME6
*** Begin SPECIAL ROUTE on Thu Sep 29 11:31:45 2011 ***
Sroute/fcroute version 8.1.46 promoted on 02/17/2009.
SPECIAL ROUTE ran on directory: /usr/zupo/dz4/kgf/projects/sha3/shabziger/encounter
SPECIAL ROUTE ran on machine: aotearoa.ee.ethz.ch (Linux 2.6.18-238.5.1.el5 Xeon 2.79Ghz)
Begin option processing ...
(from .sroute_9079.conf) srouteConnectPowerBump set to false
(from .sroute_9079.conf) routeSpecial set to true
(from .sroute_9079.conf) srouteConnectBlockPin set to false
(from .sroute_9079.conf) srouteConnectCorePin set to false
(from .sroute_9079.conf) srouteConnectStripe set to false
(from .sroute_9079.conf) srouteCrossoverViaTopLayer set to 6
(from .sroute_9079.conf) srouteFollowCorePinEnd set to 3
(from .sroute_9079.conf) srouteJogControl set to "preferWithChanges differentLayer"
(from .sroute_9079.conf) srouteMaxPadPinLayer set to 6
(from .sroute_9079.conf) srouteMinPadPinLayer set to 2
(from .sroute_9079.conf) sroutePadPinAllGeoms set to true
(from .sroute_9079.conf) sroutePadPinAllPorts set to true
(from .sroute_9079.conf) sroutePadPinPreferredLayer set to true
(from .sroute_9079.conf) sroutePreserveExistingRoutes set to true
(from .sroute_9079.conf) srouteTopTargetLayerLimit set to 6
End option processing: cpu: 0:00:00, real: 0:00:00, peak: 1982.00 megs.
Reading DB technology information...
**WARN: (ENCSR-2455): An unexpected implant layer:SPSHVT is found between layer:LPLUS and layer:CONT. Move the implant layer to the beginning or the end of LAYER section in the LEF tech file.
Finished reading DB technology information.
Reading floorplan and netlist information...
Finished reading floorplan and netlist information.
**WARN: Cap-table is found in the design, so the same information from LEF will be ignored.
Read in 24 layers, 8 routing layers, 0 overlap layer
Read in 3309 macros, 763 used
Read in 1008 components
745 core components: 745 unplaced, 0 placed, 0 fixed
256 pad components: 0 unplaced, 200 placed, 56 fixed
3 block/ring components: 0 unplaced, 0 placed, 3 fixed
4 other components: 0 unplaced, 0 placed, 4 fixed
Read in 40 logical pins
Read in 4 blockages
Read in 40 nets
Read in 4 special nets, 2 routed
Read in 2124 terminals
Begin power routing ...
**WARN: (ENCSR-486): Ring/Stripe at (92800 92800) (1782200 104800) on layer ME7 is out of layer range and is ignored. The ports will route to other nearby rings/stripes. (Same type of warning will be suppressed)
Number of IO ports routed: 144 ignored: 288 open: 144
End power routing: cpu: 0:00:00, real: 0:00:00, peak: 2021.00 megs.
Begin updating DB with routing results ...
Updating DB with 116 via definition ...Extracting standard cell pins and blockage ......
Pin and blockage extraction finished
sroute post-processing starts at Thu Sep 29 11:31:47 2011
The viaGen is rebuilding shadow vias for net VSS.
sroute post-processing ends at Thu Sep 29 11:31:47 2011
sroute post-processing starts at Thu Sep 29 11:31:47 2011
The viaGen is rebuilding shadow vias for net VDD.
sroute post-processing ends at Thu Sep 29 11:31:47 2011
sroute: Total CPU time used = 0:0:3
sroute: Total Real time used = 0:0:4
sroute: Total Memory used = 9.04 megs
sroute: Total Peak Memory used = 1576.70 megs
sroute -connect { padPin } -padPinPortConnect { allPort preferLayer } -padPinLayerRange {ME7 ME8} -allowJogging 0 -allowLayerChange 1
*** Begin SPECIAL ROUTE on Thu Sep 29 11:31:51 2011 ***
Sroute/fcroute version 8.1.46 promoted on 02/17/2009.
SPECIAL ROUTE ran on directory: /usr/zupo/dz4/kgf/projects/sha3/shabziger/encounter
SPECIAL ROUTE ran on machine: aotearoa.ee.ethz.ch (Linux 2.6.18-238.5.1.el5 Xeon 2.79Ghz)
Begin option processing ...
(from .sroute_9079.conf) srouteConnectPowerBump set to false
(from .sroute_9079.conf) routeSpecial set to true
(from .sroute_9079.conf) srouteConnectBlockPin set to false
(from .sroute_9079.conf) srouteConnectCorePin set to false
(from .sroute_9079.conf) srouteConnectStripe set to false
(from .sroute_9079.conf) srouteFollowCorePinEnd set to 3
(from .sroute_9079.conf) srouteMaxPadPinLayer set to 8
(from .sroute_9079.conf) srouteMinPadPinLayer set to 7
(from .sroute_9079.conf) sroutePadPinAllGeoms set to true
(from .sroute_9079.conf) sroutePadPinAllPorts set to true
(from .sroute_9079.conf) sroutePadPinPreferredLayer set to true
(from .sroute_9079.conf) sroutePreserveExistingRoutes set to true
(from .sroute_9079.conf) srouteStraightConnections set to "straightWithChanges"
End option processing: cpu: 0:00:00, real: 0:00:00, peak: 2021.00 megs.
Reading DB technology information...
**WARN: (ENCSR-2455): An unexpected implant layer:SPSHVT is found between layer:LPLUS and layer:CONT. Move the implant layer to the beginning or the end of LAYER section in the LEF tech file.
Finished reading DB technology information.
Reading floorplan and netlist information...
Finished reading floorplan and netlist information.
**WARN: Cap-table is found in the design, so the same information from LEF will be ignored.
Read in 24 layers, 8 routing layers, 0 overlap layer
Read in 3309 macros, 763 used
Read in 1008 components
745 core components: 745 unplaced, 0 placed, 0 fixed
256 pad components: 0 unplaced, 200 placed, 56 fixed
3 block/ring components: 0 unplaced, 0 placed, 3 fixed
4 other components: 0 unplaced, 0 placed, 4 fixed
Read in 40 logical pins
Read in 4 blockages
Read in 40 nets
Read in 4 special nets, 2 routed
Read in 2124 terminals
Begin power routing ...
Number of IO ports routed: 32 ignored: 64 open: 32
End power routing: cpu: 0:00:00, real: 0:00:00, peak: 2073.00 megs.
Begin updating DB with routing results ...
Updating DB with 121 via definition ...
sroute post-processing starts at Thu Sep 29 11:31:52 2011
The viaGen is rebuilding shadow vias for net VSS.
sroute post-processing ends at Thu Sep 29 11:31:52 2011
sroute post-processing starts at Thu Sep 29 11:31:52 2011
The viaGen is rebuilding shadow vias for net VDD.
sroute post-processing ends at Thu Sep 29 11:31:52 2011
sroute: Total CPU time used = 0:0:3
sroute: Total Real time used = 0:0:3
sroute: Total Memory used = 0.00 megs
sroute: Total Peak Memory used = 1576.70 megs
setAddStripeMode -trim_antenna_back_to_shape stripe
The power planner will set stripe antenna targets to stripe.
addStripe -set_to_set_distance 10.8 -ybottom_offset 1.5 -spacing 4.6 -width 0.6 -allow_jog_padcore_ring 0 -same_layer_target_only 1 -max_same_layer_jog_length 4 -direction horizontal -layer ME7 -padcore_ring_bottom_layer_limit ME6 -nets {VSS VDD}
**WARN: (ENCPP-2008): AddStripe option -remove_floating_stripe_over_block is ON so all fragmented stripes within a block will be removed.
To turn OFF, setAddStripeOption -remove_floating_stripe_over_block 0.
Starting stripe generation ...
Non-Default setAddStripeOption Settings :
-trim_antenna_back_to_shape stripe
Stripe generation is complete; vias are now being generated.
*** Begin Point to Point Power Routing **************
*** Point to Point Power Routing Summary ************
Number of connections routed: 0 open: 2
*****************************************************
*** Point to Point Routing Complete *****************
The power planner created 295 wires.
addStripe -set_to_set_distance 48.0 -spacing 18.0 -xleft_offset 23.1 -width 6.0 -allow_jog_padcore_ring 0 -same_layer_target_only 1 -max_same_layer_jog_length 4 -layer ME8 -nets {VSS VDD}
**WARN: (ENCPP-2008): AddStripe option -remove_floating_stripe_over_block is ON so all fragmented stripes within a block will be removed.
To turn OFF, setAddStripeOption -remove_floating_stripe_over_block 0.
Starting stripe generation ...
Non-Default setAddStripeOption Settings :
-trim_antenna_back_to_shape stripe
-trim_antenna_max_distance 0.00
Stripe generation is complete; vias are now being generated.
The power planner created 65 wires.
globalNetConnect VDD -type pgpin -pin VCC -inst i_RAM*
globalNetConnect VSS -type pgpin -pin GND -inst i_RAM*
sroute -connect { blockPin } -blockPinRouteWithPinWidth -blockPin { all } -nets {VSS VDD}
*** Begin SPECIAL ROUTE on Thu Sep 29 11:31:58 2011 ***
Sroute/fcroute version 8.1.46 promoted on 02/17/2009.
SPECIAL ROUTE ran on directory: /usr/zupo/dz4/kgf/projects/sha3/shabziger/encounter
SPECIAL ROUTE ran on machine: aotearoa.ee.ethz.ch (Linux 2.6.18-238.5.1.el5 Xeon 2.79Ghz)
Begin option processing ...
(from .sroute_9079.conf) srouteConnectPowerBump set to false
(from .sroute_9079.conf) routeSelectNet set to "VSS VDD"
(from .sroute_9079.conf) routeSpecial set to true
(from .sroute_9079.conf) srouteBlockPin set to "allPins"
(from .sroute_9079.conf) srouteConnectCorePin set to false
(from .sroute_9079.conf) srouteConnectPadPin set to false
(from .sroute_9079.conf) srouteConnectStripe set to false
(from .sroute_9079.conf) srouteFollowCorePinEnd set to 3
(from .sroute_9079.conf) srouteFullWidthBlockpinRoute set to true
(from .sroute_9079.conf) srouteJogControl set to "preferWithChanges differentLayer"
(from .sroute_9079.conf) sroutePadPinAllPorts set to true
(from .sroute_9079.conf) sroutePreserveExistingRoutes set to true
End option processing: cpu: 0:00:00, real: 0:00:00, peak: 2073.00 megs.
Reading DB technology information...
**WARN: (ENCSR-2455): An unexpected implant layer:SPSHVT is found between layer:LPLUS and layer:CONT. Move the implant layer to the beginning or the end of LAYER section in the LEF tech file.
Finished reading DB technology information.
Reading floorplan and netlist information...
Finished reading floorplan and netlist information.
**WARN: Cap-table is found in the design, so the same information from LEF will be ignored.
Read in 24 layers, 8 routing layers, 0 overlap layer
Read in 3309 macros, 763 used
Read in 1008 components
745 core components: 745 unplaced, 0 placed, 0 fixed
256 pad components: 0 unplaced, 200 placed, 56 fixed
3 block/ring components: 0 unplaced, 0 placed, 3 fixed
4 other components: 0 unplaced, 0 placed, 4 fixed
Read in 40 logical pins
Read in 4 blockages
Read in 40 nets
Read in 4 special nets, 2 routed
Read in 2124 terminals
2 nets selected.
Begin power routing ...
Number of Block ports routed: 0
Number of Power Bump ports routed: 0
End power routing: cpu: 0:00:00, real: 0:00:00, peak: 2073.00 megs.
Begin updating DB with routing results ...
Updating DB with 211 via definition ...
sroute: Total CPU time used = 0:0:3
sroute: Total Real time used = 0:0:3
sroute: Total Memory used = 64.00 megs
sroute: Total Peak Memory used = 1640.70 megs
sroute -connect { corePin } -allowLayerChange 1 -targetPenetration { stripe 90 }
*** Begin SPECIAL ROUTE on Thu Sep 29 11:32:04 2011 ***
Sroute/fcroute version 8.1.46 promoted on 02/17/2009.
SPECIAL ROUTE ran on directory: /usr/zupo/dz4/kgf/projects/sha3/shabziger/encounter
SPECIAL ROUTE ran on machine: aotearoa.ee.ethz.ch (Linux 2.6.18-238.5.1.el5 Xeon 2.79Ghz)
Begin option processing ...
(from .sroute_9079.conf) srouteConnectPowerBump set to false
(from .sroute_9079.conf) routeSpecial set to true
(from .sroute_9079.conf) srouteConnectBlockPin set to false
(from .sroute_9079.conf) srouteConnectPadPin set to false
(from .sroute_9079.conf) srouteConnectStripe set to false
(from .sroute_9079.conf) srouteFollowCorePinEnd set to 3
(from .sroute_9079.conf) srouteJogControl set to "preferWithChanges differentLayer"
(from .sroute_9079.conf) sroutePadPinAllPorts set to true
(from .sroute_9079.conf) sroutePreserveExistingRoutes set to true
(from .sroute_9079.conf) srouteTargetPenetration set to "stripe 90"
End option processing: cpu: 0:00:00, real: 0:00:00, peak: 2073.00 megs.
Reading DB technology information...
**WARN: (ENCSR-2455): An unexpected implant layer:SPSHVT is found between layer:LPLUS and layer:CONT. Move the implant layer to the beginning or the end of LAYER section in the LEF tech file.
Finished reading DB technology information.
Reading floorplan and netlist information...
Finished reading floorplan and netlist information.
**WARN: Cap-table is found in the design, so the same information from LEF will be ignored.
Read in 24 layers, 8 routing layers, 0 overlap layer
Read in 3309 macros, 763 used
Read in 1008 components
745 core components: 745 unplaced, 0 placed, 0 fixed
256 pad components: 0 unplaced, 200 placed, 56 fixed
3 block/ring components: 0 unplaced, 0 placed, 3 fixed
4 other components: 0 unplaced, 0 placed, 4 fixed
Read in 40 logical pins
Read in 4 blockages
Read in 40 nets
Read in 4 special nets, 2 routed
Read in 2124 terminals
Begin power routing ...
**WARN: (ENCSR-1253): Net VDDIO does not have standard cells to be routed. Please check net list.
**WARN: (ENCSR-1253): Net VSSIO does not have standard cells to be routed. Please check net list.
CPU time for FollowPin 0 seconds
CPU time for FollowPin 0 seconds
Number of Core ports routed: 3032
Number of Followpin connections: 1516
End power routing: cpu: 0:00:02, real: 0:00:02, peak: 2073.00 megs.
Begin updating DB with routing results ...
Updating DB with 248 via definition ...
sroute post-processing starts at Thu Sep 29 11:32:09 2011
The viaGen is rebuilding shadow vias for net VSS.
sroute post-processing ends at Thu Sep 29 11:32:12 2011
sroute post-processing starts at Thu Sep 29 11:32:12 2011
The viaGen is rebuilding shadow vias for net VDD.
sroute post-processing ends at Thu Sep 29 11:32:16 2011
sroute: Total CPU time used = 0:0:12
sroute: Total Real time used = 0:0:13
sroute: Total Memory used = 9.04 megs
sroute: Total Peak Memory used = 1649.74 megs
redraw
addWellTap -cell WT3S -cellInterval 30 -checkerBoard
skipRow option will be disabled when checkerBoard is set
For 36663 new insts, *** Applied 4 GNC rules (cpu = 0:00:00.0)
Inserted 36663 well-taps cells (prefix WELLTAP).
setPlaceMode -congEffort high -timingDriven 1 -modulePlan 1 -doCongOpt 0 -ignoreScan 0 -reorderScan 0 -rpSpreadEffort high
placeDesign -prePlaceOpt
*** Starting placeDesign default flow ***
*** Start deleteBufferTree ***
Using new Cte TW Api base...#################################################################################
# Design Stage: PreRoute
# Design Mode: 65nm
# Analysis Mode: MMMC non-OCV
# Extraction Mode: default
# Delay Calculation Options: engine=signalStorm signOff=true SIAware=false(opt)
# Switching Delay Calculation Engine to signalStorm
#################################################################################
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:02.0, MEM = 1960.4M, InitMEM = 1954.9M)
Start delay calculation using Signal Storm (mem=1960.379M)...
Start translating cell libraries into ECSM model (MEM=1960.4M)
End translating ECSM and Loading done (CPU=0:00:15.4, MEM=2164.7M)
**WARN: (ENCTS-403): Delay calculation was forced to extrapolate table data outside of the characterized range. In some cases, extrapolation can reduce the accuracy of the delay calculation. You can enable more detailed reporting of these cases by enabling the command 'setDelayCalMode -reportOutBound'.
Delay calculation completed. (cpu=0:01:08 real=0:01:08 mem=2464.859M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.2, MEM = 2464.9M, InitMEM = 2464.9M)
Start delay calculation using Signal Storm (mem=2464.859M)...
Start translating cell libraries into ECSM model (MEM=2464.9M)
End translating ECSM and Loading done (CPU=0:00:00.0, MEM=2464.9M)
Delay calculation completed. (cpu=0:00:20.3 real=0:00:20.0 mem=2464.859M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.3, MEM = 2464.9M, InitMEM = 2464.9M)
Start delay calculation using Signal Storm (mem=2464.859M)...
Start translating cell libraries into ECSM model (MEM=2464.9M)
End translating ECSM and Loading done (CPU=0:00:00.0, MEM=2464.9M)
Delay calculation completed. (cpu=0:00:19.9 real=0:00:20.0 mem=2465.926M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.2, MEM = 2465.9M, InitMEM = 2465.9M)
Start delay calculation using Signal Storm (mem=2465.926M)...
Start translating cell libraries into ECSM model (MEM=2465.9M)
End translating ECSM and Loading done (CPU=0:00:00.1, MEM=2465.9M)
Delay calculation completed. (cpu=0:00:20.5 real=0:00:21.0 mem=2465.926M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.3, MEM = 2465.9M, InitMEM = 2465.9M)
Start delay calculation using Signal Storm (mem=2465.926M)...
Start translating cell libraries into ECSM model (MEM=2465.9M)
End translating ECSM and Loading done (CPU=0:00:00.0, MEM=2465.9M)
Delay calculation completed. (cpu=0:00:20.4 real=0:00:20.0 mem=2465.926M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.3, MEM = 2465.9M, InitMEM = 2465.9M)
Start delay calculation using Signal Storm (mem=2465.926M)...
Start translating cell libraries into ECSM model (MEM=2465.9M)
End translating ECSM and Loading done (CPU=0:00:00.0, MEM=2465.9M)
Delay calculation completed. (cpu=0:00:20.6 real=0:00:20.0 mem=2465.926M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.3, MEM = 2465.9M, InitMEM = 2465.9M)
Start delay calculation using Signal Storm (mem=2465.926M)...
Start translating cell libraries into ECSM model (MEM=2465.9M)
End translating ECSM and Loading done (CPU=0:00:00.0, MEM=2465.9M)
Delay calculation completed. (cpu=0:00:19.8 real=0:00:19.0 mem=2465.926M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.2, MEM = 2465.9M, InitMEM = 2465.9M)
Start delay calculation using Signal Storm (mem=2465.926M)...
Start translating cell libraries into ECSM model (MEM=2465.9M)
End translating ECSM and Loading done (CPU=0:00:00.0, MEM=2465.9M)
Delay calculation completed. (cpu=0:00:19.9 real=0:00:20.0 mem=2465.926M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.2, MEM = 2465.9M, InitMEM = 2465.9M)
Start delay calculation using Signal Storm (mem=2465.926M)...
Start translating cell libraries into ECSM model (MEM=2465.9M)
End translating ECSM and Loading done (CPU=0:00:00.0, MEM=2465.9M)
Delay calculation completed. (cpu=0:00:19.3 real=0:00:19.0 mem=2466.930M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.3, MEM = 2466.9M, InitMEM = 2466.9M)
Start delay calculation using Signal Storm (mem=2466.930M)...
Start translating cell libraries into ECSM model (MEM=2466.9M)
End translating ECSM and Loading done (CPU=0:00:00.0, MEM=2466.9M)
Delay calculation completed. (cpu=0:00:20.3 real=0:00:20.0 mem=2466.930M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.3, MEM = 2466.9M, InitMEM = 2466.9M)
Start delay calculation using Signal Storm (mem=2466.930M)...
Start translating cell libraries into ECSM model (MEM=2466.9M)
End translating ECSM and Loading done (CPU=0:00:00.0, MEM=2466.9M)
Delay calculation completed. (cpu=0:00:20.3 real=0:00:21.0 mem=2466.930M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.3, MEM = 2466.9M, InitMEM = 2466.9M)
Start delay calculation using Signal Storm (mem=2466.930M)...
Start translating cell libraries into ECSM model (MEM=2466.9M)
End translating ECSM and Loading done (CPU=0:00:00.1, MEM=2466.9M)
Delay calculation completed. (cpu=0:00:19.8 real=0:00:20.0 mem=2466.930M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.2, MEM = 2466.9M, InitMEM = 2466.9M)
Start delay calculation using Signal Storm (mem=2466.930M)...
Start translating cell libraries into ECSM model (MEM=2466.9M)
End translating ECSM and Loading done (CPU=0:00:00.0, MEM=2466.9M)
Delay calculation completed. (cpu=0:00:19.4 real=0:00:19.0 mem=2466.930M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.3, MEM = 2466.9M, InitMEM = 2466.9M)
Start delay calculation using Signal Storm (mem=2466.930M)...
Start translating cell libraries into ECSM model (MEM=2466.9M)
End translating ECSM and Loading done (CPU=0:00:00.0, MEM=2466.9M)
Delay calculation completed. (cpu=0:00:20.5 real=0:00:20.0 mem=2466.930M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.3, MEM = 2466.9M, InitMEM = 2466.9M)
Start delay calculation using Signal Storm (mem=2466.930M)...
Start translating cell libraries into ECSM model (MEM=2466.9M)
End translating ECSM and Loading done (CPU=0:00:00.0, MEM=2466.9M)
Delay calculation completed. (cpu=0:00:20.5 real=0:00:20.0 mem=2466.930M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.2, MEM = 2466.9M, InitMEM = 2466.9M)
Start delay calculation using Signal Storm (mem=2466.930M)...
Start translating cell libraries into ECSM model (MEM=2466.9M)
End translating ECSM and Loading done (CPU=0:00:00.0, MEM=2466.9M)
Delay calculation completed. (cpu=0:00:19.9 real=0:00:19.0 mem=2466.930M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.4, MEM = 2466.9M, InitMEM = 2466.9M)
Start delay calculation using Signal Storm (mem=2466.930M)...
Start translating cell libraries into ECSM model (MEM=2466.9M)
End translating ECSM and Loading done (CPU=0:00:00.0, MEM=2466.9M)
Delay calculation completed. (cpu=0:00:17.3 real=0:00:17.0 mem=2466.930M 0)
*** CDM Built up (cpu=0:07:58 real=0:07:58 mem= 2458.9M) ***
Info: Detect buffers to remove automatically.
Analyzing netlist ...
Updating netlist
*summary: 249 instances (buffers/inverters) removed
*** Finish deleteBufferTree (0:09:14) ***
Total CPU(s) requested: 8
CPU(s) enabled with current License(s): 2
Additional license(s) checked out: 2 Encounter_Digital_Impl_Sys_XL license(s) for 6 CPU(s)
Total CPU(s) now enabled: 8
Multithreaded Timing Analysis is initialized with 8 threads
*** Starting "NanoPlace(TM) placement v#18 (mem=2887.9M)" ...
*** Build Buffered Sizing Timing Model (Used Compact Buffer Set) ...(cpu=0:00:15.1 mem=3194.4M) ***
*** Build Virtual Sizing Timing Model
(cpu=0:00:29.9 mem=3331.9M) ***
Options: timingDriven clkGateAware ignoreSpare pinGuide gpeffort=medium
*** Free Virtual Timing Model ...(mem=1923.8M)
Using new Cte TW Api base...#################################################################################
# Design Stage: PreRoute
# Design Mode: 65nm
# Analysis Mode: MMMC non-OCV
# Extraction Mode: default
# Delay Calculation Options: engine=feDc signOff=true SIAware=false(opt)
# Switching Delay Calculation Engine to feDC
#################################################################################
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.3, MEM = 2331.7M, InitMEM = 2325.7M)
Start delay calculation (mem=2331.703M)...
*** Build Buffered Sizing Timing Model (Used Compact Buffer Set) ...(cpu=0:00:09.8 mem=2636.9M) ***
*** Build Virtual Sizing Timing Model
(cpu=0:00:19.5 mem=2774.4M) ***
Delay calculation completed. (cpu=0:00:56.5 real=0:00:57.0 mem=3071.621M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.8, MEM = 3071.6M, InitMEM = 3071.6M)
Start delay calculation (mem=3071.621M)...
Delay calculation completed. (cpu=0:00:13.9 real=0:00:14.0 mem=3071.621M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.8, MEM = 3071.6M, InitMEM = 3071.6M)
Start delay calculation (mem=3071.621M)...
Delay calculation completed. (cpu=0:00:14.0 real=0:00:14.0 mem=3071.621M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.8, MEM = 3071.6M, InitMEM = 3071.6M)
Start delay calculation (mem=3071.621M)...
Delay calculation completed. (cpu=0:00:14.0 real=0:00:14.0 mem=3071.621M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.8, MEM = 3071.6M, InitMEM = 3071.6M)
Start delay calculation (mem=3071.621M)...
Delay calculation completed. (cpu=0:00:13.9 real=0:00:14.0 mem=3071.621M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.8, MEM = 3071.6M, InitMEM = 3071.6M)
Start delay calculation (mem=3071.621M)...
Delay calculation completed. (cpu=0:00:14.0 real=0:00:14.0 mem=3071.621M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.8, MEM = 3071.6M, InitMEM = 3071.6M)
Start delay calculation (mem=3071.621M)...
Delay calculation completed. (cpu=0:00:13.9 real=0:00:14.0 mem=3071.621M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.8, MEM = 3071.6M, InitMEM = 3071.6M)
Start delay calculation (mem=3071.621M)...
Delay calculation completed. (cpu=0:00:13.9 real=0:00:13.0 mem=3071.621M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.8, MEM = 3071.6M, InitMEM = 3071.6M)
Start delay calculation (mem=3071.621M)...
Delay calculation completed. (cpu=0:00:13.9 real=0:00:14.0 mem=3071.621M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.8, MEM = 3071.6M, InitMEM = 3071.6M)
Start delay calculation (mem=3071.621M)...
Delay calculation completed. (cpu=0:00:13.9 real=0:00:14.0 mem=3071.621M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.8, MEM = 3071.6M, InitMEM = 3071.6M)
Start delay calculation (mem=3071.621M)...
Delay calculation completed. (cpu=0:00:13.9 real=0:00:14.0 mem=3071.621M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.8, MEM = 3071.6M, InitMEM = 3071.6M)
Start delay calculation (mem=3071.621M)...
Delay calculation completed. (cpu=0:00:13.8 real=0:00:13.0 mem=3071.621M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.8, MEM = 3071.6M, InitMEM = 3071.6M)
Start delay calculation (mem=3071.621M)...
Delay calculation completed. (cpu=0:00:13.9 real=0:00:14.0 mem=3071.621M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.8, MEM = 3071.6M, InitMEM = 3071.6M)
Start delay calculation (mem=3071.621M)...
Delay calculation completed. (cpu=0:00:14.0 real=0:00:14.0 mem=3071.621M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.8, MEM = 3071.6M, InitMEM = 3071.6M)
Start delay calculation (mem=3071.621M)...
Delay calculation completed. (cpu=0:00:13.9 real=0:00:14.0 mem=3071.621M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.8, MEM = 3071.6M, InitMEM = 3071.6M)
Start delay calculation (mem=3071.621M)...
Delay calculation completed. (cpu=0:00:13.8 real=0:00:13.0 mem=3071.621M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.8, MEM = 3071.6M, InitMEM = 3071.6M)
Start delay calculation (mem=3071.621M)...
Delay calculation completed. (cpu=0:00:14.2 real=0:00:15.0 mem=3071.621M 0)
*** CDM Built up (cpu=0:05:39 real=0:05:40 mem= 3064.6M) ***
*** Memory pool thread-safe mode activated.
ViewTrimming: worst 17 views:
View Pruning: WorstView slack is 347.900000 ps.
View: gmu_groestl_slow_view
Corner: worst_corn
View Pruning: WorstView slack is 329.800000 ps.
View: ethz_skein_slow_view
Corner: worst_corn
View Pruning: WorstView slack is 320.300000 ps.
View: gmu_keccak_slow_view
Corner: worst_corn
View Pruning: WorstView slack is 316.100000 ps.
View: gmu_jh_slow_view
Corner: worst_corn
DC Corner worst_corn, is equivalent to worst_corn.
DC Corner worst_corn, is equivalent to worst_corn.
DC Corner worst_corn, is equivalent to worst_corn.
Mem message Memory info before deleting aae data base (MEM=2364.7M)
Mem message Memory info after deleting aae data base (MEM=2364.7M)
Initializing multi-corner RC extraction with 2 active RC Corners ...
Reading Capacitance Table File tech/u65ll_RCMAX.captbl ...
Cap Table was created using Encounter 10.11-s096_1.
Process name: G_4J_LOGIC_MIXED_MODE65N_1P8M1T0F1U_LL_LOW_K_TOP_METAL32_5K_1_0_P1.
**WARN: (ENCEXT-2760): Layer M9 in the cap table is larger than max number of layers, 8, defined in the LEF file.
**WARN: (ENCEXT-2771): Top layer, M9, of Via ALVIA in the cap table is larger than max number of layers, 8, defined in the LEF file.
Allocated an empty WireEdgeEnlargement table in rc_worst [8]
**WARN: (ENCEXT-2710): Cap table for M9 is ignored, the layer is not defined in the design.
Reading Capacitance Table File tech/u65ll_RCMIN.captbl ...
Cap Table was created using Encounter 10.11-s096_1.
Process name: G_4J_LOGIC_MIXED_MODE65N_1P8M1T0F1U_LL_LOW_K_TOP_METAL32_5K_1_0_P1.
**WARN: (ENCEXT-2760): Layer M9 in the cap table is larger than max number of layers, 8, defined in the LEF file.
**WARN: (ENCEXT-2771): Top layer, M9, of Via ALVIA in the cap table is larger than max number of layers, 8, defined in the LEF file.
Allocated an empty WireEdgeEnlargement table in rc_best [8]
**WARN: (ENCEXT-2710): Cap table for M9 is ignored, the layer is not defined in the design.
Importing multi-corner RC tables ...
Summary of Active RC-Corners :
Analysis View: gmu_jh_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: gmu_keccak_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: ethz_skein_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: gmu_groestl_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: hold_fast_view
RC-Corner Name : rc_best
RC-Corner Index : 1
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMIN.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
*Info: initialize multi-corner CTS.
CTE reading timing constraint file 'src/shabziger_mmmc_gmu_keccak.sdc' ...
Number of path exceptions in the constraint file = 3
Number of paths exceptions after getting compressed = 2
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_gmu_groestl.sdc' ...
Number of path exceptions in the constraint file = 3
Number of paths exceptions after getting compressed = 2
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_ethz_skein.sdc' ...
Number of path exceptions in the constraint file = 2
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_gmu_jh.sdc' ...
Number of path exceptions in the constraint file = 3
Number of paths exceptions after getting compressed = 2
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_test.sdc' ...
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
Total number of combinational cells: 2004
Total number of sequential cells: 1182
Total number of tristate cells: 45
Total number of level shifter cells: 0
Total number of power gating cells: 0
Total number of isolation cells: 0
Total number of power switch cells: 0
Total number of pulse generator cells: 0
Total number of always on buffers: 0
Total number of retention cells: 0
List of usable buffers: BUFM2S BUFM4S BUFM3S BUFM6S BUFM5S BUFM8S BUFM10S BUFM12S BUFM14S BUFM16S BUFM18S BUFM22SA BUFM20S BUFM24S BUFM26SA BUFM32SA BUFM40SA BUFM48SA CKBUFM2S CKBUFM1S CKBUFM4S CKBUFM3S CKBUFM6S CKBUFM8S CKBUFM12S CKBUFM16S CKBUFM20S CKBUFM22SA CKBUFM24S CKBUFM26SA CKBUFM32S CKBUFM40S CKBUFM48S BUFM2R BUFM4R BUFM3R BUFM6R BUFM5R BUFM8R BUFM10R BUFM12R BUFM14R BUFM16R BUFM18R BUFM22RA BUFM20R BUFM24R BUFM26RA BUFM32RA BUFM40RA BUFM48RA CKBUFM2R CKBUFM1R CKBUFM4R CKBUFM3R CKBUFM6R CKBUFM8R CKBUFM12R CKBUFM16R CKBUFM20R CKBUFM22RA CKBUFM24R CKBUFM26RA CKBUFM32R CKBUFM40R CKBUFM48R DEL1M4R BUFM2W BUFM4W BUFM3W BUFM6W BUFM5W BUFM8W BUFM10W BUFM12W BUFM14W BUFM16W BUFM18W BUFM22WA BUFM20W BUFM24W BUFM26WA BUFM32WA BUFM40WA BUFM48WA CKBUFM2W CKBUFM1W CKBUFM4W CKBUFM3W CKBUFM6W CKBUFM8W CKBUFM12W CKBUFM16W CKBUFM20W CKBUFM22WA CKBUFM24W CKBUFM26WA CKBUFM32W CKBUFM40W CKBUFM48W DEL1M1W DEL1M4W
Total number of usable buffers: 102
List of unusable buffers:
Total number of unusable buffers: 0
List of usable inverters: CKINVM2S CKINVM1S CKINVM4S CKINVM3S CKINVM6S CKINVM8S CKINVM12S CKINVM16S CKINVM20S CKINVM22SA CKINVM24S CKINVM26SA CKINVM32S CKINVM40S CKINVM48S INVM2S INVM1S INVM4S INVM3S INVM6S INVM5S INVM8S INVM10S INVM12S INVM14S INVM16S INVM18S INVM20S INVM22SA INVM24S INVM26SA INVM32S INVM40S INVM48S CKINVM2R CKINVM1R CKINVM4R CKINVM3R CKINVM6R CKINVM8R CKINVM12R CKINVM16R CKINVM20R CKINVM22RA CKINVM24R CKINVM26RA CKINVM32R CKINVM40R CKINVM48R INVM2R INVM1R INVM4R INVM3R INVM6R INVM5R INVM8R INVM10R INVM12R INVM14R INVM16R INVM18R INVM20R INVM22RA INVM24R INVM26RA INVM32R INVM40R INVM48R CKINVM2W CKINVM1W CKINVM4W CKINVM3W CKINVM6W CKINVM8W CKINVM12W CKINVM16W CKINVM20W CKINVM22WA CKINVM24W CKINVM26WA CKINVM32W CKINVM40W CKINVM48W INVM2W INVM1W INVM4W INVM3W INVM6W INVM5W INVM8W INVM10W INVM12W INVM14W INVM16W INVM18W INVM20W INVM22WA INVM24W INVM26WA INVM32W INVM40W INVM48W
Total number of usable inverters: 102
List of unusable inverters: REGKM2S REGKM1S REGKM4S REGKM2R REGKM1R REGKM4R REGKM2W REGKM1W REGKM4W INVM0S INVM0R INVM0W
Total number of unusable inverters: 12
List of identified usable delay cells: DEL1M1S DEL1M4S DEL2M1S DEL2M4S DEL3M1S DEL3M4S DEL4M1S DEL4M4S DEL1M1R DEL2M1R DEL2M4R DEL3M1R DEL3M4R DEL4M1R DEL4M4R DEL2M1W DEL2M4W DEL3M1W DEL3M4W DEL4M1W DEL4M4W
Total number of identified usable delay cells: 21
List of identified unusable delay cells:
Total number of identified unusable delay cells: 0
#std cell=289974 #block=3 (0 floating + 3 preplaced) #ioInst=260 #net=259455 #term=931213 #term/net=3.59, #fixedIo=260, #floatIo=0, #fixedPin=40, #floatPin=0
stdCell: 289974 single + 0 double + 0 multi
Total standard cell length = 563.9194 (mm), area = 1.0151 (mm^2)
Average module density = 0.533.
Density for the design = 0.533.
= stdcell_area 2709608 (975459 um^2) / alloc_area 5085376 (1830735 um^2).
Pin Density = 0.213.
= total # of pins 931213 / total Instance area 4371056.
Enabling multi-CPU acceleration with 8 CPU(s) for placement
Checking spec file integrity...
Clock gating cells determined by native netlist tracing.
Iteration 1: Total net bbox = 4.408e+05 (1.70e+05 2.70e+05)
Est. stn bbox = 4.408e+05 (1.70e+05 2.70e+05)
cpu = 0:00:04.3 real = 0:00:04.0 mem = 2986.6M
Iteration 2: Total net bbox = 4.408e+05 (1.70e+05 2.70e+05)
Est. stn bbox = 4.408e+05 (1.70e+05 2.70e+05)
cpu = 0:00:00.1 real = 0:00:01.0 mem = 2990.5M
Iteration 3: Total net bbox = 4.416e+05 (1.71e+05 2.71e+05)
Est. stn bbox = 4.416e+05 (1.71e+05 2.71e+05)
cpu = 0:00:00.6 real = 0:00:00.0 mem = 3009.9M
Iteration 4: Total net bbox = 8.274e+06 (4.01e+06 4.26e+06)
Est. stn bbox = 8.274e+06 (4.01e+06 4.26e+06)
cpu = 0:03:36 real = 0:00:41.0 mem = 3009.9M
Iteration 5: Total net bbox = 9.920e+06 (4.71e+06 5.21e+06)
Est. stn bbox = 9.920e+06 (4.71e+06 5.21e+06)
cpu = 0:02:54 real = 0:00:35.0 mem = 3009.9M
Iteration 6: Total net bbox = 1.176e+07 (5.62e+06 6.14e+06)
Est. stn bbox = 1.176e+07 (5.62e+06 6.14e+06)
cpu = 0:03:07 real = 0:00:41.0 mem = 3015.9M
Iteration 7: Total net bbox = 1.233e+07 (5.87e+06 6.46e+06)
Est. stn bbox = 1.430e+07 (6.82e+06 7.48e+06)
cpu = 0:01:38 real = 0:00:37.0 mem = 2829.4M
Iteration 8: Total net bbox = 1.242e+07 (5.90e+06 6.52e+06)
Est. stn bbox = 1.440e+07 (6.86e+06 7.54e+06)
cpu = 0:01:53 real = 0:01:37 mem = 2886.7M
Iteration 9: Total net bbox = 1.278e+07 (5.97e+06 6.81e+06)
Est. stn bbox = 1.508e+07 (7.05e+06 8.03e+06)
cpu = 0:03:39 real = 0:01:06 mem = 2891.8M
Iteration 10: Total net bbox = 1.278e+07 (5.97e+06 6.81e+06)
Est. stn bbox = 1.508e+07 (7.05e+06 8.03e+06)
cpu = 0:01:55 real = 0:01:39 mem = 2889.0M
Iteration 11: Total net bbox = 1.309e+07 (6.07e+06 7.02e+06)
Est. stn bbox = 1.551e+07 (7.20e+06 8.31e+06)
cpu = 0:02:28 real = 0:00:52.0 mem = 2892.0M
Iteration 12: Total net bbox = 1.308e+07 (6.07e+06 7.01e+06)
Est. stn bbox = 1.550e+07 (7.20e+06 8.30e+06)
cpu = 0:01:56 real = 0:01:39 mem = 2891.5M
Iteration 13: Total net bbox = 1.347e+07 (6.28e+06 7.19e+06)
Est. stn bbox = 1.598e+07 (7.45e+06 8.52e+06)
cpu = 0:02:02 real = 0:00:48.0 mem = 2895.5M
Iteration 14: Total net bbox = 1.347e+07 (6.28e+06 7.19e+06)
Est. stn bbox = 1.598e+07 (7.45e+06 8.52e+06)
cpu = 0:00:00.2 real = 0:00:00.0 mem = 2895.5M
Iteration 15: Total net bbox = 1.305e+07 (6.09e+06 6.96e+06)
Est. stn bbox = 1.553e+07 (7.25e+06 8.28e+06)
cpu = 0:02:31 real = 0:00:57.0 mem = 2905.6M
Iteration 16: Total net bbox = 1.304e+07 (6.09e+06 6.96e+06)
Est. stn bbox = 1.552e+07 (7.25e+06 8.28e+06)
cpu = 0:01:56 real = 0:01:40 mem = 2909.6M
Iteration 17: Total net bbox = 1.321e+07 (6.16e+06 7.05e+06)
Est. stn bbox = 1.569e+07 (7.32e+06 8.37e+06)
cpu = 0:01:47 real = 0:00:29.0 mem = 2924.6M
Iteration 18: Total net bbox = 1.321e+07 (6.16e+06 7.05e+06)
Est. stn bbox = 1.569e+07 (7.32e+06 8.37e+06)
cpu = 0:00:00.3 real = 0:00:01.0 mem = 2945.7M
Iteration 19: Total net bbox = 1.336e+07 (6.30e+06 7.06e+06)
Est. stn bbox = 1.585e+07 (7.46e+06 8.39e+06)
cpu = 0:00:03.2 real = 0:00:03.0 mem = 2945.7M
*** cost = 1.336e+07 (6.30e+06 7.06e+06) (cpu for global=0:31:34) real=0:13:34***
Placement multithread real runtime: 0:13:34 with 8 threads.
Info: 17 clock gating cells identified, 15 (on average) moved
Core Placement runtime cpu: 0:22:35 real: 0:05:39
Starting refinePlace ...
move report: placeLevelShifters moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Spread Effort: high, pre-route mode.
Finished Phase I. CPU Time = 0:00:21.0, Real Time = 0:00:21.0
move report: preRPlace moves 61621 insts, mean move: 0.89 um, max move: 9.80 um
max move on inst (top/i_gmu_blake/datapath_gen/hreg_gen_output_reg_183_): (1124.40, 148.80) --> (1116.40, 150.60)
Placement tweakage begins.
wire length = 1.337e+07 = 6.301e+06 H + 7.072e+06 V
wire length = 1.305e+07 = 6.015e+06 H + 7.037e+06 V
Placement tweakage ends.
move report: tweak moves 97935 insts, mean move: 4.16 um, max move: 60.20 um
max move on inst (top/i_gmu_groestl/U3085): (490.00, 471.00) --> (507.00, 514.20)
move report: rPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: overall moves 132253 insts, mean move: 3.33 um, max move: 60.20 um
max move on inst (top/i_gmu_groestl/U3085): (490.00, 471.00) --> (507.00, 514.20)
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 60.20 um
inst (top/i_gmu_groestl/U3085) with max move: (490, 471) -> (507, 514.2)
mean (X+Y) = 3.33 um
Total instances flipped for WireLenOpt: 4208
Total instances flipped, including legalization: 86317
Total instances moved : 132253
*** cpu=0:00:33.8 mem=2534.7M mem(used)=13.1M***
Total net length = 1.306e+07 (6.015e+06 7.041e+06) (ext = 0.000e+00)
*** End of Placement (cpu=0:46:26, real=0:27:24, mem=2534.7M) ***
default core: bins with density > 0.75 = 14.2 % ( 1100 / 7744 )
*** Free Virtual Timing Model ...(mem=2093.0M)
Starting IO pin assignment...
DC Corner worst_corn, is equivalent to worst_corn.
DC Corner worst_corn, is equivalent to worst_corn.
DC Corner worst_corn, is equivalent to worst_corn.
DC Corner worst_corn, is equivalent to worst_corn.
DC Corner worst_corn, is equivalent to worst_corn.
DC Corner worst_corn, is equivalent to worst_corn.
DC Corner worst_corn, is equivalent to worst_corn.
DC Corner worst_corn, is equivalent to worst_corn.
DC Corner worst_corn, is equivalent to worst_corn.
DC Corner worst_corn, is equivalent to worst_corn.
DC Corner worst_corn, is equivalent to worst_corn.
DC Corner worst_corn, is equivalent to worst_corn.
DC Corner worst_corn, is equivalent to worst_corn.
DC Corner worst_corn, is equivalent to worst_corn.
DC Corner worst_corn, is equivalent to worst_corn.
DC Corner worst_corn, is equivalent to worst_corn.
Mem message Memory info before deleting aae data base (MEM=2019.9M)
Mem message Memory info after deleting aae data base (MEM=2019.9M)
Initializing multi-corner RC extraction with 2 active RC Corners ...
Reading Capacitance Table File tech/u65ll_RCMAX.captbl ...
Cap Table was created using Encounter 10.11-s096_1.
Process name: G_4J_LOGIC_MIXED_MODE65N_1P8M1T0F1U_LL_LOW_K_TOP_METAL32_5K_1_0_P1.
**WARN: (ENCEXT-2760): Layer M9 in the cap table is larger than max number of layers, 8, defined in the LEF file.
**WARN: (ENCEXT-2771): Top layer, M9, of Via ALVIA in the cap table is larger than max number of layers, 8, defined in the LEF file.
Allocated an empty WireEdgeEnlargement table in rc_worst [8]
**WARN: (ENCEXT-2710): Cap table for M9 is ignored, the layer is not defined in the design.
Reading Capacitance Table File tech/u65ll_RCMIN.captbl ...
Cap Table was created using Encounter 10.11-s096_1.
Process name: G_4J_LOGIC_MIXED_MODE65N_1P8M1T0F1U_LL_LOW_K_TOP_METAL32_5K_1_0_P1.
**WARN: (ENCEXT-2760): Layer M9 in the cap table is larger than max number of layers, 8, defined in the LEF file.
**WARN: (ENCEXT-2771): Top layer, M9, of Via ALVIA in the cap table is larger than max number of layers, 8, defined in the LEF file.
Allocated an empty WireEdgeEnlargement table in rc_best [8]
**WARN: (ENCEXT-2710): Cap table for M9 is ignored, the layer is not defined in the design.
Importing multi-corner RC tables ...
Summary of Active RC-Corners :
Analysis View: dummy_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: ethz_blake_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: ethz_groestl_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: ethz_jh_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: ethz_keccak_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: ethz_sha2_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: ethz_skein_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: gmu_blake_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: gmu_groestl_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: gmu_jh_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: gmu_keccak_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: gmu_sha2_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: gmu_skein_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: ram1_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: ram2_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: ram3_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: test_slow_view
RC-Corner Name : rc_worst
RC-Corner Index : 0
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMAX.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
Analysis View: hold_fast_view
RC-Corner Name : rc_best
RC-Corner Index : 1
RC-Corner Temperature : 25 Celsius
RC-Corner Cap Table : 'tech/u65ll_RCMIN.captbl'
RC-Corner PreRoute Res Factor : 1
RC-Corner PreRoute Cap Factor : 1
RC-Corner PostRoute Res Factor : 1
RC-Corner PostRoute Cap Factor : 1
RC-Corner PostRoute XCap Factor : 1
RC-Corner PreRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1 [Derived from postRoute_cap (effortLevel low)]
RC-Corner PostRoute Clock Res Factor : 1 [Derived from postRoute_res (effortLevel low)]
*Info: initialize multi-corner CTS.
CTE reading timing constraint file 'src/shabziger_mmmc_gmu_keccak.sdc' ...
Number of path exceptions in the constraint file = 3
Number of paths exceptions after getting compressed = 2
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_gmu_skein.sdc' ...
Number of path exceptions in the constraint file = 2
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_ethz_blake.sdc' ...
Number of path exceptions in the constraint file = 2
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_ethz_sha2.sdc' ...
Number of path exceptions in the constraint file = 3
Number of paths exceptions after getting compressed = 2
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_gmu_groestl.sdc' ...
Number of path exceptions in the constraint file = 3
Number of paths exceptions after getting compressed = 2
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_ram3.sdc' ...
Number of path exceptions in the constraint file = 2
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_ethz_groestl.sdc' ...
Number of path exceptions in the constraint file = 3
Number of paths exceptions after getting compressed = 2
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_ram2.sdc' ...
Number of path exceptions in the constraint file = 2
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_dummy.sdc' ...
Number of path exceptions in the constraint file = 3
Number of paths exceptions after getting compressed = 2
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_gmu_blake.sdc' ...
Number of path exceptions in the constraint file = 2
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_gmu_sha2.sdc' ...
Number of path exceptions in the constraint file = 3
Number of paths exceptions after getting compressed = 2
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_ethz_keccak.sdc' ...
Number of path exceptions in the constraint file = 3
Number of paths exceptions after getting compressed = 2
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_ram1.sdc' ...
Number of path exceptions in the constraint file = 2
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_ethz_skein.sdc' ...
Number of path exceptions in the constraint file = 2
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_ethz_jh.sdc' ...
Number of path exceptions in the constraint file = 3
Number of paths exceptions after getting compressed = 2
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_gmu_jh.sdc' ...
Number of path exceptions in the constraint file = 3
Number of paths exceptions after getting compressed = 2
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_test.sdc' ...
INFO (CTE): constraints read successfully
CTE reading timing constraint file 'src/shabziger_mmmc_shared.sdc' ...
Number of path exceptions in the constraint file = 1
Number of paths exceptions after getting compressed = 1
INFO (CTE): constraints read successfully
Total number of combinational cells: 2004
Total number of sequential cells: 1182
Total number of tristate cells: 45
Total number of level shifter cells: 0
Total number of power gating cells: 0
Total number of isolation cells: 0
Total number of power switch cells: 0
Total number of pulse generator cells: 0
Total number of always on buffers: 0
Total number of retention cells: 0
List of usable buffers: BUFM2S BUFM4S BUFM3S BUFM6S BUFM5S BUFM8S BUFM10S BUFM12S BUFM14S BUFM16S BUFM18S BUFM22SA BUFM20S BUFM24S BUFM26SA BUFM32SA BUFM40SA BUFM48SA CKBUFM2S CKBUFM1S CKBUFM4S CKBUFM3S CKBUFM6S CKBUFM8S CKBUFM12S CKBUFM16S CKBUFM20S CKBUFM22SA CKBUFM24S CKBUFM26SA CKBUFM32S CKBUFM40S CKBUFM48S BUFM2R BUFM4R BUFM3R BUFM6R BUFM5R BUFM8R BUFM10R BUFM12R BUFM14R BUFM16R BUFM18R BUFM22RA BUFM20R BUFM24R BUFM26RA BUFM32RA BUFM40RA BUFM48RA CKBUFM2R CKBUFM1R CKBUFM4R CKBUFM3R CKBUFM6R CKBUFM8R CKBUFM12R CKBUFM16R CKBUFM20R CKBUFM22RA CKBUFM24R CKBUFM26RA CKBUFM32R CKBUFM40R CKBUFM48R DEL1M4R BUFM2W BUFM4W BUFM3W BUFM6W BUFM5W BUFM8W BUFM10W BUFM12W BUFM14W BUFM16W BUFM18W BUFM22WA BUFM20W BUFM24W BUFM26WA BUFM32WA BUFM40WA BUFM48WA CKBUFM2W CKBUFM1W CKBUFM4W CKBUFM3W CKBUFM6W CKBUFM8W CKBUFM12W CKBUFM16W CKBUFM20W CKBUFM22WA CKBUFM24W CKBUFM26WA CKBUFM32W CKBUFM40W CKBUFM48W DEL1M1W DEL1M4W
Total number of usable buffers: 102
List of unusable buffers:
Total number of unusable buffers: 0
List of usable inverters: CKINVM2S CKINVM1S CKINVM4S CKINVM3S CKINVM6S CKINVM8S CKINVM12S CKINVM16S CKINVM20S CKINVM22SA CKINVM24S CKINVM26SA CKINVM32S CKINVM40S CKINVM48S INVM2S INVM1S INVM4S INVM3S INVM6S INVM5S INVM8S INVM10S INVM12S INVM14S INVM16S INVM18S INVM20S INVM22SA INVM24S INVM26SA INVM32S INVM40S INVM48S CKINVM2R CKINVM1R CKINVM4R CKINVM3R CKINVM6R CKINVM8R CKINVM12R CKINVM16R CKINVM20R CKINVM22RA CKINVM24R CKINVM26RA CKINVM32R CKINVM40R CKINVM48R INVM2R INVM1R INVM4R INVM3R INVM6R INVM5R INVM8R INVM10R INVM12R INVM14R INVM16R INVM18R INVM20R INVM22RA INVM24R INVM26RA INVM32R INVM40R INVM48R CKINVM2W CKINVM1W CKINVM4W CKINVM3W CKINVM6W CKINVM8W CKINVM12W CKINVM16W CKINVM20W CKINVM22WA CKINVM24W CKINVM26WA CKINVM32W CKINVM40W CKINVM48W INVM2W INVM1W INVM4W INVM3W INVM6W INVM5W INVM8W INVM10W INVM12W INVM14W INVM16W INVM18W INVM20W INVM22WA INVM24W INVM26WA INVM32W INVM40W INVM48W
Total number of usable inverters: 102
List of unusable inverters: REGKM2S REGKM1S REGKM4S REGKM2R REGKM1R REGKM4R REGKM2W REGKM1W REGKM4W INVM0S INVM0R INVM0W
Total number of unusable inverters: 12
List of identified usable delay cells: DEL1M1S DEL1M4S DEL2M1S DEL2M4S DEL3M1S DEL3M4S DEL4M1S DEL4M4S DEL1M1R DEL2M1R DEL2M4R DEL3M1R DEL3M4R DEL4M1R DEL4M4R DEL2M1W DEL2M4W DEL3M1W DEL3M4W DEL4M1W DEL4M4W
Total number of identified usable delay cells: 21
List of identified unusable delay cells:
Total number of identified unusable delay cells: 0
***Info:reseting back to current views is done ****
Starting congestion repair ...
moveBlkTerm was implicitly turned on (since useM1).
*** Starting trialRoute (mem=2133.2M) ***
There are 0 pin guide points passed to trialRoute.
**WARN: (ENCTR-2325): there are 40 nets connecting a pad term to a fterm without geometry and these nets will not be routed. Type 'set trPrintIgnoredPadNets ' to see these nets.
moveBlkTerm was implicitly turned on (since useM1).
Options: -moveBlkTerm -useM1 -noPinGuide
Nr of prerouted/Fixed nets = 40
Num blk terms moved = 930723.
routingBox: (100 200) (1874900 1874800)
coreBox: (148800 148800) (1726200 1726200)
Number of multi-gpin terms=0, multi-gpins=0, moved blk term=88/211524
Phase 1a route (0:00:02.9 2455.7M):
Est net length = 1.534e+07um = 7.253e+06H + 8.085e+06V
Usage: (25.6%H 29.4%V) = (7.640e+06um 7.907e+06um) = (7636444 4392996)
Obstruct: 784163 = 288147 (16.7%H) + 496016 (28.8%V)
Overflow: 18389 = 3859 (0.27% H) + 14530 (1.18% V)
Number obstruct path=71068 reroute=0
Phase 1b route (0:00:04.5 2470.3M):
Usage: (26.1%H 29.8%V) = (7.787e+06um 8.017e+06um) = (7783146 4453897)
Overflow: 60087 = 2884 (0.20% H) + 57203 (4.66% V)
Phase 1c route (0:00:02.2 2470.3M):
Usage: (26.1%H 29.8%V) = (7.776e+06um 8.021e+06um) = (7772284 4456090)
Overflow: 51593 = 2539 (0.18% H) + 49054 (4.00% V)
Phase 1d route (0:00:01.9 2471.3M):
Usage: (26.1%H 29.8%V) = (7.778e+06um 8.027e+06um) = (7774345 4459207)
Overflow: 33691 = 764 (0.05% H) + 32927 (2.68% V)
Phase 1e route (0:00:01.6 2536.3M):
Usage: (26.1%H 29.8%V) = (7.795e+06um 8.032e+06um) = (7791427 4462499)
Overflow: 381 = 8 (0.00% H) + 373 (0.03% V)
Phase 1f route (0:00:01.3 2536.3M):
Usage: (26.1%H 29.8%V) = (7.794e+06um 8.032e+06um) = (7790462 4462378)
Overflow: 44 = 1 (0.00% H) + 43 (0.00% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-1: 1 0.00% 43 0.00%
--------------------------------------
0: 393 0.03% 6907 0.56%
1: 1107 0.08% 16084 1.31%
2: 2769 0.19% 22968 1.87%
3: 7582 0.53% 36400 2.97%
4: 10377 0.72% 58379 4.76%
5: 14705 1.03% 278252 22.69%
6: 23228 1.62% 121941 9.94%
7: 26588 1.85% 78976 6.44%
8: 36075 2.51% 74461 6.07%
9: 52729 3.68% 71134 5.80%
10: 56093 3.91% 79838 6.51%
11: 68477 4.77% 57812 4.71%
12: 161131 11.23% 50074 4.08%
13: 204788 14.28% 36461 2.97%
14: 118709 8.28% 30843 2.51%
15: 75422 5.26% 153284 12.50%
16: 73327 5.11% 42148 3.44%
17: 67319 4.69% 449 0.04%
18: 61460 4.28% 5883 0.48%
19: 51684 3.60% 11 0.00%
20: 320489 22.34% 4236 0.35%
Global route (cpu=14.6s real=15.0s 2465.4M)
Phase 1l route (0:00:13.3 2386.5M):
*** After '-updateRemainTrks' operation:
Usage: (26.9%H 31.5%V) = (8.024e+06um 8.474e+06um) = (8020711 4707518)
Overflow: 4853 = 142 (0.01% H) + 4711 (0.38% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-5: 0 0.00% 2 0.00%
-4: 2 0.00% 20 0.00%
-3: 7 0.00% 146 0.01%
-2: 28 0.00% 842 0.07%
-1: 86 0.01% 3223 0.26%
--------------------------------------
0: 622 0.04% 11214 0.91%
1: 1476 0.10% 21416 1.75%
2: 3465 0.24% 29551 2.41%
3: 8652 0.60% 43701 3.56%
4: 11758 0.82% 60667 4.95%
5: 16871 1.18% 277995 22.66%
6: 26041 1.82% 119216 9.72%
7: 30284 2.11% 75039 6.12%
8: 39335 2.74% 70342 5.73%
9: 55500 3.87% 66779 5.44%
10: 58229 4.06% 75637 6.17%
11: 69831 4.87% 54258 4.42%
12: 160745 11.21% 47212 3.85%
13: 203188 14.16% 34190 2.79%
14: 116645 8.13% 29490 2.40%
15: 72978 5.09% 152945 12.47%
16: 70335 4.90% 42141 3.44%
17: 64422 4.49% 444 0.04%
18: 58818 4.10% 5867 0.48%
19: 49484 3.45% 11 0.00%
20: 315651 22.00% 4236 0.35%
Num blk terms moved back = 925494
*** Completed Phase 1 route (0:00:32.2 2424.8M) ***
Total length: 1.580e+07um, number of vias: 2463878
M1(H) length: 1.445e+04um, number of vias: 931412
M2(V) length: 2.711e+06um, number of vias: 929033
M3(H) length: 3.758e+06um, number of vias: 340186
M4(V) length: 2.998e+06um, number of vias: 170788
M5(H) length: 3.291e+06um, number of vias: 83462
M6(V) length: 2.701e+06um, number of vias: 8170
M7(H) length: 3.137e+05um, number of vias: 827
M8(V) length: 1.143e+04um
*** Completed Phase 2 route (0:00:37.1 2493.8M) ***
*** Finished all Phases (cpu=0:01:11 mem=2493.8M) ***
Peak Memory Usage was 2473.7M
*** Finished trialRoute (cpu=0:01:13 mem=2492.8M) ***
CongRepair Bin Grid Size (width, height) = ( default_value , default_value )
Trial Route Overflow 0.009880(H) 0.384085(V).
Start repairing congestion with level 3.
Iteration 11: Total net bbox = 1.294e+07 (6.01e+06 6.93e+06)
Est. stn bbox = 1.294e+07 (6.01e+06 6.93e+06)
cpu = 0:00:20.0 real = 0:00:05.0 mem = 2748.8M
Iteration 12: Total net bbox = 1.304e+07 (6.05e+06 6.98e+06)
Est. stn bbox = 1.304e+07 (6.05e+06 6.98e+06)
cpu = 0:00:32.2 real = 0:00:14.0 mem = 2544.2M
Iteration 13: Total net bbox = 1.309e+07 (6.08e+06 7.01e+06)
Est. stn bbox = 1.309e+07 (6.08e+06 7.01e+06)
cpu = 0:00:52.2 real = 0:00:20.0 mem = 2578.6M
Starting refinePlace ...
move report: placeLevelShifters moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Spread Effort: high, pre-route mode.
Finished Phase I. CPU Time = 0:00:22.1, Real Time = 0:00:22.0
move report: preRPlace moves 59296 insts, mean move: 0.65 um, max move: 8.60 um
max move on inst (top/i_ethz_sha2/U6983): (1385.80, 150.60) --> (1394.40, 150.60)
Placement tweakage begins.
wire length = 1.319e+07 = 6.151e+06 H + 7.039e+06 V
wire length = 1.297e+07 = 5.946e+06 H + 7.025e+06 V
Placement tweakage ends.
move report: tweak moves 58514 insts, mean move: 3.35 um, max move: 60.20 um
max move on inst (top/U18330): (1079.60, 1014.60) --> (1098.40, 1056.00)
move report: rPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: overall moves 99291 insts, mean move: 2.24 um, max move: 60.20 um
max move on inst (top/U18330): (1079.60, 1014.60) --> (1098.40, 1056.00)
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 60.20 um
inst (top/U18330) with max move: (1079.6, 1014.6) -> (1098.4, 1056)
mean (X+Y) = 2.24 um
Total instances flipped for WireLenOpt: 4223
Total instances flipped, including legalization: 109701
Total instances moved : 99291
*** cpu=0:00:34.2 mem=2230.9M mem(used)=6.1M***
Total net length = 1.298e+07 (5.947e+06 7.028e+06) (ext = 0.000e+00)
moveBlkTerm was implicitly turned on (since useM1).
*** Starting trialRoute (mem=2224.8M) ***
There are 0 pin guide points passed to trialRoute.
moveBlkTerm was implicitly turned on (since useM1).
Options: -moveBlkTerm -useM1 -noPinGuide
Nr of prerouted/Fixed nets = 40
Num blk terms moved = 930723.
routingBox: (100 200) (1874900 1874800)
coreBox: (148800 148800) (1726200 1726200)
Number of multi-gpin terms=0, multi-gpins=0, moved blk term=88/149912
Phase 1a route (0:00:02.8 2496.5M):
Est net length = 1.526e+07um = 7.184e+06H + 8.072e+06V
Usage: (25.4%H 29.4%V) = (7.567e+06um 7.893e+06um) = (7563220 4384941)
Obstruct: 784078 = 288147 (16.7%H) + 495931 (28.8%V)
Overflow: 11001 = 3102 (0.22% H) + 7899 (0.64% V)
Number obstruct path=46156 reroute=0
Phase 1b route (0:00:03.9 2508.1M):
Usage: (25.7%H 29.7%V) = (7.664e+06um 7.965e+06um) = (7660957 4425038)
Overflow: 27062 = 2291 (0.16% H) + 24771 (2.02% V)
Phase 1c route (0:00:02.2 2508.1M):
Usage: (25.7%H 29.7%V) = (7.654e+06um 7.969e+06um) = (7650409 4427204)
Overflow: 22048 = 2099 (0.15% H) + 19949 (1.63% V)
Phase 1d route (0:00:01.9 2508.1M):
Usage: (25.7%H 29.7%V) = (7.655e+06um 7.971e+06um) = (7651209 4428343)
Overflow: 14622 = 671 (0.05% H) + 13951 (1.14% V)
Phase 1e route (0:00:01.4 2573.1M):
Usage: (25.7%H 29.7%V) = (7.660e+06um 7.974e+06um) = (7656881 4429768)
Overflow: 168 = 6 (0.00% H) + 161 (0.01% V)
Phase 1f route (0:00:01.3 2573.1M):
Usage: (25.7%H 29.7%V) = (7.660e+06um 7.974e+06um) = (7656624 4429770)
Overflow: 29 = 3 (0.00% H) + 26 (0.00% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-1: 3 0.00% 26 0.00%
--------------------------------------
0: 236 0.02% 3477 0.28%
1: 721 0.05% 11118 0.91%
2: 1796 0.13% 17599 1.43%
3: 5891 0.41% 32393 2.64%
4: 8001 0.56% 60196 4.91%
5: 11674 0.81% 283400 23.10%
6: 19277 1.34% 129431 10.55%
7: 22727 1.58% 86881 7.08%
8: 32078 2.24% 80278 6.54%
9: 49691 3.46% 73777 6.01%
10: 54132 3.77% 81626 6.65%
11: 67275 4.69% 58983 4.81%
12: 161675 11.27% 49711 4.05%
13: 206024 14.36% 36284 2.96%
14: 123396 8.60% 29439 2.40%
15: 81000 5.65% 142528 11.62%
16: 78412 5.47% 38990 3.18%
17: 73108 5.10% 441 0.04%
18: 67452 4.70% 5844 0.48%
19: 58147 4.05% 11 0.00%
20: 311737 21.73% 4236 0.35%
Global route (cpu=13.6s real=14.0s 2502.2M)
Phase 1l route (0:00:12.7 2423.3M):
*** After '-updateRemainTrks' operation:
Usage: (26.4%H 31.3%V) = (7.874e+06um 8.386e+06um) = (7870460 4659084)
Overflow: 1234 = 43 (0.00% H) + 1192 (0.10% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-3: 3 0.00% 16 0.00%
-2: 8 0.00% 140 0.01%
-1: 26 0.00% 966 0.08%
--------------------------------------
0: 299 0.02% 5941 0.48%
1: 906 0.06% 16241 1.32%
2: 2138 0.15% 25514 2.08%
3: 6706 0.47% 42443 3.46%
4: 9280 0.65% 64682 5.27%
5: 13494 0.94% 283931 23.15%
6: 22117 1.54% 126708 10.33%
7: 25771 1.80% 82157 6.70%
8: 35496 2.47% 75154 6.13%
9: 52339 3.65% 69439 5.66%
10: 56246 3.92% 77115 6.29%
11: 68425 4.77% 55336 4.51%
12: 162116 11.30% 46879 3.82%
13: 205434 14.32% 34237 2.79%
14: 121830 8.49% 28090 2.29%
15: 78907 5.50% 142182 11.59%
16: 75565 5.27% 38988 3.18%
17: 70504 4.92% 435 0.04%
18: 64468 4.49% 5828 0.48%
19: 55976 3.90% 11 0.00%
20: 306399 21.36% 4236 0.35%
Num blk terms moved back = 923565
*** Completed Phase 1 route (0:00:30.6 2460.2M) ***
Total length: 1.566e+07um, number of vias: 2385562
M1(H) length: 1.524e+04um, number of vias: 931380
M2(V) length: 2.688e+06um, number of vias: 913226
M3(H) length: 3.855e+06um, number of vias: 317352
M4(V) length: 3.029e+06um, number of vias: 146737
M5(H) length: 3.131e+06um, number of vias: 69960
M6(V) length: 2.673e+06um, number of vias: 6261
M7(H) length: 2.618e+05um, number of vias: 646
M8(V) length: 7.045e+03um
*** Completed Phase 2 route (0:00:36.5 2526.3M) ***
*** Finished all Phases (cpu=0:01:08 mem=2526.3M) ***
Peak Memory Usage was 2510.5M
*** Finished trialRoute (cpu=0:01:11 mem=2526.3M) ***
End of congRepair (cpu=0:05:42, real=0:04:10)
*** Finishing placeDesign default flow ***
**placeDesign ... cpu = 1: 4: 9, real = 0:43:37, mem = 2526.3M **
deleteTieHiLo -cell {TIE0S TIE0S TIE1S TIE1S TIE0W TIE0W TIE1W TIE1W TIE0R TIE0R TIE1R TIE1R}
Deleted 0 physical inst (cell TIE0S / prefix -).
Deleted 0 physical inst (cell TIE0S / prefix -).
Deleted 0 physical inst (cell TIE1S / prefix -).
Deleted 0 physical inst (cell TIE1S / prefix -).
Deleted 0 physical inst (cell TIE0W / prefix -).
Deleted 0 physical inst (cell TIE0W / prefix -).
Deleted 0 physical inst (cell TIE1W / prefix -).
Deleted 0 physical inst (cell TIE1W / prefix -).
Deleted 0 physical inst (cell TIE0R / prefix -).
Deleted 0 physical inst (cell TIE0R / prefix -).
Deleted 0 physical inst (cell TIE1R / prefix -).
Deleted 0 physical inst (cell TIE1R / prefix -).
Deleted 0 logical insts of cell TIE0S
Deleted 0 logical insts of cell TIE0S
Deleted 0 logical insts of cell TIE1S
Deleted 0 logical insts of cell TIE1S
Deleted 0 logical insts of cell TIE0W
Deleted 0 logical insts of cell TIE0W
Deleted 0 logical insts of cell TIE1W
Deleted 0 logical insts of cell TIE1W
Deleted 0 logical insts of cell TIE0R
Deleted 0 logical insts of cell TIE0R
Deleted 0 logical insts of cell TIE1R
Deleted 0 logical insts of cell TIE1R
setTieHiLoMode -reset
setTieHiLoMode -maxFanout 12 -maxDistance 200 -createHierPort true -cell {TIE1W TIE0W}
addTieHiLo -prefix tieoff
Options: Max Distance = 200.000 microns, Max Fan-out = 12.
INFO: Total Number of Tie Cells (TIE1W) placed: 4
INFO: Total Number of Tie Cells (TIE0W) placed: 49
refinePlace
Starting refinePlace ...
Spread Effort: high, standalone mode.
Finished Phase I. CPU Time = 0:00:15.1, Real Time = 0:00:15.0
move report: preRPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: rPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: overall moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 0.00 um
mean (X+Y) = 0.00 um
Total instances moved : 0
*** cpu=0:00:16.5 mem=2431.1M mem(used)=70.1M***
Total net length = 1.298e+07 (5.950e+06 7.034e+06) (ext = 0.000e+00)
default core: bins with density > 0.75 = 6.13 % ( 475 / 7744 )
optDesign -preCTS -drv -outDir timingReports_final -prefix shabziger.preCTS-drv
*info: Enabling Trial Route flow for DRV Fixing.
**WARN: (ENCOPT-6055): The following cells have a dont_touch property but without being dont_use.
Such configuration can impact the timing closure because they can be inserted in the netlist but never transformed again.
It is recommended that you apply a dont_use attribute on them.
Cell SYKA65_2048X32X1CM8 is dont_touch but not dont_use
Cell SHKA65_2048X32X1CM4 is dont_touch but not dont_use
Cell SHKA65_16384X32X1CM16 is dont_touch but not dont_use
...
Reporting only the 20 first cells found...
**optDesign ... cpu = 0:00:00, real = 0:00:00, mem = 2361.0M **
setTrialRouteMode -fixAirConnect true -useM1 true
Added -handlePreroute to trialRouteMode
*** optDesign -preCTS ***
DRC Margin: user margin 0.0; extra margin 0.2
Setup Target Slack: user slack 0.0; extra slack 0.1
Hold Target Slack: user slack 0.0
**WARN: (ENCOPT-3195): Changed analysis mode: setAnalysisMode -clkSrcPath false -clockPropagation forcedIdeal
*info: Setting setup target slack to 0.100
*info: Hold target slack is 0.000
**INFO : Adding temp dont-use cells (LVT only flow version : 4)
Creating information for LVT Only Flow
Num of Buffers : 123
Num of Inverters : 105
Num of VTs : 3
Executing LVT Only Same Size Flow (setting 4)
*Info* Num dontuse cells 311
*Info* Num dontuse cells 2259
moveBlkTerm was implicitly turned on (since useM1).
*** Starting trialRoute (mem=2361.0M) ***
There are 0 pin guide points passed to trialRoute.
moveBlkTerm was implicitly turned on (since useM1).
Options: -moveBlkTerm -useM1 -handlePreroute -noPinGuide
Nr of prerouted/Fixed nets = 40
Num blk terms moved = 931068.
routingBox: (100 200) (1874900 1874800)
coreBox: (148800 148800) (1726200 1726200)
Number of multi-gpin terms=0, multi-gpins=0, moved blk term=192/150072
Phase 1a route (0:00:02.8 2572.8M):
Est net length = 1.527e+07um = 7.187e+06H + 8.078e+06V
Usage: (25.4%H 29.5%V) = (7.570e+06um 7.899e+06um) = (7566459 4388088)
Obstruct: 784078 = 288147 (16.7%H) + 495931 (28.8%V)
Overflow: 11001 = 3102 (0.22% H) + 7899 (0.64% V)
Number obstruct path=46190 reroute=0
Phase 1b route (0:00:03.9 2584.4M):
Usage: (25.7%H 29.7%V) = (7.668e+06um 7.971e+06um) = (7664269 4428200)
Overflow: 27072 = 2291 (0.16% H) + 24780 (2.02% V)
Phase 1c route (0:00:02.2 2584.4M):
Usage: (25.7%H 29.7%V) = (7.658e+06um 7.975e+06um) = (7653723 4430361)
Overflow: 22056 = 2099 (0.15% H) + 19957 (1.63% V)
Phase 1d route (0:00:01.9 2584.4M):
Usage: (25.7%H 29.8%V) = (7.658e+06um 7.977e+06um) = (7654526 4431501)
Overflow: 14626 = 671 (0.05% H) + 13955 (1.14% V)
Phase 1e route (0:00:01.4 2649.4M):
Usage: (25.7%H 29.8%V) = (7.664e+06um 7.979e+06um) = (7660199 4432926)
Overflow: 168 = 6 (0.00% H) + 161 (0.01% V)
Phase 1f route (0:00:01.3 2649.4M):
Usage: (25.7%H 29.8%V) = (7.664e+06um 7.979e+06um) = (7659942 4432928)
Overflow: 29 = 3 (0.00% H) + 26 (0.00% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-1: 3 0.00% 26 0.00%
--------------------------------------
0: 236 0.02% 3480 0.28%
1: 722 0.05% 11121 0.91%
2: 1799 0.13% 17610 1.44%
3: 5893 0.41% 32429 2.64%
4: 8030 0.56% 60216 4.91%
5: 11654 0.81% 283545 23.12%
6: 19314 1.35% 129410 10.55%
7: 22710 1.58% 86921 7.09%
8: 32109 2.24% 80319 6.55%
9: 49687 3.46% 73878 6.02%
10: 54129 3.77% 81514 6.65%
11: 67435 4.70% 59101 4.82%
12: 161540 11.26% 49592 4.04%
13: 206041 14.36% 36152 2.95%
14: 123399 8.60% 29739 2.42%
15: 81001 5.65% 142332 11.60%
16: 78698 5.49% 38948 3.18%
17: 72841 5.08% 291 0.02%
18: 67787 4.73% 5798 0.47%
19: 57734 4.02% 11 0.00%
20: 311691 21.73% 4236 0.35%
Global route (cpu=13.6s real=14.0s 2578.5M)
Phase 1l route (0:00:12.8 2499.6M):
*** After '-updateRemainTrks' operation:
Usage: (26.4%H 31.3%V) = (7.878e+06um 8.393e+06um) = (7873982 4662581)
Overflow: 1243 = 42 (0.00% H) + 1201 (0.10% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-3: 3 0.00% 16 0.00%
-2: 8 0.00% 141 0.01%
-1: 25 0.00% 974 0.08%
--------------------------------------
0: 301 0.02% 5942 0.48%
1: 911 0.06% 16243 1.32%
2: 2142 0.15% 25550 2.08%
3: 6708 0.47% 42468 3.46%
4: 9294 0.65% 64735 5.28%
5: 13518 0.94% 284069 23.16%
6: 22133 1.54% 126682 10.33%
7: 25737 1.79% 82177 6.70%
8: 35538 2.48% 75199 6.13%
9: 52373 3.65% 69503 5.67%
10: 56226 3.92% 77039 6.28%
11: 68598 4.78% 55457 4.52%
12: 161959 11.29% 46738 3.81%
13: 205419 14.32% 34101 2.78%
14: 121905 8.50% 28397 2.31%
15: 78841 5.50% 141999 11.58%
16: 75827 5.29% 38935 3.17%
17: 70257 4.90% 267 0.02%
18: 64815 4.52% 5790 0.47%
19: 55557 3.87% 11 0.00%
20: 306358 21.36% 4236 0.35%
Num blk terms moved back = 924010
*** Completed Phase 1 route (0:00:30.7 2535.9M) ***
Total length: 1.567e+07um, number of vias: 2387155
M1(H) length: 1.627e+04um, number of vias: 932016
M2(V) length: 2.690e+06um, number of vias: 913695
M3(H) length: 3.857e+06um, number of vias: 317603
M4(V) length: 3.031e+06um, number of vias: 146855
M5(H) length: 3.131e+06um, number of vias: 70062
M6(V) length: 2.675e+06um, number of vias: 6278
M7(H) length: 2.621e+05um, number of vias: 646
M8(V) length: 7.094e+03um
*** Completed Phase 2 route (0:00:36.6 2600.9M) ***
*** Finished all Phases (cpu=0:01:09 mem=2600.9M) ***
Peak Memory Usage was 2586.8M
*** Finished trialRoute (cpu=0:01:11 mem=2600.9M) ***
Extraction called for design 'shabziger_chip' of instances=290290 and nets=263204 using extraction engine 'preRoute' .
Default RC Extraction called for design shabziger_chip.
RC Extraction called in multi-corner(2) mode.
RCMode: Default
RC Corner Indexes 0 1
Capacitance Scaling Factor : 1.00000 1.00000
Resistance Scaling Factor : 1.00000 1.00000
Clock Cap. Scaling Factor : 1.00000 1.00000
Clock Res. Scaling Factor : 1.00000 1.00000
Shrink Factor : 1.00000
Default RC extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Default RC Extraction DONE (CPU Time: 0:00:01.3 Real Time: 0:00:02.0 MEM: 2601.926M)
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
Initial Summary
------------------------------------------------------------
+--------------------+---------+
| Setup mode | all |
+--------------------+---------+
| WNS (ns):| -36.060 |
| TNS (ns):|-36436.9 |
| Violating Paths:| 26196 |
| All Paths:| 84142 |
+--------------------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 6750 (6750) | -6.686 | 6765 (6765) |
| max_tran | 7172 (53498) | -26.886 | 7186 (53528) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 51.718%
------------------------------------------------------------
**optDesign ... cpu = 0:14:06, real = 0:13:12, mem = 3656.1M **
*** Starting optimizing excluded clock nets MEM= 3656.1M) ***
*info: No excluded clock nets to be optimized.
*** Completed optimizing excluded clock nets (CPU Time= 0:00:00.0 MEM= 3656.1M) ***
*info: Start fixing DRV (Mem = 3656.12M) ...
*info: Options = -maxCap -maxTran -noMaxFanout -noSensitivity -backward -reduceBuffer -maxIter 2
*info: Start fixing DRV iteration 1 ...
*** Starting dpFixDRCViolation (3690.4M)
*info: 40 io nets excluded
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
*info: 18 clock nets excluded
*info: 4 special nets excluded.
*info: 2405 no-driver nets excluded.
*** Starting multi-driver net buffering ***
*summary: 0 non-ignored multi-driver nets.
*** Finished buffering multi-driver nets (CPU=0:00:00.0, MEM=3690.4M) ***
*info: 21 multi-driver nets excluded.
*info: There are 20 candidate Buffer cells
*info: There are 20 candidate Inverter cells
Initializing placement sections/sites ...
Density before buffering = 0.517183
Start fixing design rules ... (0:00:43.0 3798.3M)
Done fixing design rule (0:03:51 3875.7M)
Summary:
3731 buffers added on 3485 nets (with 7191 drivers resized)
Density after buffering = 0.523993
default core: bins with density > 0.75 = 6.64 % ( 514 / 7744 )
Starting refinePlace ...
move report: placeLevelShifters moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Spread Effort: high, pre-route mode.
Finished Phase I. CPU Time = 0:00:19.2, Real Time = 0:00:19.0
move report: preRPlace moves 10722 insts, mean move: 0.49 um, max move: 3.40 um
max move on inst (top/i_gmu_keccak/FE_OFC1395_n923): (1656.60, 953.40) --> (1658.20, 955.20)
move report: rPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: overall moves 10722 insts, mean move: 0.49 um, max move: 3.40 um
max move on inst (top/i_gmu_keccak/FE_OFC1395_n923): (1656.60, 953.40) --> (1658.20, 955.20)
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 3.40 um
inst (top/i_gmu_keccak/FE_OFC1395_n923) with max move: (1656.6, 953.4) -> (1658.2, 955.2)
mean (X+Y) = 0.49 um
Total instances moved : 10722
*** cpu=0:00:21.0 mem=3816.9M mem(used)=73.0M***
*** Completed dpFixDRCViolation (0:04:20 3738.8M)
moveBlkTerm was implicitly turned on (since useM1).
*** Starting trialRoute (mem=3738.5M) ***
There are 0 pin guide points passed to trialRoute.
moveBlkTerm was implicitly turned on (since useM1).
Options: -moveBlkTerm -useM1 -handlePreroute -keepMarkedOptRoutes -noPinGuide
Nr of prerouted/Fixed nets = 40
Num blk terms moved = 938530.
routingBox: (100 200) (1874900 1874800)
coreBox: (148800 148800) (1726200 1726200)
Number of multi-gpin terms=0, multi-gpins=0, moved blk term=192/151204
Phase 1a route (0:00:03.3 3843.7M):
Est net length = 1.530e+07um = 7.205e+06H + 8.092e+06V
Usage: (25.5%H 29.5%V) = (7.591e+06um 7.913e+06um) = (7585999 4395941)
Obstruct: 784086 = 288147 (16.7%H) + 495939 (28.8%V)
Overflow: 10119 = 2789 (0.19% H) + 7330 (0.60% V)
Number obstruct path=47819 reroute=0
Phase 1b route (0:00:05.0 3843.7M):
Usage: (25.8%H 29.8%V) = (7.689e+06um 7.985e+06um) = (7684219 4436063)
Overflow: 25382 = 1680 (0.12% H) + 23701 (1.93% V)
Phase 1c route (0:00:03.2 3843.7M):
Usage: (25.8%H 29.8%V) = (7.679e+06um 7.989e+06um) = (7674340 4438186)
Overflow: 21022 = 1525 (0.11% H) + 19498 (1.59% V)
Phase 1d route (0:00:02.6 3843.7M):
Usage: (25.8%H 29.8%V) = (7.680e+06um 7.991e+06um) = (7675096 4439250)
Overflow: 13750 = 358 (0.02% H) + 13392 (1.09% V)
Phase 1e route (0:00:01.9 3907.7M):
Usage: (25.8%H 29.8%V) = (7.686e+06um 7.993e+06um) = (7680716 4440547)
Overflow: 166 = 5 (0.00% H) + 161 (0.01% V)
Phase 1f route (0:00:01.7 3907.7M):
Usage: (25.8%H 29.8%V) = (7.685e+06um 7.993e+06um) = (7680506 4440555)
Overflow: 25 = 5 (0.00% H) + 20 (0.00% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-1: 5 0.00% 20 0.00%
--------------------------------------
0: 197 0.01% 3496 0.29%
1: 671 0.05% 11052 0.90%
2: 1834 0.13% 17717 1.44%
3: 6112 0.43% 32859 2.68%
4: 8312 0.58% 60938 4.97%
5: 12039 0.84% 283819 23.14%
6: 19710 1.37% 130046 10.60%
7: 23008 1.60% 86532 7.05%
8: 32796 2.29% 79953 6.52%
9: 49814 3.47% 73631 6.00%
10: 54386 3.79% 80979 6.60%
11: 68176 4.75% 59072 4.82%
12: 162495 11.33% 49686 4.05%
13: 206245 14.38% 36178 2.95%
14: 123619 8.62% 30360 2.48%
15: 80663 5.62% 141509 11.54%
16: 78281 5.46% 37992 3.10%
17: 72277 5.04% 530 0.04%
18: 67403 4.70% 5932 0.48%
19: 56631 3.95% 41 0.00%
20: 309779 21.60% 4319 0.35%
Global route (cpu=17.8s real=18.0s 3843.7M)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Phase 1l route (0:00:19.3 3763.8M):
*** After '-updateRemainTrks' operation:
Usage: (26.5%H 31.4%V) = (7.902e+06um 8.411e+06um) = (7896746 4672577)
Overflow: 1284 = 33 (0.00% H) + 1251 (0.10% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-3: 0 0.00% 14 0.00%
-2: 3 0.00% 154 0.01%
-1: 29 0.00% 1009 0.08%
--------------------------------------
0: 260 0.02% 5989 0.49%
1: 864 0.06% 16283 1.33%
2: 2239 0.16% 25824 2.11%
3: 6964 0.49% 42992 3.50%
4: 9572 0.67% 65507 5.34%
5: 14021 0.98% 284218 23.17%
6: 22436 1.56% 126911 10.35%
7: 26296 1.83% 81710 6.66%
8: 35857 2.50% 74876 6.10%
9: 52584 3.67% 69236 5.64%
10: 56764 3.96% 76733 6.26%
11: 69236 4.83% 55442 4.52%
12: 162813 11.35% 46657 3.80%
13: 205581 14.33% 34162 2.78%
14: 122164 8.52% 29069 2.37%
15: 78326 5.46% 141110 11.50%
16: 75448 5.26% 37991 3.10%
17: 69607 4.85% 525 0.04%
18: 64538 4.50% 5891 0.48%
19: 54355 3.79% 41 0.00%
20: 304496 21.23% 4317 0.35%
Num blk terms moved back = 930765
*** Completed Phase 1 route (0:00:43.1 3763.8M) ***
Total length: 1.571e+07um, number of vias: 2405261
M1(H) length: 1.183e+04um, number of vias: 939462
M2(V) length: 2.685e+06um, number of vias: 920049
M3(H) length: 3.857e+06um, number of vias: 319252
M4(V) length: 3.043e+06um, number of vias: 148046
M5(H) length: 3.111e+06um, number of vias: 71100
M6(V) length: 2.687e+06um, number of vias: 6714
M7(H) length: 3.068e+05um, number of vias: 638
M8(V) length: 6.941e+03um
*** Completed Phase 2 route (0:00:43.0 3738.5M) ***
*** Finished all Phases (cpu=0:01:28 mem=3738.5M) ***
Peak Memory Usage was 3843.7M
*** Finished trialRoute (cpu=0:01:31 mem=3738.5M) ***
Extraction called for design 'shabziger_chip' of instances=294021 and nets=266935 using extraction engine 'preRoute' .
Default RC Extraction called for design shabziger_chip.
RC Extraction called in multi-corner(2) mode.
RCMode: Default
RC Corner Indexes 0 1
Capacitance Scaling Factor : 1.00000 1.00000
Resistance Scaling Factor : 1.00000 1.00000
Clock Cap. Scaling Factor : 1.00000 1.00000
Clock Res. Scaling Factor : 1.00000 1.00000
Shrink Factor : 1.00000
Default RC extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Default RC Extraction DONE (CPU Time: 0:00:01.6 Real Time: 0:00:02.0 MEM: 3737.523M)
Using new Cte TW Api base...#################################################################################
# Design Stage: PreRoute
# Design Mode: 65nm
# Analysis Mode: MMMC non-OCV
# Extraction Mode: default
# Delay Calculation Options: engine=signalStorm signOff=true SIAware=false(opt)
# Switching Delay Calculation Engine to signalStorm
#################################################################################
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.6, MEM = 3062.6M, InitMEM = 3063.1M)
Start delay calculation using Signal Storm (mem=3062.629M)...
Delay calculation completed. (cpu=0:00:55.5 real=0:00:55.0 mem=3360.949M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3360.9M, InitMEM = 3360.9M)
Start delay calculation using Signal Storm (mem=3360.949M)...
Delay calculation completed. (cpu=0:00:29.0 real=0:00:29.0 mem=3360.949M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3360.9M, InitMEM = 3360.9M)
Start delay calculation using Signal Storm (mem=3360.949M)...
Delay calculation completed. (cpu=0:00:29.9 real=0:00:30.0 mem=3360.949M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3360.9M, InitMEM = 3360.9M)
Start delay calculation using Signal Storm (mem=3360.949M)...
Delay calculation completed. (cpu=0:00:29.6 real=0:00:30.0 mem=3360.949M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3360.9M, InitMEM = 3360.9M)
Start delay calculation using Signal Storm (mem=3360.949M)...
Delay calculation completed. (cpu=0:00:29.4 real=0:00:29.0 mem=3360.949M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3360.9M, InitMEM = 3360.9M)
Start delay calculation using Signal Storm (mem=3360.949M)...
Delay calculation completed. (cpu=0:00:28.7 real=0:00:29.0 mem=3360.949M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3360.9M, InitMEM = 3360.9M)
Start delay calculation using Signal Storm (mem=3360.949M)...
Delay calculation completed. (cpu=0:00:29.2 real=0:00:29.0 mem=3360.949M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3360.9M, InitMEM = 3360.9M)
Start delay calculation using Signal Storm (mem=3360.949M)...
Delay calculation completed. (cpu=0:00:28.9 real=0:00:29.0 mem=3360.949M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3360.9M, InitMEM = 3360.9M)
Start delay calculation using Signal Storm (mem=3360.949M)...
Delay calculation completed. (cpu=0:00:30.6 real=0:00:31.0 mem=3360.949M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 3360.9M, InitMEM = 3360.9M)
Start delay calculation using Signal Storm (mem=3360.949M)...
Delay calculation completed. (cpu=0:00:29.1 real=0:00:29.0 mem=3360.949M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3360.9M, InitMEM = 3360.9M)
Start delay calculation using Signal Storm (mem=3360.949M)...
Delay calculation completed. (cpu=0:00:29.9 real=0:00:30.0 mem=3360.949M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3360.9M, InitMEM = 3360.9M)
Start delay calculation using Signal Storm (mem=3360.949M)...
Delay calculation completed. (cpu=0:00:29.0 real=0:00:29.0 mem=3360.949M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3360.9M, InitMEM = 3360.9M)
Start delay calculation using Signal Storm (mem=3360.949M)...
Delay calculation completed. (cpu=0:00:31.2 real=0:00:31.0 mem=3360.949M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3360.9M, InitMEM = 3360.9M)
Start delay calculation using Signal Storm (mem=3360.949M)...
Delay calculation completed. (cpu=0:00:29.1 real=0:00:29.0 mem=3360.949M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 3360.9M, InitMEM = 3360.9M)
Start delay calculation using Signal Storm (mem=3360.949M)...
Delay calculation completed. (cpu=0:00:29.7 real=0:00:30.0 mem=3360.949M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 3360.9M, InitMEM = 3360.9M)
Start delay calculation using Signal Storm (mem=3360.949M)...
Delay calculation completed. (cpu=0:00:29.4 real=0:00:29.0 mem=3360.949M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 3360.9M, InitMEM = 3360.9M)
Start delay calculation using Signal Storm (mem=3360.949M)...
Delay calculation completed. (cpu=0:00:43.1 real=0:00:43.0 mem=3360.949M 0)
*** CDM Built up (cpu=0:10:11 real=0:10:11 mem= 3360.9M) ***
*info: DRV Fixing Iteration 1.
*info: Remaining violations:
*info: Max cap violations: 8
*info: Max tran violations: 236
*info: Prev Max cap violations: 6750
*info: Prev Max tran violations: 53498
*info: Start fixing DRV iteration 2 ...
*** Starting dpFixDRCViolation (3671.4M)
*info: 40 io nets excluded
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
*info: 18 clock nets excluded
*info: 4 special nets excluded.
*info: 2405 no-driver nets excluded.
*** Starting multi-driver net buffering ***
*summary: 0 non-ignored multi-driver nets.
*** Finished buffering multi-driver nets (CPU=0:00:00.0, MEM=3671.4M) ***
*info: 21 multi-driver nets excluded.
Start fixing design rules ... (0:00:05.1 3864.9M)
Done fixing design rule (0:01:08 3874.2M)
Summary:
91 buffers added on 91 nets (with 789 drivers resized)
Density after buffering = 0.524296
default core: bins with density > 0.75 = 6.71 % ( 520 / 7744 )
Starting refinePlace ...
move report: placeLevelShifters moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Spread Effort: high, pre-route mode.
Finished Phase I. CPU Time = 0:00:19.6, Real Time = 0:00:19.0
move report: preRPlace moves 955 insts, mean move: 0.29 um, max move: 2.20 um
max move on inst (top/FE_OFC3778_In2xD_501_): (468.80, 611.40) --> (468.40, 609.60)
move report: rPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: overall moves 955 insts, mean move: 0.29 um, max move: 2.20 um
max move on inst (top/FE_OFC3778_In2xD_501_): (468.80, 611.40) --> (468.40, 609.60)
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 2.20 um
inst (top/FE_OFC3778_In2xD_501_) with max move: (468.8, 611.4) -> (468.4, 609.6)
mean (X+Y) = 0.29 um
Total instances moved : 955
*** cpu=0:00:21.1 mem=3771.1M mem(used)=87.1M***
*** Completed dpFixDRCViolation (0:01:38 3677.9M)
moveBlkTerm was implicitly turned on (since useM1).
*** Starting trialRoute (mem=3677.6M) ***
There are 0 pin guide points passed to trialRoute.
moveBlkTerm was implicitly turned on (since useM1).
Options: -moveBlkTerm -useM1 -handlePreroute -keepMarkedOptRoutes -noPinGuide
Nr of prerouted/Fixed nets = 40
Num blk terms moved = 938712.
routingBox: (100 200) (1874900 1874800)
coreBox: (148800 148800) (1726200 1726200)
Number of multi-gpin terms=0, multi-gpins=0, moved blk term=192/151232
Phase 1a route (0:00:03.3 3784.1M):
Est net length = 1.530e+07um = 7.206e+06H + 8.092e+06V
Usage: (25.5%H 29.5%V) = (7.592e+06um 7.913e+06um) = (7586829 4395953)
Obstruct: 784085 = 288147 (16.7%H) + 495938 (28.8%V)
Overflow: 9945 = 2791 (0.19% H) + 7154 (0.58% V)
Number obstruct path=47808 reroute=0
Phase 1b route (0:00:05.2 3789.6M):
Usage: (25.8%H 29.8%V) = (7.690e+06um 7.985e+06um) = (7685070 4436031)
Overflow: 25433 = 1680 (0.12% H) + 23753 (1.94% V)
Phase 1c route (0:00:03.5 3789.6M):
Usage: (25.8%H 29.8%V) = (7.680e+06um 7.989e+06um) = (7675088 4438180)
Overflow: 20938 = 1527 (0.11% H) + 19410 (1.58% V)
Phase 1d route (0:00:02.8 3789.6M):
Usage: (25.8%H 29.8%V) = (7.681e+06um 7.991e+06um) = (7675831 4439254)
Overflow: 13787 = 358 (0.02% H) + 13429 (1.09% V)
Phase 1e route (0:00:02.0 3854.6M):
Usage: (25.8%H 29.8%V) = (7.687e+06um 7.993e+06um) = (7681411 4440547)
Overflow: 169 = 5 (0.00% H) + 164 (0.01% V)
Phase 1f route (0:00:01.8 3854.6M):
Usage: (25.8%H 29.8%V) = (7.686e+06um 7.993e+06um) = (7681170 4440562)
Overflow: 25 = 5 (0.00% H) + 20 (0.00% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-1: 5 0.00% 20 0.00%
--------------------------------------
0: 201 0.01% 3433 0.28%
1: 690 0.05% 11095 0.90%
2: 1888 0.13% 17667 1.44%
3: 6047 0.42% 32802 2.67%
4: 8348 0.58% 60755 4.95%
5: 12020 0.84% 283907 23.14%
6: 19894 1.39% 130206 10.61%
7: 22983 1.60% 87060 7.10%
8: 32656 2.28% 80084 6.53%
9: 49958 3.48% 73222 5.97%
10: 54204 3.78% 81123 6.61%
11: 68323 4.76% 58485 4.77%
12: 162940 11.36% 49628 4.05%
13: 205802 14.35% 36293 2.96%
14: 123609 8.62% 30427 2.48%
15: 80643 5.62% 141560 11.54%
16: 78199 5.45% 38073 3.10%
17: 72254 5.04% 530 0.04%
18: 67421 4.70% 5932 0.48%
19: 56484 3.94% 41 0.00%
20: 309884 21.60% 4319 0.35%
Global route (cpu=18.7s real=18.0s 3784.7M)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Phase 1l route (0:00:19.8 3705.9M):
*** After '-updateRemainTrks' operation:
Usage: (26.5%H 31.4%V) = (7.903e+06um 8.411e+06um) = (7897663 4672796)
Overflow: 1258 = 29 (0.00% H) + 1228 (0.10% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-3: 0 0.00% 12 0.00%
-2: 1 0.00% 151 0.01%
-1: 28 0.00% 994 0.08%
--------------------------------------
0: 261 0.02% 5857 0.48%
1: 890 0.06% 16415 1.34%
2: 2297 0.16% 25733 2.10%
3: 6926 0.48% 43074 3.51%
4: 9683 0.68% 65230 5.32%
5: 13900 0.97% 284381 23.18%
6: 22582 1.57% 127127 10.36%
7: 26414 1.84% 82185 6.70%
8: 35612 2.48% 75071 6.12%
9: 52819 3.68% 68688 5.60%
10: 56498 3.94% 76800 6.26%
11: 69538 4.85% 54856 4.47%
12: 163098 11.37% 46642 3.80%
13: 205035 14.29% 34318 2.80%
14: 122202 8.52% 29118 2.37%
15: 78148 5.45% 141156 11.51%
16: 75521 5.26% 38080 3.10%
17: 69647 4.86% 525 0.04%
18: 64618 4.50% 5891 0.48%
19: 54176 3.78% 41 0.00%
20: 304559 21.23% 4317 0.35%
Num blk terms moved back = 930946
*** Completed Phase 1 route (0:00:44.7 3703.9M) ***
Total length: 1.571e+07um, number of vias: 2406112
M1(H) length: 1.190e+04um, number of vias: 939663
M2(V) length: 2.686e+06um, number of vias: 920267
M3(H) length: 3.859e+06um, number of vias: 319239
M4(V) length: 3.037e+06um, number of vias: 148352
M5(H) length: 3.111e+06um, number of vias: 71051
M6(V) length: 2.692e+06um, number of vias: 6837
M7(H) length: 3.048e+05um, number of vias: 703
M8(V) length: 7.048e+03um
*** Completed Phase 2 route (0:00:43.3 3677.6M) ***
*** Finished all Phases (cpu=0:01:30 mem=3677.6M) ***
Peak Memory Usage was 3793.0M
*** Finished trialRoute (cpu=0:01:34 mem=3677.6M) ***
Extraction called for design 'shabziger_chip' of instances=294112 and nets=267026 using extraction engine 'preRoute' .
Default RC Extraction called for design shabziger_chip.
RC Extraction called in multi-corner(2) mode.
RCMode: Default
RC Corner Indexes 0 1
Capacitance Scaling Factor : 1.00000 1.00000
Resistance Scaling Factor : 1.00000 1.00000
Clock Cap. Scaling Factor : 1.00000 1.00000
Clock Res. Scaling Factor : 1.00000 1.00000
Shrink Factor : 1.00000
Default RC extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Default RC Extraction DONE (CPU Time: 0:00:01.7 Real Time: 0:00:01.0 MEM: 3677.637M)
Using new Cte TW Api base...#################################################################################
# Design Stage: PreRoute
# Design Mode: 65nm
# Analysis Mode: MMMC non-OCV
# Extraction Mode: default
# Delay Calculation Options: engine=signalStorm signOff=true SIAware=false(opt)
# Switching Delay Calculation Engine to signalStorm
#################################################################################
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.6, MEM = 3062.6M, InitMEM = 3062.6M)
Start delay calculation using Signal Storm (mem=3062.629M)...
Delay calculation completed. (cpu=0:00:55.9 real=0:00:56.0 mem=3360.949M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 3360.9M, InitMEM = 3360.9M)
Start delay calculation using Signal Storm (mem=3360.949M)...
Delay calculation completed. (cpu=0:00:29.7 real=0:00:29.0 mem=3360.949M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3360.9M, InitMEM = 3360.9M)
Start delay calculation using Signal Storm (mem=3360.949M)...
Delay calculation completed. (cpu=0:00:30.1 real=0:00:31.0 mem=3360.949M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3360.9M, InitMEM = 3360.9M)
Start delay calculation using Signal Storm (mem=3360.949M)...
Delay calculation completed. (cpu=0:00:29.8 real=0:00:29.0 mem=3360.949M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 3360.9M, InitMEM = 3360.9M)
Start delay calculation using Signal Storm (mem=3360.949M)...
Delay calculation completed. (cpu=0:00:30.4 real=0:00:31.0 mem=3360.949M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 3360.9M, InitMEM = 3360.9M)
Start delay calculation using Signal Storm (mem=3360.949M)...
Delay calculation completed. (cpu=0:00:29.7 real=0:00:29.0 mem=3360.949M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 3360.9M, InitMEM = 3360.9M)
Start delay calculation using Signal Storm (mem=3360.949M)...
Delay calculation completed. (cpu=0:00:30.7 real=0:00:30.0 mem=3360.949M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.1, MEM = 3360.9M, InitMEM = 3360.9M)
Start delay calculation using Signal Storm (mem=3360.949M)...
Delay calculation completed. (cpu=0:00:30.1 real=0:00:31.0 mem=3360.949M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 3360.9M, InitMEM = 3360.9M)
Start delay calculation using Signal Storm (mem=3360.949M)...
Delay calculation completed. (cpu=0:00:31.6 real=0:00:31.0 mem=3360.949M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 3360.9M, InitMEM = 3360.9M)
Start delay calculation using Signal Storm (mem=3360.949M)...
Delay calculation completed. (cpu=0:00:29.4 real=0:00:30.0 mem=3360.949M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 3360.9M, InitMEM = 3360.9M)
Start delay calculation using Signal Storm (mem=3360.949M)...
Delay calculation completed. (cpu=0:00:30.3 real=0:00:30.0 mem=3360.949M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 3360.9M, InitMEM = 3360.9M)
Start delay calculation using Signal Storm (mem=3360.949M)...
Delay calculation completed. (cpu=0:00:29.6 real=0:00:30.0 mem=3360.949M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 3360.9M, InitMEM = 3360.9M)
Start delay calculation using Signal Storm (mem=3360.949M)...
Delay calculation completed. (cpu=0:00:31.2 real=0:00:31.0 mem=3360.949M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3360.9M, InitMEM = 3360.9M)
Start delay calculation using Signal Storm (mem=3360.949M)...
Delay calculation completed. (cpu=0:00:28.6 real=0:00:29.0 mem=3360.949M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3360.9M, InitMEM = 3360.9M)
Start delay calculation using Signal Storm (mem=3360.949M)...
Delay calculation completed. (cpu=0:00:29.2 real=0:00:29.0 mem=3360.949M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3360.9M, InitMEM = 3360.9M)
Start delay calculation using Signal Storm (mem=3360.949M)...
Delay calculation completed. (cpu=0:00:29.4 real=0:00:29.0 mem=3360.949M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3360.9M, InitMEM = 3360.9M)
Start delay calculation using Signal Storm (mem=3360.949M)...
Delay calculation completed. (cpu=0:00:37.9 real=0:00:38.0 mem=3360.949M 0)
*** CDM Built up (cpu=0:10:15 real=0:10:15 mem= 3360.9M) ***
*info: DRV Fixing Iteration 2.
*info: Remaining violations:
*info: Max cap violations: 0
*info: Max tran violations: 8
*info: Prev Max cap violations: 8
*info: Prev Max tran violations: 236
*info: Start fixing DRV while maintaining existing placement ...
*** Starting dpFixDRCViolation (3671.2M)
*info: 40 io nets excluded
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
*info: 18 clock nets excluded
*info: 4 special nets excluded.
*info: 2405 no-driver nets excluded.
*** Starting multi-driver net buffering ***
*summary: 0 non-ignored multi-driver nets.
*** Finished buffering multi-driver nets (CPU=0:00:00.0, MEM=3671.2M) ***
*info: 21 multi-driver nets excluded.
Start fixing design rules ... (0:00:04.8 3865.8M)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Done fixing design rule (0:01:03 3842.8M)
Summary:
408 buffers added on 408 nets (with 0 driver resized)
Density after buffering = 0.526401
default core: bins with density > 0.75 = 6.86 % ( 531 / 7744 )
Starting refinePlace ...
move report: placeLevelShifters moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Spread Effort: high, pre-route mode.
Finished Phase I. CPU Time = 0:00:15.5, Real Time = 0:00:15.0
move report: preRPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: rPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: overall moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 0.00 um
mean (X+Y) = 0.00 um
Total instances moved : 0
*** cpu=0:00:16.9 mem=3744.8M mem(used)=0.0M***
*** Completed dpFixDRCViolation (0:01:27 3738.6M)
moveBlkTerm was implicitly turned on (since useM1).
*** Starting trialRoute (mem=3738.4M) ***
There are 0 pin guide points passed to trialRoute.
moveBlkTerm was implicitly turned on (since useM1).
Options: -moveBlkTerm -useM1 -handlePreroute -keepMarkedOptRoutes -noPinGuide
Nr of prerouted/Fixed nets = 40
Num blk terms moved = 939528.
routingBox: (100 200) (1874900 1874800)
coreBox: (148800 148800) (1726200 1726200)
Number of multi-gpin terms=0, multi-gpins=0, moved blk term=192/151400
Phase 1a route (0:00:03.1 3843.5M):
Est net length = 1.530e+07um = 7.207e+06H + 8.093e+06V
Usage: (25.5%H 29.5%V) = (7.593e+06um 7.914e+06um) = (7588062 4396803)
Obstruct: 784085 = 288147 (16.7%H) + 495938 (28.8%V)
Overflow: 9799 = 2852 (0.20% H) + 6947 (0.57% V)
Number obstruct path=47870 reroute=0
Phase 1b route (0:00:05.0 3843.5M):
Usage: (25.8%H 29.8%V) = (7.691e+06um 7.987e+06um) = (7686219 4437035)
Overflow: 25427 = 1689 (0.12% H) + 23738 (1.94% V)
Phase 1c route (0:00:03.4 3843.5M):
Usage: (25.8%H 29.8%V) = (7.682e+06um 7.990e+06um) = (7676427 4439106)
Overflow: 21188 = 1542 (0.11% H) + 19646 (1.60% V)
Phase 1d route (0:00:02.7 3843.5M):
Usage: (25.8%H 29.8%V) = (7.682e+06um 7.992e+06um) = (7677175 4440173)
Overflow: 13903 = 357 (0.02% H) + 13546 (1.10% V)
Phase 1e route (0:00:01.9 3907.5M):
Usage: (25.8%H 29.8%V) = (7.688e+06um 7.995e+06um) = (7682802 4441477)
Overflow: 169 = 5 (0.00% H) + 164 (0.01% V)
Phase 1f route (0:00:01.8 3907.5M):
Usage: (25.8%H 29.8%V) = (7.688e+06um 7.995e+06um) = (7682560 4441487)
Overflow: 26 = 5 (0.00% H) + 21 (0.00% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-1: 5 0.00% 21 0.00%
--------------------------------------
0: 209 0.01% 3511 0.29%
1: 664 0.05% 11166 0.91%
2: 1884 0.13% 17598 1.43%
3: 6192 0.43% 32859 2.68%
4: 8299 0.58% 60566 4.94%
5: 12109 0.84% 283600 23.12%
6: 19999 1.39% 130514 10.64%
7: 23289 1.62% 86899 7.08%
8: 32753 2.28% 80529 6.56%
9: 49807 3.47% 73379 5.98%
10: 54913 3.83% 81155 6.62%
11: 68001 4.74% 58579 4.78%
12: 163299 11.38% 49191 4.01%
13: 206221 14.38% 36348 2.96%
14: 123491 8.61% 30513 2.49%
15: 80134 5.59% 141409 11.53%
16: 78194 5.45% 37996 3.10%
17: 72238 5.04% 465 0.04%
18: 67047 4.67% 6004 0.49%
19: 56333 3.93% 41 0.00%
20: 309372 21.57% 4319 0.35%
Global route (cpu=18.0s real=18.0s 3843.5M)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Phase 1l route (0:00:18.8 3764.7M):
*** After '-updateRemainTrks' operation:
Usage: (26.5%H 31.4%V) = (7.905e+06um 8.413e+06um) = (7899275 4674002)
Overflow: 1227 = 29 (0.00% H) + 1198 (0.10% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-3: 0 0.00% 13 0.00%
-2: 2 0.00% 149 0.01%
-1: 26 0.00% 965 0.08%
--------------------------------------
0: 267 0.02% 6020 0.49%
1: 861 0.06% 16418 1.34%
2: 2293 0.16% 25726 2.10%
3: 7029 0.49% 43088 3.51%
4: 9646 0.67% 64992 5.30%
5: 13994 0.98% 284150 23.16%
6: 22778 1.59% 127338 10.38%
7: 26652 1.86% 82206 6.70%
8: 35885 2.50% 75549 6.16%
9: 52663 3.67% 68763 5.61%
10: 57059 3.98% 76727 6.25%
11: 69299 4.83% 54965 4.48%
12: 163272 11.38% 46230 3.77%
13: 205581 14.33% 34366 2.80%
14: 122047 8.51% 29212 2.38%
15: 77687 5.42% 141004 11.49%
16: 75567 5.27% 37995 3.10%
17: 69571 4.85% 470 0.04%
18: 64149 4.47% 5958 0.49%
19: 54044 3.77% 41 0.00%
20: 304081 21.20% 4317 0.35%
Num blk terms moved back = 931753
*** Completed Phase 1 route (0:00:42.7 3764.7M) ***
Total length: 1.571e+07um, number of vias: 2408123
M1(H) length: 1.098e+04um, number of vias: 940474
M2(V) length: 2.680e+06um, number of vias: 920677
M3(H) length: 3.864e+06um, number of vias: 319795
M4(V) length: 3.041e+06um, number of vias: 148383
M5(H) length: 3.107e+06um, number of vias: 71182
M6(V) length: 2.696e+06um, number of vias: 6911
M7(H) length: 3.062e+05um, number of vias: 701
M8(V) length: 6.804e+03um
*** Completed Phase 2 route (0:00:45.3 3738.4M) ***
*** Finished all Phases (cpu=0:01:30 mem=3738.4M) ***
Peak Memory Usage was 3843.5M
*** Finished trialRoute (cpu=0:01:34 mem=3738.4M) ***
Extraction called for design 'shabziger_chip' of instances=294520 and nets=267434 using extraction engine 'preRoute' .
Default RC Extraction called for design shabziger_chip.
RC Extraction called in multi-corner(2) mode.
RCMode: Default
RC Corner Indexes 0 1
Capacitance Scaling Factor : 1.00000 1.00000
Resistance Scaling Factor : 1.00000 1.00000
Clock Cap. Scaling Factor : 1.00000 1.00000
Clock Res. Scaling Factor : 1.00000 1.00000
Shrink Factor : 1.00000
Default RC extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Default RC Extraction DONE (CPU Time: 0:00:02.0 Real Time: 0:00:02.0 MEM: 3738.379M)
Using new Cte TW Api base...#################################################################################
# Design Stage: PreRoute
# Design Mode: 65nm
# Analysis Mode: MMMC non-OCV
# Extraction Mode: default
# Delay Calculation Options: engine=signalStorm signOff=true SIAware=false(opt)
# Switching Delay Calculation Engine to signalStorm
#################################################################################
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:02.4, MEM = 3129.5M, InitMEM = 3129.5M)
Start delay calculation using Signal Storm (mem=3129.512M)...
Delay calculation completed. (cpu=0:01:20 real=0:01:20 mem=3427.832M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.4, MEM = 3427.8M, InitMEM = 3427.8M)
Start delay calculation using Signal Storm (mem=3427.832M)...
Delay calculation completed. (cpu=0:00:40.7 real=0:00:40.0 mem=3427.832M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.4, MEM = 3427.8M, InitMEM = 3427.8M)
Start delay calculation using Signal Storm (mem=3427.832M)...
Delay calculation completed. (cpu=0:00:40.8 real=0:00:41.0 mem=3427.832M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.4, MEM = 3427.8M, InitMEM = 3427.8M)
Start delay calculation using Signal Storm (mem=3427.832M)...
Delay calculation completed. (cpu=0:00:40.8 real=0:00:41.0 mem=3427.832M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.5, MEM = 3427.8M, InitMEM = 3427.8M)
Start delay calculation using Signal Storm (mem=3427.832M)...
Delay calculation completed. (cpu=0:00:40.8 real=0:00:40.0 mem=3427.832M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.4, MEM = 3427.8M, InitMEM = 3427.8M)
Start delay calculation using Signal Storm (mem=3427.832M)...
Delay calculation completed. (cpu=0:00:40.1 real=0:00:40.0 mem=3427.832M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.4, MEM = 3427.8M, InitMEM = 3427.8M)
Start delay calculation using Signal Storm (mem=3427.832M)...
Delay calculation completed. (cpu=0:00:40.7 real=0:00:41.0 mem=3427.832M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.4, MEM = 3427.8M, InitMEM = 3427.8M)
Start delay calculation using Signal Storm (mem=3427.832M)...
Delay calculation completed. (cpu=0:00:40.7 real=0:00:40.0 mem=3427.832M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.5, MEM = 3427.8M, InitMEM = 3427.8M)
Start delay calculation using Signal Storm (mem=3427.832M)...
Delay calculation completed. (cpu=0:00:42.3 real=0:00:42.0 mem=3427.832M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.4, MEM = 3427.8M, InitMEM = 3427.8M)
Start delay calculation using Signal Storm (mem=3427.832M)...
Delay calculation completed. (cpu=0:00:40.6 real=0:00:40.0 mem=3427.832M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.5, MEM = 3427.8M, InitMEM = 3427.8M)
Start delay calculation using Signal Storm (mem=3427.832M)...
Delay calculation completed. (cpu=0:00:42.2 real=0:00:42.0 mem=3427.832M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.4, MEM = 3427.8M, InitMEM = 3427.8M)
Start delay calculation using Signal Storm (mem=3427.832M)...
Delay calculation completed. (cpu=0:00:40.6 real=0:00:40.0 mem=3427.832M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.4, MEM = 3427.8M, InitMEM = 3427.8M)
Start delay calculation using Signal Storm (mem=3427.832M)...
Delay calculation completed. (cpu=0:00:43.5 real=0:00:43.0 mem=3427.832M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.4, MEM = 3427.8M, InitMEM = 3427.8M)
Start delay calculation using Signal Storm (mem=3427.832M)...
Delay calculation completed. (cpu=0:00:39.7 real=0:00:39.0 mem=3427.832M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.4, MEM = 3427.8M, InitMEM = 3427.8M)
Start delay calculation using Signal Storm (mem=3427.832M)...
Delay calculation completed. (cpu=0:00:40.4 real=0:00:40.0 mem=3427.832M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.4, MEM = 3427.8M, InitMEM = 3427.8M)
Start delay calculation using Signal Storm (mem=3427.832M)...
Delay calculation completed. (cpu=0:00:40.2 real=0:00:40.0 mem=3427.832M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.5, MEM = 3427.8M, InitMEM = 3427.8M)
Start delay calculation using Signal Storm (mem=3427.832M)...
Delay calculation completed. (cpu=0:00:55.7 real=0:00:56.0 mem=3427.832M 0)
*** CDM Built up (cpu=0:14:12 real=0:14:12 mem= 3427.8M) ***
*info: DRV Fixing Iteration 3.
*info: Remaining violations:
*info: Max cap violations: 3
*info: Max tran violations: 13
*info: Prev Max cap violations: 0
*info: Prev Max tran violations: 8
*info:
*info: Completed fixing DRV (CPU Time = 0:51:41, Mem = 3711.95M).
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
Summary (cpu=51.68min real=51.68min mem=3712.0M)
------------------------------------------------------------
+--------------------+---------+
| Setup mode | all |
+--------------------+---------+
| WNS (ns):| -3.053 |
| TNS (ns):| -9890.0 |
| Violating Paths:| 22190 |
| All Paths:| 85005 |
+--------------------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 3 (3) | -0.025 | 18 (18) |
| max_tran | 4 (13) | -0.434 | 17 (26) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 52.640%
Routing Overflow: 0.00% H and 0.10% V
------------------------------------------------------------
**optDesign ... cpu = 1:06:33, real = 1:05:40, mem = 3712.0M **
Reported timing to dir timingReports_final
**optDesign ... cpu = 1:06:46, real = 1:05:52, mem = 3427.8M **
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
optDesign Final Summary
------------------------------------------------------------
+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| -3.053 | -3.053 | -0.620 | 2.578 | 19.391 | 14.811 |
| TNS (ns):| -9890.0 | -8334.8 | -1555.2 | 0.000 | 0.000 | 0.000 |
| Violating Paths:| 22190 | 17071 | 5119 | 0 | 0 | 0 |
| All Paths:| 85005 | 46605 | 63302 | 19 | 2 | 15 |
+--------------------+---------+---------+---------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 3 (3) | -0.025 | 18 (18) |
| max_tran | 4 (13) | -0.434 | 17 (26) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 52.640%
Routing Overflow: 0.00% H and 0.10% V
------------------------------------------------------------
**optDesign ... cpu = 1:09:37, real = 1:07:41, mem = 3438.1M **
*info: Setting setup target slack to 0.000
*info: Hold target slack is 0.000
**INFO : removing temp dont-use cells (LVT only flow version : 4)
Deleting the dont_use list
**WARN: (ENCOPT-3195): Changed analysis mode: setAnalysisMode -clkSrcPath false -clockPropagation forcedIdeal
*** Finished optDesign ***
timeDesign -reportOnly -expandedViews -outDir timingReports_final -prefix shabziger.preCTS-drv.expV
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
timeDesign Summary
------------------------------------------------------------
+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| -3.053 | -3.053 | -0.620 | 2.578 | 19.391 | 14.811 |
| TNS (ns):| -9890.0 | -8334.8 | -1555.2 | 0.000 | 0.000 | 0.000 |
| Violating Paths:| 22190 | 17071 | 5119 | 0 | 0 | 0 |
| All Paths:| 85005 | 46605 | 63302 | 19 | 2 | 15 |
+--------------------+---------+---------+---------+---------+---------+---------+
|dummy_slow_view | 6.516 | 6.516 | 7.780 | 10.978 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5131 | 2517 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_blake_slow_view| -0.282 | -0.282 | 2.780 | 5.978 | N/A | N/A |
| | -1.207 | -1.207 | 0.000 | 0.000 | N/A | N/A |
| | 8 | 8 | 0 | 0 | N/A | N/A |
| | 8290 | 4385 | 3887 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_groestl_slow_view
| | -2.078 | -2.078 | 1.380 | 4.578 | N/A | N/A |
| |-848.626 |-848.626 | 0.000 | 0.000 | N/A | N/A |
| | 1709 | 1709 | 0 | 0 | N/A | N/A |
| | 8236 | 4070 | 4148 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_jh_slow_view | -1.444 | -1.444 | 0.780 | 3.978 | N/A | N/A |
| |-605.441 |-605.441 | 0.000 | 0.000 | N/A | N/A |
| | 1051 | 1051 | 0 | 0 | N/A | N/A |
| | 8801 | 4640 | 4143 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_keccak_slow_view
| | -1.881 | -1.881 | -0.599 | 2.978 | N/A | N/A |
| | -2286.0 | -1471.5 |-814.464 | 0.000 | N/A | N/A |
| | 5544 | 3810 | 1734 | 0 | N/A | N/A |
| | 8346 | 4125 | 4203 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_sha2_slow_view | -0.464 | -0.464 | 1.154 | 4.478 | N/A | N/A |
| | -15.577 | -15.577 | 0.000 | 0.000 | N/A | N/A |
| | 87 | 87 | 0 | 0 | N/A | N/A |
| | 7204 | 3554 | 3632 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_skein_slow_view| -1.759 | -1.759 | 0.580 | 3.778 | N/A | N/A |
| |-204.889 |-204.889 | 0.000 | 0.000 | N/A | N/A |
| | 611 | 611 | 0 | 0 | N/A | N/A |
| | 9002 | 4517 | 4467 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_blake_slow_view | -1.382 | -1.382 | 1.680 | 4.878 | N/A | N/A |
| |-235.466 |-235.466 | 0.000 | 0.000 | N/A | N/A |
| | 443 | 443 | 0 | 0 | N/A | N/A |
| | 9724 | 5498 | 4208 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_groestl_slow_view
| | -1.604 | -1.604 | -0.120 | 3.078 | N/A | N/A |
| | -1330.2 | -1325.2 | -5.056 | 0.000 | N/A | N/A |
| | 4450 | 4385 | 65 | 0 | N/A | N/A |
| | 9252 | 5088 | 4146 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_jh_slow_view | -1.651 | -1.651 | -0.620 | 2.578 | N/A | N/A |
| | -3429.2 | -2900.8 |-528.397 | 0.000 | N/A | N/A |
| | 7554 | 5380 | 2174 | 0 | N/A | N/A |
| | 10269 | 5853 | 4398 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_keccak_slow_view| -1.651 | -1.651 | -0.620 | 2.578 | N/A | N/A |
| | -3095.0 | -2850.5 |-244.507 | 0.000 | N/A | N/A |
| | 6643 | 5473 | 1170 | 0 | N/A | N/A |
| | 9926 | 5702 | 4206 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_sha2_slow_view | -2.346 | -2.346 | -0.507 | 2.778 | N/A | N/A |
| | -1812.8 | -1661.3 |-151.428 | 0.000 | N/A | N/A |
| | 4231 | 3354 | 877 | 0 | N/A | N/A |
| | 7986 | 4238 | 3730 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_skein_slow_view | -3.053 | -3.053 | 0.798 | 6.478 | N/A | N/A |
| | -1107.5 | -1107.5 | 0.000 | 0.000 | N/A | N/A |
| | 631 | 631 | 0 | 0 | N/A | N/A |
| | 10156 | 5551 | 4587 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ram1_slow_view | 4.567 | 4.567 | 7.780 | 10.978 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5237 | 2623 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ram2_slow_view | 4.388 | 4.388 | 7.780 | 10.978 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5237 | 2623 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ram3_slow_view | 2.776 | 2.776 | 7.780 | 10.978 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5240 | 2626 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|test_slow_view | 10.797 | 11.447 | 10.797 | 20.978 | 19.391 | 14.811 |
| | 0.000 | 0.000 | 0.000 | 0.000 | 0.000 | 0.000 |
| | 0 | 0 | 0 | 0 | 0 | 0 |
| | 85005 | 46605 | 63302 | 19 | 2 | 15 |
+--------------------+---------+---------+---------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 3 (3) | -0.025 | 18 (18) |
| max_tran | 4 (13) | -0.434 | 17 (26) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 52.640%
------------------------------------------------------------
Reported timing to dir timingReports_final
Total CPU time: 283.26 sec
Total Real time: 225.0 sec
Total Memory Usage: 3442.125 Mbytes
setOptMode -setupTargetSlack -.050
*info: Setting setup target slack to -0.050
*info: Hold target slack is 0.000
optDesign -preCTS -outDir timingReports_final -prefix shabziger.preCTS-opt
**WARN: (PRL-55): Reducing the number of threads from 8 to 5 due to memory limitations
Enabling multi-CPU acceleration with 5 CPU(s) for optimization
Connected to aotearoa.ee.ethz.ch 41090 0
Connected to aotearoa.ee.ethz.ch 47813 1
Connected to aotearoa.ee.ethz.ch 43346 2
Connected to aotearoa.ee.ethz.ch 53993 3
Connected to aotearoa.ee.ethz.ch 57011 4
*** Finished dispatch of slaves (cpu=0:00:31.2) (real=0:00:55.0) ***
**WARN: (ENCOPT-6055): The following cells have a dont_touch property but without being dont_use.
Such configuration can impact the timing closure because they can be inserted in the netlist but never transformed again.
It is recommended that you apply a dont_use attribute on them.
Cell SYKA65_2048X32X1CM8 is dont_touch but not dont_use
Cell SHKA65_2048X32X1CM4 is dont_touch but not dont_use
Cell SHKA65_16384X32X1CM16 is dont_touch but not dont_use
...
Reporting only the 20 first cells found...
**WARN: (PRL-42): Machine aotearoa.ee.ethz.ch is overloaded. The average load (number of active jobs) is 10.83 while the total number of available cores on the machine is 8. This may cause excessive job swapping and slow down your run. Terminate other cpu intensive jobs on this machine if possible. If using LSF with "setMultiCpuUsage -cpuPerHost" option, make sure your LSF setting (in setDistributeHost) reserves the same number of cores per LSF slot as the number specified in cpuPerHost.
**optDesign ... cpu = 0:00:00, real = 0:00:00, mem = 3470.5M **
*** optDesign -preCTS ***
DRC Margin: user margin 0.0; extra margin 0.2
Setup Target Slack: user slack -0.05; extra slack 0.1
Hold Target Slack: user slack 0.0
*info: Setting setup target slack to 0.050
*info: Hold target slack is 0.000
**INFO : Adding temp dont-use cells (LVT only flow version : 2)
Creating information for LVT Only Flow
Num of Buffers : 123
Num of Inverters : 105
Num of VTs : 3
Executing LVT Only Same Size Flow (setting 2)
*Info* Num dontuse cells 311
*Info* Num dontuse cells 2259
moveBlkTerm was implicitly turned on (since useM1).
*** Starting trialRoute (mem=3473.5M) ***
There are 0 pin guide points passed to trialRoute.
Start to check current routing status for nets...
All nets are already routed correctly.
*** Finishing trialRoute (mem=3479.5M) ***
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
Initial Summary
------------------------------------------------------------
+--------------------+---------+
| Setup mode | all |
+--------------------+---------+
| WNS (ns):| -3.053 |
| TNS (ns):| -9890.0 |
| Violating Paths:| 22190 |
| All Paths:| 85005 |
+--------------------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 3 (3) | -0.025 | 18 (18) |
| max_tran | 4 (13) | -0.434 | 17 (26) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 52.640%
------------------------------------------------------------
**optDesign ... cpu = 0:01:58, real = 0:01:01, mem = 3803.1M **
*** Starting optimizing excluded clock nets MEM= 3803.1M) ***
*info: No excluded clock nets to be optimized.
*** Completed optimizing excluded clock nets (CPU Time= 0:00:00.0 MEM= 3803.1M) ***
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
Info: 40 io nets excluded
Info: 18 clock nets excluded from IPO operation.
Netlist preparation processing...
Removed 0 instance
*info: Marking 0 isolation instances dont touch
*info: Marking 0 level shifter instances dont touch
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
Summary (cpu=1.04min real=0.40min mem=3830.4M)
------------------------------------------------------------
+--------------------+---------+
| Setup mode | all |
+--------------------+---------+
| WNS (ns):| -3.053 |
| TNS (ns):| -9890.0 |
| Violating Paths:| 22190 |
| All Paths:| 85005 |
+--------------------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 3 (3) | -0.025 | 18 (18) |
| max_tran | 4 (13) | -0.434 | 17 (26) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 52.640%
Routing Overflow: 0.00% H and 0.10% V
------------------------------------------------------------
**optDesign ... cpu = 0:03:30, real = 0:01:53, mem = 3827.4M **
*Info* Num dontuse cells 311
*Info* Num dontuse cells 1285
*info: Start fixing DRV (Mem = 3862.20M) ...
*info: Options = -maxCap -maxTran -noMaxFanout -noSensitivity -backward -reduceBuffer -maxIter 1
*info: Start fixing DRV iteration 1 ...
*** Starting dpFixDRCViolation (3862.2M)
*info: 40 io nets excluded
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
*info: 18 clock nets excluded
*info: 4 special nets excluded.
*info: 2405 no-driver nets excluded.
*** Starting multi-driver net buffering ***
*summary: 0 non-ignored multi-driver nets.
*** Finished buffering multi-driver nets (CPU=0:00:00.0, MEM=3862.2M) ***
*info: 21 multi-driver nets excluded.
*info: There are 20 candidate Buffer cells
*info: There are 20 candidate Inverter cells
Initializing placement sections/sites ...
Density before buffering = 0.526401
Start fixing design rules ... (0:00:04.8 4009.4M)
Done fixing design rule (0:00:48.7 4014.4M)
Summary:
25 buffers added on 25 nets (with 130 drivers resized)
Density after buffering = 0.526465
default core: bins with density > 0.75 = 6.87 % ( 532 / 7744 )
Starting refinePlace ...
move report: placeLevelShifters moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Spread Effort: high, pre-route mode.
Finished Phase I. CPU Time = 0:00:16.3, Real Time = 0:00:16.0
move report: preRPlace moves 136 insts, mean move: 0.36 um, max move: 1.80 um
max move on inst (top/i_ethz_jh/FE_OFC4245_n20734): (877.40, 1299.00) --> (877.40, 1300.80)
move report: rPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: overall moves 136 insts, mean move: 0.36 um, max move: 1.80 um
max move on inst (top/i_ethz_jh/FE_OFC4245_n20734): (877.40, 1299.00) --> (877.40, 1300.80)
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 1.80 um
inst (top/i_ethz_jh/FE_OFC4245_n20734) with max move: (877.4, 1299) -> (877.4, 1300.8)
mean (X+Y) = 0.36 um
Total instances moved : 136
*** cpu=0:00:17.7 mem=3897.6M mem(used)=0.0M***
Ripped up 0 affected routes.
*** Completed dpFixDRCViolation (0:01:15 3891.4M)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Re-routed 179 nets
Extraction called for design 'shabziger_chip' of instances=294545 and nets=267459 using extraction engine 'preRoute' .
Default RC Extraction called for design shabziger_chip.
RC Extraction called in multi-corner(2) mode.
RCMode: Default
RC Corner Indexes 0 1
Capacitance Scaling Factor : 1.00000 1.00000
Resistance Scaling Factor : 1.00000 1.00000
Clock Cap. Scaling Factor : 1.00000 1.00000
Clock Res. Scaling Factor : 1.00000 1.00000
Shrink Factor : 1.00000
Default RC extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Default RC Extraction DONE (CPU Time: 0:00:01.7 Real Time: 0:00:02.0 MEM: 3891.398M)
Using new Cte TW Api base...#################################################################################
# Design Stage: PreRoute
# Design Mode: 65nm
# Analysis Mode: MMMC non-OCV
# Extraction Mode: default
# Delay Calculation Options: engine=signalStorm signOff=true SIAware=false(opt)
# Switching Delay Calculation Engine to signalStorm
#################################################################################
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.5, MEM = 3257.2M, InitMEM = 3257.2M)
Start delay calculation using Signal Storm (mem=3257.234M)...
Delay calculation completed. (cpu=0:00:52.6 real=0:00:53.0 mem=3555.555M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3555.6M, InitMEM = 3555.6M)
Start delay calculation using Signal Storm (mem=3555.555M)...
Delay calculation completed. (cpu=0:00:28.2 real=0:00:28.0 mem=3555.555M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3555.6M, InitMEM = 3555.6M)
Start delay calculation using Signal Storm (mem=3555.555M)...
Delay calculation completed. (cpu=0:00:27.2 real=0:00:27.0 mem=3555.555M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3555.6M, InitMEM = 3555.6M)
Start delay calculation using Signal Storm (mem=3555.555M)...
Delay calculation completed. (cpu=0:00:28.5 real=0:00:29.0 mem=3555.555M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3555.6M, InitMEM = 3555.6M)
Start delay calculation using Signal Storm (mem=3555.555M)...
Delay calculation completed. (cpu=0:00:27.0 real=0:00:27.0 mem=3555.555M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.2, MEM = 3555.6M, InitMEM = 3555.6M)
Start delay calculation using Signal Storm (mem=3555.555M)...
Delay calculation completed. (cpu=0:00:28.1 real=0:00:28.0 mem=3555.555M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3555.6M, InitMEM = 3555.6M)
Start delay calculation using Signal Storm (mem=3555.555M)...
Delay calculation completed. (cpu=0:00:27.2 real=0:00:27.0 mem=3555.555M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3555.6M, InitMEM = 3555.6M)
Start delay calculation using Signal Storm (mem=3555.555M)...
Delay calculation completed. (cpu=0:00:28.3 real=0:00:29.0 mem=3555.555M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3555.6M, InitMEM = 3555.6M)
Start delay calculation using Signal Storm (mem=3555.555M)...
Delay calculation completed. (cpu=0:00:28.2 real=0:00:28.0 mem=3555.555M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3555.6M, InitMEM = 3555.6M)
Start delay calculation using Signal Storm (mem=3555.555M)...
Delay calculation completed. (cpu=0:00:28.4 real=0:00:28.0 mem=3555.555M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 3555.6M, InitMEM = 3555.6M)
Start delay calculation using Signal Storm (mem=3555.555M)...
Delay calculation completed. (cpu=0:00:27.6 real=0:00:28.0 mem=3555.555M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3555.6M, InitMEM = 3555.6M)
Start delay calculation using Signal Storm (mem=3555.555M)...
Delay calculation completed. (cpu=0:00:27.7 real=0:00:27.0 mem=3555.555M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3555.6M, InitMEM = 3555.6M)
Start delay calculation using Signal Storm (mem=3555.555M)...
Delay calculation completed. (cpu=0:00:28.6 real=0:00:29.0 mem=3555.555M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3555.6M, InitMEM = 3555.6M)
Start delay calculation using Signal Storm (mem=3555.555M)...
Delay calculation completed. (cpu=0:00:27.3 real=0:00:27.0 mem=3555.555M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3555.6M, InitMEM = 3555.6M)
Start delay calculation using Signal Storm (mem=3555.555M)...
Delay calculation completed. (cpu=0:00:26.9 real=0:00:27.0 mem=3555.555M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3555.6M, InitMEM = 3555.6M)
Start delay calculation using Signal Storm (mem=3555.555M)...
Delay calculation completed. (cpu=0:00:27.0 real=0:00:27.0 mem=3555.555M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.2, MEM = 3555.6M, InitMEM = 3555.6M)
Start delay calculation using Signal Storm (mem=3555.555M)...
Delay calculation completed. (cpu=0:00:39.7 real=0:00:40.0 mem=3555.555M 0)
*** CDM Built up (cpu=0:09:33 real=0:09:33 mem= 3555.6M) ***
*info: DRV Fixing Iteration 1.
*info: Remaining violations:
*info: Max cap violations: 0
*info: Max tran violations: 3
*info: Prev Max cap violations: 3
*info: Prev Max tran violations: 13
*info:
*info: Completed fixing DRV (CPU Time = 0:12:57, Mem = 3878.77M).
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
Summary (cpu=12.95min real=12.00min mem=3878.8M)
------------------------------------------------------------
+--------------------+---------+
| Setup mode | all |
+--------------------+---------+
| WNS (ns):| -3.053 |
| TNS (ns):| -9790.9 |
| Violating Paths:| 22154 |
| All Paths:| 85005 |
+--------------------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 15 (15) |
| max_tran | 1 (3) | -0.009 | 14 (16) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 52.647%
Routing Overflow: 0.00% H and 0.10% V
------------------------------------------------------------
**optDesign ... cpu = 0:17:31, real = 0:14:44, mem = 3878.8M **
*Info* Num dontuse cells 311
*Info* Num dontuse cells 2227
*** Starting optFanout (3878.8M)
*info: 40 io nets excluded
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
*info: 18 clock nets excluded
*info: 4 special nets excluded.
*info: 2405 no-driver nets excluded.
*** Starting multi-driver net buffering ***
*summary: 0 non-ignored multi-driver nets.
*** Finished buffering multi-driver nets (CPU=0:00:00.0, MEM=3878.8M) ***
*info: 21 multi-driver nets excluded.
Start fixing timing ... (0:00:04.9 3952.4M)
*info: Buffered 0 large fanout net (> 100 terms)
Done fixing timing (0:09:16 4142.1M)
Summary:
12248 buffers added on 9305 nets (with 7105 drivers resized)
1017 nets rebuffered with 1091 inst removed and 1877 inst added
Density after buffering = 0.583799
default core: bins with density > 0.75 = 16.3 % ( 1266 / 7744 )
RPlace IncrNP: Rollback Lev = -3
RPlace: Density =1.923333, incremental np is triggered.
Checking spec file integrity...
Clock gating cells determined by native netlist tracing.
default core: bins with density > 0.75 = 18.8 % ( 1452 / 7744 )
RPlace postIncrNP: Density = 1.923333 -> 1.026667.
*** cpu time = 0:00:24.4.
move report: incrNP moves 37994 insts, mean move: 3.42 um, max move: 39.60 um
max move on inst (top/i_gmu_keccak/FE_OFC11958_net1549618): (1410.40, 901.20) --> (1426.60, 924.60)
Starting refinePlace ...
move report: placeLevelShifters moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Spread Effort: high, pre-route mode.
Finished Phase I. CPU Time = 0:00:24.4, Real Time = 0:00:25.0
move report: preRPlace moves 48848 insts, mean move: 0.98 um, max move: 7.40 um
max move on inst (top/i_gmu_keccak/datapath_gen_rd/FE_OFC10489_n4212): (1340.20, 1147.80) --> (1347.60, 1147.80)
move report: rPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: overall moves 48848 insts, mean move: 0.98 um, max move: 7.40 um
max move on inst (top/i_gmu_keccak/datapath_gen_rd/FE_OFC10489_n4212): (1340.20, 1147.80) --> (1347.60, 1147.80)
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 39.80 um
inst (top/i_gmu_keccak/FE_OFC11958_net1549618) with max move: (1410.4, 901.2) -> (1426.8, 924.6)
mean (X+Y) = 2.30 um
Total instances flipped for legalization: 517
Total instances moved : 73970
*** cpu=0:00:25.9 mem=4066.4M mem(used)=0.0M***
Ripped up 3939 affected routes.
*** Completed optFanout (0:10:16 4066.4M)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Re-routed 4058 nets
Extraction called for design 'shabziger_chip' of instances=305702 and nets=278616 using extraction engine 'preRoute' .
Default RC Extraction called for design shabziger_chip.
RC Extraction called in multi-corner(2) mode.
RCMode: Default
RC Corner Indexes 0 1
Capacitance Scaling Factor : 1.00000 1.00000
Resistance Scaling Factor : 1.00000 1.00000
Clock Cap. Scaling Factor : 1.00000 1.00000
Clock Res. Scaling Factor : 1.00000 1.00000
Shrink Factor : 1.00000
Default RC extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Default RC Extraction DONE (CPU Time: 0:00:02.0 Real Time: 0:00:02.0 MEM: 4066.418M)
Using new Cte TW Api base...#################################################################################
# Design Stage: PreRoute
# Design Mode: 65nm
# Analysis Mode: MMMC non-OCV
# Extraction Mode: default
# Delay Calculation Options: engine=signalStorm signOff=true SIAware=false(opt)
# Switching Delay Calculation Engine to signalStorm
#################################################################################
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.4, MEM = 3285.2M, InitMEM = 3285.2M)
Start delay calculation using Signal Storm (mem=3285.176M)...
Delay calculation completed. (cpu=0:00:50.7 real=0:00:51.0 mem=3587.758M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3587.8M, InitMEM = 3587.8M)
Start delay calculation using Signal Storm (mem=3587.758M)...
Delay calculation completed. (cpu=0:00:26.3 real=0:00:26.0 mem=3587.758M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3587.8M, InitMEM = 3587.8M)
Start delay calculation using Signal Storm (mem=3587.758M)...
Delay calculation completed. (cpu=0:00:25.5 real=0:00:25.0 mem=3587.758M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 3587.8M, InitMEM = 3587.8M)
Start delay calculation using Signal Storm (mem=3587.758M)...
Delay calculation completed. (cpu=0:00:27.2 real=0:00:28.0 mem=3587.758M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 3587.8M, InitMEM = 3587.8M)
Start delay calculation using Signal Storm (mem=3587.758M)...
Delay calculation completed. (cpu=0:00:25.3 real=0:00:25.0 mem=3587.758M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3587.8M, InitMEM = 3587.8M)
Start delay calculation using Signal Storm (mem=3587.758M)...
Delay calculation completed. (cpu=0:00:26.3 real=0:00:26.0 mem=3587.758M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 3587.8M, InitMEM = 3587.8M)
Start delay calculation using Signal Storm (mem=3587.758M)...
Delay calculation completed. (cpu=0:00:26.1 real=0:00:26.0 mem=3587.758M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.1, MEM = 3587.8M, InitMEM = 3587.8M)
Start delay calculation using Signal Storm (mem=3587.758M)...
Delay calculation completed. (cpu=0:00:26.7 real=0:00:26.0 mem=3587.758M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 3587.8M, InitMEM = 3587.8M)
Start delay calculation using Signal Storm (mem=3587.758M)...
Delay calculation completed. (cpu=0:00:27.4 real=0:00:28.0 mem=3587.758M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3587.8M, InitMEM = 3587.8M)
Start delay calculation using Signal Storm (mem=3587.758M)...
Delay calculation completed. (cpu=0:00:26.5 real=0:00:26.0 mem=3587.758M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 3587.8M, InitMEM = 3587.8M)
Start delay calculation using Signal Storm (mem=3587.758M)...
Delay calculation completed. (cpu=0:00:27.5 real=0:00:28.0 mem=3587.758M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 3587.8M, InitMEM = 3587.8M)
Start delay calculation using Signal Storm (mem=3587.758M)...
Delay calculation completed. (cpu=0:00:26.3 real=0:00:26.0 mem=3587.758M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3587.8M, InitMEM = 3587.8M)
Start delay calculation using Signal Storm (mem=3587.758M)...
Delay calculation completed. (cpu=0:00:28.3 real=0:00:29.0 mem=3587.758M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 3587.8M, InitMEM = 3587.8M)
Start delay calculation using Signal Storm (mem=3587.758M)...
Delay calculation completed. (cpu=0:00:25.5 real=0:00:25.0 mem=3587.758M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.1, MEM = 3587.8M, InitMEM = 3587.8M)
Start delay calculation using Signal Storm (mem=3587.758M)...
Delay calculation completed. (cpu=0:00:27.6 real=0:00:28.0 mem=3587.758M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 3587.8M, InitMEM = 3587.8M)
Start delay calculation using Signal Storm (mem=3587.758M)...
Delay calculation completed. (cpu=0:00:25.7 real=0:00:26.0 mem=3587.758M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 3587.8M, InitMEM = 3587.8M)
Start delay calculation using Signal Storm (mem=3587.758M)...
Delay calculation completed. (cpu=0:00:37.5 real=0:00:37.0 mem=3587.758M 0)
*** CDM Built up (cpu=0:09:12 real=0:09:12 mem= 3587.8M) ***
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
Summary (cpu=20.86min real=17.18min mem=3918.8M)
------------------------------------------------------------
+--------------------+---------+
| Setup mode | all |
+--------------------+---------+
| WNS (ns):| -2.059 |
| TNS (ns):| -2212.3 |
| Violating Paths:| 9006 |
| All Paths:| 85005 |
+--------------------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 6 (6) | -0.021 | 21 (21) |
| max_tran | 5 (293) | -0.166 | 18 (306) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 58.380%
Routing Overflow: 0.00% H and 0.10% V
------------------------------------------------------------
**optDesign ... cpu = 0:39:11, real = 0:32:26, mem = 3918.8M **
*** Timing NOT met, worst failing slack is -2.059
*** Check timing (0:00:00.6)
*Info* Num dontuse cells 311
*Info* Num dontuse cells 1285
************ Started Recovering Area and Global Resizing for Timing Improvement ***************
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
Info: 40 io nets excluded
Info: 18 clock nets excluded from IPO operation.
** Density before transform = 58.380% **
*** starting 1-st resizing pass: 28182 instances
*** starting 2-nd resizing pass: 27049 instances
*** starting 3-rd resizing pass: 19618 instances
*** starting 4-th resizing pass: 9178 instances
*** starting 5-th resizing pass: 1975 instances
*** starting 6-th resizing pass: 464 instances
*** starting 7-th resizing pass: 11 instances
** Summary: Buffer Deletion = 384 Declone = 749 Downsize = 8119 Upsize = 3079 **
** Density Change = 1.854% **
** Density after transform = 56.526% **
*** Finish transform (0:07:56) ***
*** Starting sequential cell resizing ***
density before resizing = 56.526%
*summary: 3489 instances changed cell type
density after resizing = 56.650%
*** Finish sequential cell resizing (cpu=0:01:04 mem=3934.6M) ***
density before resizing = 56.650%
* summary of transition time violation fixes:
*summary: 511 instances changed cell type
density after resizing = 56.666%
************ Finished Recovering Area and Global Resizing for Timing Improvement ***************
default core: bins with density > 0.75 = 14.6 % ( 1128 / 7744 )
Starting refinePlace ...
move report: placeLevelShifters moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Spread Effort: high, pre-route mode.
Finished Phase I. CPU Time = 0:00:16.7, Real Time = 0:00:17.0
move report: preRPlace moves 6425 insts, mean move: 0.60 um, max move: 5.00 um
max move on inst (top/i_gmu_skein/datapathInst/keygen_gen/key_reg_gen_6_output_reg_18_): (1103.00, 1493.40) --> (1104.40, 1497.00)
move report: rPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: overall moves 6425 insts, mean move: 0.60 um, max move: 5.00 um
max move on inst (top/i_gmu_skein/datapathInst/keygen_gen/key_reg_gen_6_output_reg_18_): (1103.00, 1493.40) --> (1104.40, 1497.00)
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 5.00 um
inst (top/i_gmu_skein/datapathInst/keygen_gen/key_reg_gen_6_output_reg_18_) with max move: (1103, 1493.4) -> (1104.4, 1497)
mean (X+Y) = 0.60 um
Total instances moved : 6425
*** cpu=0:00:18.3 mem=3679.5M mem(used)=0.0M***
Ripped up 0 affected routes.
moveBlkTerm was implicitly turned on (since useM1).
*** Starting trialRoute (mem=3763.8M) ***
There are 0 pin guide points passed to trialRoute.
moveBlkTerm was implicitly turned on (since useM1).
Options: -moveBlkTerm -useM1 -handlePreroute -keepMarkedOptRoutes -noPinGuide
Nr of prerouted/Fixed nets = 40
Num blk terms moved = 959626.
routingBox: (100 200) (1874900 1874800)
coreBox: (148800 148800) (1726200 1726200)
Number of multi-gpin terms=0, multi-gpins=0, moved blk term=192/163279
Phase 1a route (0:00:03.1 3907.1M):
Est net length = 1.540e+07um = 7.272e+06H + 8.128e+06V
Usage: (25.9%H 29.7%V) = (7.671e+06um 7.959e+06um) = (7665921 4421566)
Obstruct: 784127 = 288147 (16.7%H) + 495980 (28.8%V)
Overflow: 11687 = 3401 (0.24% H) + 8286 (0.68% V)
Number obstruct path=51193 reroute=0
Phase 1b route (0:00:04.3 3917.2M):
Usage: (26.3%H 30.0%V) = (7.779e+06um 8.033e+06um) = (7773714 4462693)
Overflow: 30032 = 2172 (0.15% H) + 27860 (2.27% V)
Phase 1c route (0:00:02.4 3917.2M):
Usage: (26.3%H 30.0%V) = (7.769e+06um 8.036e+06um) = (7763881 4464626)
Overflow: 25276 = 1937 (0.14% H) + 23339 (1.90% V)
Phase 1d route (0:00:02.3 3917.2M):
Usage: (26.3%H 30.0%V) = (7.770e+06um 8.039e+06um) = (7764776 4465969)
Overflow: 15923 = 438 (0.03% H) + 15485 (1.26% V)
Phase 1e route (0:00:01.6 3982.5M):
Usage: (26.3%H 30.0%V) = (7.777e+06um 8.041e+06um) = (7771381 4467515)
Overflow: 235 = 8 (0.00% H) + 227 (0.02% V)
Phase 1f route (0:00:01.5 3982.5M):
Usage: (26.3%H 30.0%V) = (7.777e+06um 8.042e+06um) = (7771249 4467529)
Overflow: 34 = 2 (0.00% H) + 32 (0.00% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-1: 2 0.00% 32 0.00%
--------------------------------------
0: 251 0.02% 4027 0.33%
1: 874 0.06% 11906 0.97%
2: 2390 0.17% 18204 1.48%
3: 7010 0.49% 33387 2.72%
4: 9803 0.68% 61382 5.00%
5: 13946 0.97% 284397 23.19%
6: 22146 1.54% 130126 10.61%
7: 26042 1.82% 86738 7.07%
8: 36058 2.51% 79770 6.50%
9: 52895 3.69% 73350 5.98%
10: 57434 4.00% 80426 6.56%
11: 70403 4.91% 57845 4.72%
12: 166172 11.58% 49491 4.03%
13: 206520 14.40% 35632 2.90%
14: 121880 8.50% 30455 2.48%
15: 79953 5.57% 140741 11.47%
16: 76680 5.35% 37863 3.09%
17: 70516 4.92% 539 0.04%
18: 64537 4.50% 5949 0.48%
19: 52845 3.68% 41 0.00%
20: 296096 20.64% 4319 0.35%
Global route (cpu=15.3s real=16.0s 3913.1M)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Phase 1l route (0:00:15.3 3838.3M):
*** After '-updateRemainTrks' operation:
Usage: (27.0%H 31.6%V) = (7.999e+06um 8.470e+06um) = (7993346 4705354)
Overflow: 1628 = 58 (0.00% H) + 1570 (0.13% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-4: 0 0.00% 1 0.00%
-3: 0 0.00% 23 0.00%
-2: 5 0.00% 192 0.02%
-1: 51 0.00% 1257 0.10%
--------------------------------------
0: 348 0.02% 6776 0.55%
1: 1167 0.08% 17243 1.41%
2: 2888 0.20% 26357 2.15%
3: 7948 0.55% 43654 3.56%
4: 11225 0.78% 65967 5.38%
5: 16035 1.12% 284557 23.20%
6: 25066 1.75% 126454 10.31%
7: 29547 2.06% 82186 6.70%
8: 39165 2.73% 74817 6.10%
9: 55632 3.88% 68542 5.59%
10: 59422 4.14% 76114 6.21%
11: 71493 4.98% 54248 4.42%
12: 166182 11.59% 46507 3.79%
13: 205367 14.32% 33547 2.73%
14: 120722 8.42% 29137 2.38%
15: 77395 5.40% 140375 11.44%
16: 73856 5.15% 37865 3.09%
17: 67446 4.70% 535 0.04%
18: 61866 4.31% 5908 0.48%
19: 50510 3.52% 41 0.00%
20: 291117 20.29% 4317 0.35%
Num blk terms moved back = 951542
*** Completed Phase 1 route (0:00:35.2 3871.4M) ***
Total length: 1.582e+07um, number of vias: 2473088
M1(H) length: 1.166e+04um, number of vias: 960522
M2(V) length: 2.674e+06um, number of vias: 947411
M3(H) length: 3.810e+06um, number of vias: 329191
M4(V) length: 3.050e+06um, number of vias: 153958
M5(H) length: 3.201e+06um, number of vias: 73813
M6(V) length: 2.730e+06um, number of vias: 7572
M7(H) length: 3.386e+05um, number of vias: 621
M8(V) length: 7.288e+03um
*** Completed Phase 2 route (0:00:40.7 3940.5M) ***
*** Finished all Phases (cpu=0:01:18 mem=3940.5M) ***
Peak Memory Usage was 3925.2M
*** Finished trialRoute (cpu=0:01:20 mem=3940.5M) ***
Extraction called for design 'shabziger_chip' of instances=304569 and nets=277483 using extraction engine 'preRoute' .
Default RC Extraction called for design shabziger_chip.
RC Extraction called in multi-corner(2) mode.
RCMode: Default
RC Corner Indexes 0 1
Capacitance Scaling Factor : 1.00000 1.00000
Resistance Scaling Factor : 1.00000 1.00000
Clock Cap. Scaling Factor : 1.00000 1.00000
Clock Res. Scaling Factor : 1.00000 1.00000
Shrink Factor : 1.00000
Default RC extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Default RC Extraction DONE (CPU Time: 0:00:01.4 Real Time: 0:00:01.0 MEM: 3940.512M)
Using new Cte TW Api base...#################################################################################
# Design Stage: PreRoute
# Design Mode: 65nm
# Analysis Mode: MMMC non-OCV
# Extraction Mode: default
# Delay Calculation Options: engine=signalStorm signOff=true SIAware=false(opt)
# Switching Delay Calculation Engine to signalStorm
#################################################################################
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.6, MEM = 3324.2M, InitMEM = 3324.2M)
Start delay calculation using Signal Storm (mem=3324.234M)...
Delay calculation completed. (cpu=0:00:52.1 real=0:00:52.0 mem=3622.668M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 3622.7M, InitMEM = 3622.7M)
Start delay calculation using Signal Storm (mem=3622.668M)...
Delay calculation completed. (cpu=0:00:25.5 real=0:00:25.0 mem=3622.668M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3622.7M, InitMEM = 3622.7M)
Start delay calculation using Signal Storm (mem=3622.668M)...
Delay calculation completed. (cpu=0:00:26.4 real=0:00:27.0 mem=3622.668M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3622.7M, InitMEM = 3622.7M)
Start delay calculation using Signal Storm (mem=3622.668M)...
Delay calculation completed. (cpu=0:00:25.5 real=0:00:25.0 mem=3622.668M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 3622.7M, InitMEM = 3622.7M)
Start delay calculation using Signal Storm (mem=3622.668M)...
Delay calculation completed. (cpu=0:00:27.2 real=0:00:27.0 mem=3622.668M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3622.7M, InitMEM = 3622.7M)
Start delay calculation using Signal Storm (mem=3622.668M)...
Delay calculation completed. (cpu=0:00:25.2 real=0:00:26.0 mem=3622.668M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 3622.7M, InitMEM = 3622.7M)
Start delay calculation using Signal Storm (mem=3622.668M)...
Delay calculation completed. (cpu=0:00:27.2 real=0:00:27.0 mem=3622.668M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3622.7M, InitMEM = 3622.7M)
Start delay calculation using Signal Storm (mem=3622.668M)...
Delay calculation completed. (cpu=0:00:25.4 real=0:00:25.0 mem=3622.668M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3622.7M, InitMEM = 3622.7M)
Start delay calculation using Signal Storm (mem=3622.668M)...
Delay calculation completed. (cpu=0:00:31.3 real=0:00:32.0 mem=3622.668M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.1, MEM = 3622.7M, InitMEM = 3622.7M)
Start delay calculation using Signal Storm (mem=3622.668M)...
Delay calculation completed. (cpu=0:00:31.1 real=0:00:31.0 mem=3622.668M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.5, MEM = 3622.7M, InitMEM = 3622.7M)
Start delay calculation using Signal Storm (mem=3622.668M)...
Delay calculation completed. (cpu=0:00:36.3 real=0:00:36.0 mem=3622.668M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.2, MEM = 3622.7M, InitMEM = 3622.7M)
Start delay calculation using Signal Storm (mem=3622.668M)...
Delay calculation completed. (cpu=0:00:34.3 real=0:00:34.0 mem=3622.668M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 3622.7M, InitMEM = 3622.7M)
Start delay calculation using Signal Storm (mem=3622.668M)...
Delay calculation completed. (cpu=0:00:28.3 real=0:00:29.0 mem=3622.668M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.1, MEM = 3622.7M, InitMEM = 3622.7M)
Start delay calculation using Signal Storm (mem=3622.668M)...
Delay calculation completed. (cpu=0:00:25.3 real=0:00:25.0 mem=3622.668M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.4, MEM = 3622.7M, InitMEM = 3622.7M)
Start delay calculation using Signal Storm (mem=3622.668M)...
Delay calculation completed. (cpu=0:00:27.3 real=0:00:27.0 mem=3622.668M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3622.7M, InitMEM = 3622.7M)
Start delay calculation using Signal Storm (mem=3622.668M)...
Delay calculation completed. (cpu=0:00:25.5 real=0:00:25.0 mem=3622.668M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.1, MEM = 3622.7M, InitMEM = 3622.7M)
Start delay calculation using Signal Storm (mem=3622.668M)...
Delay calculation completed. (cpu=0:00:37.4 real=0:00:37.0 mem=3622.668M 0)
*** CDM Built up (cpu=0:08:56 real=0:08:56 mem= 3622.7M) ***
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
Summary (cpu=24.54min real=19.67min mem=3952.6M)
------------------------------------------------------------
+--------------------+---------+
| Setup mode | all |
+--------------------+---------+
| WNS (ns):| -2.144 |
| TNS (ns):| -2007.4 |
| Violating Paths:| 8440 |
| All Paths:| 85005 |
+--------------------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 31 (31) | -0.124 | 46 (46) |
| max_tran | 32 (364) | -1.338 | 45 (377) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 56.666%
Routing Overflow: 0.00% H and 0.13% V
------------------------------------------------------------
**optDesign ... cpu = 1:04:35, real = 0:52:37, mem = 3952.6M **
*Info* Num dontuse cells 311
*Info* Num dontuse cells 1285
*info: Start fixing DRV (Mem = 3952.61M) ...
*info: Options = -maxCap -maxTran -noMaxFanout -noSensitivity -backward -reduceBuffer -secondPreCtsDrv -maxIter 1
*info: Start fixing DRV iteration 1 ...
*** Starting dpFixDRCViolation (3952.6M)
*info: 40 io nets excluded
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
*info: 18 clock nets excluded
*info: 4 special nets excluded.
*info: 2405 no-driver nets excluded.
*** Starting multi-driver net buffering ***
*summary: 0 non-ignored multi-driver nets.
*** Finished buffering multi-driver nets (CPU=0:00:00.0, MEM=3952.6M) ***
*info: 21 multi-driver nets excluded.
Start fixing design rules ... (0:00:04.9 4124.8M)
Done fixing design rule (0:00:44.7 4126.8M)
Summary:
68 buffers added on 68 nets (with 162 drivers resized)
Density after buffering = 0.566782
default core: bins with density > 0.75 = 14.6 % ( 1133 / 7744 )
Starting refinePlace ...
move report: placeLevelShifters moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Spread Effort: high, pre-route mode.
Finished Phase I. CPU Time = 0:00:18.5, Real Time = 0:00:18.0
move report: preRPlace moves 214 insts, mean move: 0.46 um, max move: 2.80 um
max move on inst (top/FE_OFC16541_MsgLenxD_60_): (1128.40, 1131.60) --> (1127.40, 1133.40)
move report: rPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: overall moves 214 insts, mean move: 0.46 um, max move: 2.80 um
max move on inst (top/FE_OFC16541_MsgLenxD_60_): (1128.40, 1131.60) --> (1127.40, 1133.40)
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 2.80 um
inst (top/FE_OFC16541_MsgLenxD_60_) with max move: (1128.4, 1131.6) -> (1127.4, 1133.4)
mean (X+Y) = 0.46 um
Total instances moved : 214
*** cpu=0:00:20.0 mem=4025.0M mem(used)=64.0M***
Ripped up 0 affected routes.
*** Completed dpFixDRCViolation (0:01:13 3954.6M)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Re-routed 298 nets
Extraction called for design 'shabziger_chip' of instances=304637 and nets=277551 using extraction engine 'preRoute' .
Default RC Extraction called for design shabziger_chip.
RC Extraction called in multi-corner(2) mode.
RCMode: Default
RC Corner Indexes 0 1
Capacitance Scaling Factor : 1.00000 1.00000
Resistance Scaling Factor : 1.00000 1.00000
Clock Cap. Scaling Factor : 1.00000 1.00000
Clock Res. Scaling Factor : 1.00000 1.00000
Shrink Factor : 1.00000
Default RC extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Default RC Extraction DONE (CPU Time: 0:00:01.4 Real Time: 0:00:02.0 MEM: 3954.621M)
Using new Cte TW Api base...#################################################################################
# Design Stage: PreRoute
# Design Mode: 65nm
# Analysis Mode: MMMC non-OCV
# Extraction Mode: default
# Delay Calculation Options: engine=signalStorm signOff=true SIAware=false(opt)
# Switching Delay Calculation Engine to signalStorm
#################################################################################
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.4, MEM = 3322.1M, InitMEM = 3322.1M)
Start delay calculation using Signal Storm (mem=3322.094M)...
Delay calculation completed. (cpu=0:00:49.3 real=0:00:49.0 mem=3624.676M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.2, MEM = 3624.7M, InitMEM = 3624.7M)
Start delay calculation using Signal Storm (mem=3624.676M)...
Delay calculation completed. (cpu=0:00:24.4 real=0:00:25.0 mem=3624.676M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3624.7M, InitMEM = 3624.7M)
Start delay calculation using Signal Storm (mem=3624.676M)...
Delay calculation completed. (cpu=0:00:25.2 real=0:00:25.0 mem=3624.676M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3624.7M, InitMEM = 3624.7M)
Start delay calculation using Signal Storm (mem=3624.676M)...
Delay calculation completed. (cpu=0:00:25.4 real=0:00:25.0 mem=3624.676M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 3624.7M, InitMEM = 3624.7M)
Start delay calculation using Signal Storm (mem=3624.676M)...
Delay calculation completed. (cpu=0:00:32.1 real=0:00:32.0 mem=3624.676M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.2, MEM = 3624.7M, InitMEM = 3624.7M)
Start delay calculation using Signal Storm (mem=3624.676M)...
Delay calculation completed. (cpu=0:00:31.6 real=0:00:32.0 mem=3624.676M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.2, MEM = 3624.7M, InitMEM = 3624.7M)
Start delay calculation using Signal Storm (mem=3624.676M)...
**WARN: (PRL-42): Machine aotearoa.ee.ethz.ch is overloaded. The average load (number of active jobs) is 11.90 while the total number of available cores on the machine is 8. This may cause excessive job swapping and slow down your run. Terminate other cpu intensive jobs on this machine if possible. If using LSF with "setMultiCpuUsage -cpuPerHost" option, make sure your LSF setting (in setDistributeHost) reserves the same number of cores per LSF slot as the number specified in cpuPerHost.
Delay calculation completed. (cpu=0:00:34.2 real=0:00:34.0 mem=3624.676M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.5, MEM = 3624.7M, InitMEM = 3624.7M)
Start delay calculation using Signal Storm (mem=3624.676M)...
Delay calculation completed. (cpu=0:00:34.3 real=0:00:34.0 mem=3624.676M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.3, MEM = 3624.7M, InitMEM = 3624.7M)
Start delay calculation using Signal Storm (mem=3624.676M)...
Delay calculation completed. (cpu=0:00:33.9 real=0:00:34.0 mem=3624.676M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.2, MEM = 3624.7M, InitMEM = 3624.7M)
Start delay calculation using Signal Storm (mem=3624.676M)...
Delay calculation completed. (cpu=0:00:31.2 real=0:00:31.0 mem=3624.676M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.2, MEM = 3624.7M, InitMEM = 3624.7M)
Start delay calculation using Signal Storm (mem=3624.676M)...
Delay calculation completed. (cpu=0:00:30.7 real=0:00:31.0 mem=3624.676M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.1, MEM = 3624.7M, InitMEM = 3624.7M)
Start delay calculation using Signal Storm (mem=3624.676M)...
Delay calculation completed. (cpu=0:00:31.0 real=0:00:31.0 mem=3624.676M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.2, MEM = 3624.7M, InitMEM = 3624.7M)
Start delay calculation using Signal Storm (mem=3624.676M)...
Delay calculation completed. (cpu=0:00:34.5 real=0:00:34.0 mem=3624.676M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.4, MEM = 3624.7M, InitMEM = 3624.7M)
Start delay calculation using Signal Storm (mem=3624.676M)...
Delay calculation completed. (cpu=0:00:31.9 real=0:00:32.0 mem=3624.676M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.2, MEM = 3624.7M, InitMEM = 3624.7M)
Start delay calculation using Signal Storm (mem=3624.676M)...
Delay calculation completed. (cpu=0:00:32.2 real=0:00:32.0 mem=3624.676M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.2, MEM = 3624.7M, InitMEM = 3624.7M)
Start delay calculation using Signal Storm (mem=3624.676M)...
Delay calculation completed. (cpu=0:00:33.8 real=0:00:34.0 mem=3624.676M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.3, MEM = 3624.7M, InitMEM = 3624.7M)
Start delay calculation using Signal Storm (mem=3624.676M)...
Delay calculation completed. (cpu=0:00:43.4 real=0:00:44.0 mem=3624.676M 0)
*** CDM Built up (cpu=0:10:27 real=0:10:27 mem= 3624.7M) ***
*info: DRV Fixing Iteration 1.
*info: Remaining violations:
*info: Max cap violations: 0
*info: Max tran violations: 0
*info: Prev Max cap violations: 31
*info: Prev Max tran violations: 364
*info:
*info: Completed fixing DRV (CPU Time = 0:13:49, Mem = 3954.50M).
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
Summary (cpu=13.82min real=12.85min mem=3954.5M)
------------------------------------------------------------
+--------------------+---------+
| Setup mode | all |
+--------------------+---------+
| WNS (ns):| -2.144 |
| TNS (ns):| -2000.0 |
| Violating Paths:| 8411 |
| All Paths:| 85005 |
+--------------------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 15 (15) |
| max_tran | 0 (0) | 0.000 | 13 (13) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 56.678%
Routing Overflow: 0.00% H and 0.13% V
------------------------------------------------------------
**optDesign ... cpu = 1:19:27, real = 1:06:16, mem = 3954.5M **
*** Timing NOT met, worst failing slack is -2.144
*** Check timing (0:00:00.4)
*Info* Num dontuse cells 311
*Info* Num dontuse cells 2259
Started binary server on port 35722
*** Starting optCritPath ***
*info: 40 io nets excluded
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
*info: 18 clock nets excluded
*info: 4 special nets excluded.
*info: 21 multi-driver nets excluded.
*info: 2405 no-driver nets excluded.
Density : 0.5668
Max route overflow : 0.0013
Current slack : -2.144 ns, density : 0.5668 End_Point: top/i_gmu_skein/datapathInst/r_reg_239_/D
Current slack : -2.126 ns, density : 0.5668 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_239_/D
Current slack : -2.126 ns, density : 0.5668 End_Point: top/i_gmu_skein/datapathInst/r_reg_239_/D
Current slack : -2.118 ns, density : 0.5668 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_239_/D
Current slack : -1.840 ns, density : 0.5668 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_383_/D
Current slack : -1.839 ns, density : 0.5668 End_Point: top/i_gmu_skein/datapathInst/r_reg_319_/D
Current slack : -1.839 ns, density : 0.5668 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_319_/D
Current slack : -1.839 ns, density : 0.5668 End_Point: top/i_gmu_skein/datapathInst/r_reg_319_/D
Current slack : -1.824 ns, density : 0.5668 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_319_/D
Current slack : -1.730 ns, density : 0.5668 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_255_/D
Current slack : -1.724 ns, density : 0.5668 End_Point: top/i_gmu_skein/datapathInst/r_reg_255_/D
Current slack : -1.724 ns, density : 0.5668 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_255_/D
Current slack : -1.724 ns, density : 0.5668 End_Point: top/i_gmu_skein/datapathInst/r_reg_255_/D
Current slack : -1.724 ns, density : 0.5668 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_255_/D
Current slack : -1.682 ns, density : 0.5668 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_254_/D
Current slack : -1.682 ns, density : 0.5668 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_254_/D
Current slack : -1.682 ns, density : 0.5668 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_254_/D
Current slack : -1.682 ns, density : 0.5668 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_254_/D
Current slack : -1.682 ns, density : 0.5668 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_254_/D
Current slack : -1.682 ns, density : 0.5668 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_254_/D
Current slack : -1.682 ns, density : 0.5668 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_254_/D
Current slack : -1.682 ns, density : 0.5668 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_254_/D
Current slack : -1.638 ns, density : 0.5668 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_383_/D
Current slack : -1.638 ns, density : 0.5668 End_Point: top/i_gmu_skein/datapathInst/r_reg_383_/D
Current slack : -1.638 ns, density : 0.5667 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_383_/D
Current slack : -0.860 ns, density : 0.5684 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_127_/D
Current slack : -0.676 ns, density : 0.5704 End_Point: top/i_gmu_skein/datapathInst/r_reg_127_/D
Current slack : -0.645 ns, density : 0.5705 End_Point: top/i_gmu_skein/datapathInst/r_reg_382_/D
Current slack : -0.632 ns, density : 0.5705 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_127_/D
Current slack : -0.632 ns, density : 0.5705 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_127_/D
Current slack : -0.632 ns, density : 0.5705 End_Point: top/i_gmu_skein/datapathInst/r_reg_127_/D
Current slack : -0.617 ns, density : 0.5705 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_333_/D
Current slack : -0.508 ns, density : 0.5707 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_362_/D
Current slack : -0.508 ns, density : 0.5707 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_360_/D
Current slack : -0.508 ns, density : 0.5707 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_360_/D
Current slack : -0.489 ns, density : 0.5709 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_362_/D
Current slack : -0.489 ns, density : 0.5709 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_362_/D
Current slack : -0.489 ns, density : 0.5709 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_362_/D
Current slack : -0.489 ns, density : 0.5709 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_362_/D
Current slack : -0.489 ns, density : 0.5708 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_362_/D
Current slack : -0.432 ns, density : 0.5710 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_335_/D
Current slack : -0.430 ns, density : 0.5711 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_335_/D
Current slack : -0.417 ns, density : 0.5711 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_335_/D
Current slack : -0.420 ns, density : 0.5711 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_374_/D
Current slack : -0.420 ns, density : 0.5711 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_374_/D
Current slack : -0.420 ns, density : 0.5711 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_374_/D
Current slack : -0.420 ns, density : 0.5711 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_374_/D
Current slack : -0.414 ns, density : 0.5711 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_365_/D
Current slack : -0.385 ns, density : 0.5712 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_383_/D
Current slack : -0.377 ns, density : 0.5713 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_295_/D
Current slack : -0.377 ns, density : 0.5713 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_295_/D
Current slack : -0.373 ns, density : 0.5714 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_359_/D
Current slack : -0.373 ns, density : 0.5714 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_359_/D
Current slack : -0.373 ns, density : 0.5714 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_359_/D
Current slack : -0.373 ns, density : 0.5714 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_359_/D
Current slack : -0.373 ns, density : 0.5713 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_359_/D
Current slack : -0.342 ns, density : 0.5714 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_265_/D
Current slack : -0.340 ns, density : 0.5715 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_276_/D
Current slack : -0.332 ns, density : 0.5715 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_279_/D
Current slack : -0.330 ns, density : 0.5715 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_279_/D
Current slack : -0.330 ns, density : 0.5715 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_279_/D
Current slack : -0.330 ns, density : 0.5715 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_279_/D
Current slack : -0.330 ns, density : 0.5715 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_279_/D
Current slack : -0.330 ns, density : 0.5715 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_279_/D
Current slack : -0.298 ns, density : 0.5717 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_359_/D
Current slack : -0.298 ns, density : 0.5717 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_359_/D
Current slack : -0.294 ns, density : 0.5717 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_308_/D
Current slack : -0.290 ns, density : 0.5718 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_336_/D
Current slack : -0.290 ns, density : 0.5718 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_336_/D
Current slack : -0.290 ns, density : 0.5718 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_336_/D
Current slack : -0.290 ns, density : 0.5718 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_336_/D
Current slack : -0.291 ns, density : 0.5718 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_339_/D
Current slack : -0.274 ns, density : 0.5718 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_127_/D
Current slack : -0.271 ns, density : 0.5719 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_338_/D
*** Starting refinePlace (0:07:24 mem=3745.9M) ***
default core: bins with density > 0.75 = 15.9 % ( 1234 / 7744 )
RPlace IncrNP: Rollback Lev = -3
RPlace: Density =1.120000, incremental np is triggered.
Checking spec file integrity...
Clock gating cells determined by native netlist tracing.
default core: bins with density > 0.75 = 16.5 % ( 1280 / 7744 )
RPlace postIncrNP: Density = 1.120000 -> 0.998870.
*** cpu time = 0:00:11.7.
move report: incrNP moves 15909 insts, mean move: 3.33 um, max move: 30.00 um
max move on inst (top/i_gmu_skein/datapathInst/U5078): (1354.20, 1392.60) --> (1335.00, 1381.80)
Starting refinePlace ...
move report: placeLevelShifters moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Spread Effort: high, pre-route mode.
Finished Phase I. CPU Time = 0:00:30.0, Real Time = 0:00:30.0
move report: preRPlace moves 11328 insts, mean move: 0.75 um, max move: 7.60 um
max move on inst (top/i_gmu_skein/datapathInst/DP_OP_119J1_127_774_U5492): (1238.40, 1270.20) --> (1244.20, 1272.00)
move report: rPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: overall moves 11328 insts, mean move: 0.75 um, max move: 7.60 um
max move on inst (top/i_gmu_skein/datapathInst/DP_OP_119J1_127_774_U5492): (1238.40, 1270.20) --> (1244.20, 1272.00)
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 30.00 um
inst (top/i_gmu_skein/datapathInst/U5078) with max move: (1354.2, 1392.6) -> (1335, 1381.8)
mean (X+Y) = 2.72 um
Total instances flipped for legalization: 111
Total instances moved : 21451
*** cpu=0:00:31.6 mem=3777.5M mem(used)=27.2M***
*** maximum move = 30.0um ***
*** Finished refinePlace (0:08:14 mem=3743.9M) ***
*** Done re-routing un-routed nets (3743.9M) ***
*** Starting delays update (0:08:23 mem=3743.9M) ***
*** Finished delays update (0:10:23 mem=3752.7M) ***
Current slack : -0.290 ns, density : 0.5719 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_255_/D
Current slack : -0.290 ns, density : 0.5719 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_255_/D
Current slack : -0.290 ns, density : 0.5719 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_255_/D
Current slack : -0.290 ns, density : 0.5719 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_255_/D
Current slack : -0.290 ns, density : 0.5719 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_255_/D
Current slack : -0.290 ns, density : 0.5719 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_255_/D
Current slack : -0.238 ns, density : 0.5719 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_362_/D
Current slack : -0.238 ns, density : 0.5719 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_362_/D
Current slack : -0.241 ns, density : 0.5719 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_362_/D
Current slack : -0.224 ns, density : 0.5718 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_303_/D
Current slack : -0.224 ns, density : 0.5718 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_303_/D
Current slack : -0.224 ns, density : 0.5718 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_303_/D
Current slack : -0.224 ns, density : 0.5718 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_303_/D
Current slack : -0.207 ns, density : 0.5718 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_322_/D
Current slack : -0.207 ns, density : 0.5718 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_322_/D
Current slack : -0.207 ns, density : 0.5718 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_322_/D
Current slack : -0.207 ns, density : 0.5718 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_322_/D
Current slack : -0.207 ns, density : 0.5718 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_322_/D
Current slack : -0.207 ns, density : 0.5718 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_322_/D
Current slack : -0.207 ns, density : 0.5718 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_322_/D
Current slack : -0.207 ns, density : 0.5718 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_322_/D
Current slack : -0.862 ns, density : 0.5718 Worst_View: ethz_groestl_slow_view End_Point: top/i_ethz_groestl/i_p/PxDP_reg_6__4__2_/D
Current slack : -0.862 ns, density : 0.5718 Worst_View: ethz_groestl_slow_view End_Point: top/i_ethz_groestl/i_p/PxDP_reg_6__4__2_/D
Current slack : -0.694 ns, density : 0.5718 Worst_View: ethz_keccak_slow_view End_Point: top/i_ethz_keccak/StatexDP_reg_2__1__38_/D
Current slack : -0.678 ns, density : 0.5718 End_Point: top/i_ethz_jh/HxDP_reg_162__2_/D
Current slack : -0.678 ns, density : 0.5718 Worst_View: ethz_jh_slow_view End_Point: top/i_ethz_jh/HxDP_reg_162__2_/D
Current slack : -0.467 ns, density : 0.5727 Worst_View: ethz_keccak_slow_view End_Point: top/OutRegxDP_reg_110_/D
Current slack : -0.359 ns, density : 0.5749 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_82_/D
Current slack : -0.354 ns, density : 0.5749 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_350_/D
Current slack : -0.351 ns, density : 0.5749 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_392_/D
Current slack : -0.351 ns, density : 0.5749 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_392_/D
Current slack : -0.351 ns, density : 0.5749 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_392_/D
Current slack : -0.351 ns, density : 0.5749 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_392_/D
Current slack : -0.350 ns, density : 0.5749 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_392_/D
Current slack : -0.291 ns, density : 0.5750 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_state_reg_output_reg_244_/D
Current slack : -0.278 ns, density : 0.5753 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_309_/D
Current slack : -0.278 ns, density : 0.5753 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_309_/D
Current slack : -0.278 ns, density : 0.5754 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_309_/D
Current slack : -0.278 ns, density : 0.5754 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_309_/D
Current slack : -0.278 ns, density : 0.5754 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_309_/D
Current slack : -0.278 ns, density : 0.5754 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_309_/D
Current slack : -0.278 ns, density : 0.5754 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_309_/D
Current slack : -0.262 ns, density : 0.5756 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_99_/D
Current slack : -0.255 ns, density : 0.5762 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_380_/D
Current slack : -0.736 ns, density : 0.5762 Worst_View: ethz_skein_slow_view End_Point: top/i_inputblock_MsgLenxDP_reg_60_/D
Current slack : -0.255 ns, density : 0.5762 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_380_/D
Current slack : -0.255 ns, density : 0.5762 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_380_/D
Current slack : -0.234 ns, density : 0.5769 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_359_/D
Current slack : -0.234 ns, density : 0.5769 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_359_/D
Current slack : -0.234 ns, density : 0.5769 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_359_/D
Current slack : -0.223 ns, density : 0.5773 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_99_/D
Current slack : -0.221 ns, density : 0.5773 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_99_/D
Current slack : -0.221 ns, density : 0.5773 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_99_/D
Current slack : -0.221 ns, density : 0.5773 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_99_/D
Current slack : -0.221 ns, density : 0.5773 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_99_/D
Current slack : -0.221 ns, density : 0.5773 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_99_/D
Current slack : -0.211 ns, density : 0.5777 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_27_/D
Current slack : -0.200 ns, density : 0.5784 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_281_/D
Current slack : -0.200 ns, density : 0.5784 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_281_/D
Current slack : -0.200 ns, density : 0.5784 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_281_/D
Current slack : -0.200 ns, density : 0.5787 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_281_/D
Current slack : -0.187 ns, density : 0.5821 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_337_/D
Current slack : -0.187 ns, density : 0.5821 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_337_/D
Current slack : -0.133 ns, density : 0.5821 Worst_View: ethz_keccak_slow_view End_Point: top/OutRegxDP_reg_107_/D
Current slack : -0.133 ns, density : 0.5821 End_Point: top/OutRegxDP_reg_107_/D
Current slack : -0.133 ns, density : 0.5820 Worst_View: ethz_keccak_slow_view End_Point: top/OutRegxDP_reg_107_/D
Current slack : -0.133 ns, density : 0.5819 Worst_View: ethz_keccak_slow_view End_Point: top/OutRegxDP_reg_107_/D
Current slack : -0.129 ns, density : 0.5820 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_state_reg_output_reg_459_/D
Current slack : -0.129 ns, density : 0.5821 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_state_reg_output_reg_459_/D
Current slack : -0.117 ns, density : 0.5841 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_307_/D
Current slack : -0.117 ns, density : 0.5841 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_307_/D
Current slack : -0.104 ns, density : 0.5841 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_178_/D
Current slack : -0.104 ns, density : 0.5841 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_178_/D
Current slack : -0.104 ns, density : 0.5841 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_178_/D
Current slack : -0.104 ns, density : 0.5841 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_178_/D
Current slack : -0.104 ns, density : 0.5841 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_178_/D
Current slack : -0.104 ns, density : 0.5842 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_178_/D
Current slack : -0.097 ns, density : 0.5849 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_178_/D
Current slack : -0.097 ns, density : 0.5849 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_178_/D
Current slack : -0.091 ns, density : 0.5849 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_469_/D
Current slack : -0.091 ns, density : 0.5849 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_469_/D
Current slack : -0.093 ns, density : 0.5849 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_state_reg_output_reg_137_/D
Current slack : -0.093 ns, density : 0.5849 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_state_reg_output_reg_137_/D
Current slack : -0.093 ns, density : 0.5849 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_state_reg_output_reg_137_/D
Current slack : -0.091 ns, density : 0.5849 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_469_/D
Current slack : -0.091 ns, density : 0.5849 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_469_/D
Current slack : -0.091 ns, density : 0.5849 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_469_/D
Current slack : -0.091 ns, density : 0.5849 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_469_/D
Current slack : -0.091 ns, density : 0.5849 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_469_/D
Current slack : -0.091 ns, density : 0.5849 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_471_/D
Current slack : -0.091 ns, density : 0.5849 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_471_/D
Current slack : -0.091 ns, density : 0.5849 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_471_/D
Current slack : -0.084 ns, density : 0.5861 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_182_/D
Current slack : -0.078 ns, density : 0.5884 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_331_/D
Current slack : -0.078 ns, density : 0.5885 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_9_/D
Current slack : -0.074 ns, density : 0.5886 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_9_/D
Current slack : -0.074 ns, density : 0.5886 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_9_/D
Current slack : -0.074 ns, density : 0.5886 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_9_/D
Current slack : -0.074 ns, density : 0.5886 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_9_/D
Current slack : -0.074 ns, density : 0.5886 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_9_/D
Current slack : -0.074 ns, density : 0.5886 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_state_reg_output_reg_132_/D
Current slack : -0.071 ns, density : 0.5886 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_49_/D
*** Starting refinePlace (0:45:43 mem=3908.4M) ***
default core: bins with density > 0.75 = 20.2 % ( 1563 / 7744 )
RPlace IncrNP: Rollback Lev = -3
RPlace: Density =1.100000, incremental np is triggered.
Checking spec file integrity...
Clock gating cells determined by native netlist tracing.
default core: bins with density > 0.75 = 21.7 % ( 1680 / 7744 )
RPlace postIncrNP: Density = 1.100000 -> 0.994350.
*** cpu time = 0:00:17.5.
move report: incrNP moves 36657 insts, mean move: 3.63 um, max move: 74.80 um
max move on inst (top/i_gmu_groestl/FE_OCPC19007_n9532): (413.80, 631.20) --> (376.80, 669.00)
Starting refinePlace ...
move report: placeLevelShifters moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Spread Effort: high, pre-route mode.
Finished Phase I. CPU Time = 0:00:31.4, Real Time = 0:00:31.0
move report: preRPlace moves 29854 insts, mean move: 0.76 um, max move: 7.20 um
max move on inst (top/i_gmu_sha2/datapathInst_DP_OP_60J1_124_3254_U423): (1237.80, 402.60) --> (1243.20, 404.40)
move report: rPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: overall moves 29854 insts, mean move: 0.76 um, max move: 7.20 um
max move on inst (top/i_gmu_sha2/datapathInst_DP_OP_60J1_124_3254_U423): (1237.80, 402.60) --> (1243.20, 404.40)
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 74.80 um
inst (top/i_gmu_groestl/FE_OCPC19007_n9532) with max move: (413.8, 631.2) -> (376.8, 669)
mean (X+Y) = 2.75 um
Total instances flipped for legalization: 258
Total instances moved : 54317
*** cpu=0:00:33.0 mem=3912.9M mem(used)=0.0M***
*** maximum move = 74.8um ***
*** Finished refinePlace (0:46:40 mem=3906.4M) ***
*** Done re-routing un-routed nets (3906.4M) ***
*** Starting delays update (0:46:44 mem=3906.4M) ***
*** Finished delays update (0:52:05 mem=3876.7M) ***
post refinePlace cleanup
post refinePlace cleanup
post refinePlace cleanup
post refinePlace cleanup
post refinePlace cleanup
post refinePlace cleanup
post refinePlace cleanup
post refinePlace cleanup
post refinePlace cleanup
post refinePlace cleanup
post refinePlace cleanup
post refinePlace cleanup
post refinePlace cleanup
Current slack : -0.110 ns, density : 0.5887 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_255_/D
Current slack : -0.108 ns, density : 0.5887 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_255_/D
Current slack : -0.108 ns, density : 0.5887 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_255_/D
Current slack : -0.108 ns, density : 0.5887 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_255_/D
Current slack : -0.108 ns, density : 0.5887 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_255_/D
Current slack : -0.108 ns, density : 0.5887 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_255_/D
Current slack : -0.097 ns, density : 0.5887 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_340_/D
RouteType : FE_CTS_DEFAULT
PreferredExtraSpace : 1
Shield : NONE
PreferLayer : M3 M4
RC Information for View dummy_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View ethz_blake_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View ethz_groestl_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View ethz_jh_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View ethz_keccak_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View ethz_sha2_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View ethz_skein_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View gmu_blake_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View gmu_groestl_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View gmu_jh_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View gmu_keccak_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View gmu_sha2_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View gmu_skein_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View ram1_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View ram2_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View ram3_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View test_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View hold_fast_view :
Est. Cap : 0.1491(V=0.1491 H=0.1491) (ff/um) [0.0001491]
Est. Res : 1.30435(V=1.30435 H=1.30435)(ohm/um) [0.00130435]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0974885(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.145(ff/um) res=1.73(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.149(ff/um) res=1.3(ohm/um) viaRes=1.25758(ohm) viaCap=0.0959145(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.149(ff/um) res=1.3(ohm/um) viaRes=1.37179(ohm) viaCap=0.0974885(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.149(ff/um) res=1.3(ohm/um) viaRes=1.37179(ohm) viaCap=0.0974885(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.149(ff/um) res=1.3(ohm/um) viaRes=1.37179(ohm) viaCap=0.0974885(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.147(ff/um) res=1.3(ohm/um) viaRes=1.37179(ohm) viaCap=0.0969772(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.168(ff/um) res=0.309(ohm/um) viaRes=0.333333(ohm) viaCap=0.236025(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.37(ff/um) res=0.00215(ohm/um) viaRes=0.0489583(ohm) viaCap=1.72343(ff)
Current slack : -0.085 ns, density : 0.5887 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_72_/D
Current slack : -0.085 ns, density : 0.5887 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_72_/D
Current slack : -0.084 ns, density : 0.5888 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_481_/D
Current slack : -0.084 ns, density : 0.5888 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_481_/D
Current slack : -0.084 ns, density : 0.5888 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_481_/D
Current slack : -0.084 ns, density : 0.5888 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_481_/D
Current slack : -0.084 ns, density : 0.5888 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_481_/D
Current slack : -0.075 ns, density : 0.5888 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_state_reg_output_reg_502_/D
Current slack : -0.074 ns, density : 0.5888 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_471_/D
Current slack : -0.071 ns, density : 0.5888 End_Point: top/i_gmu_groestl/dp_fx2_256_final_reg_output_reg_162_/D
Current slack : -0.070 ns, density : 0.5888 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_399_/D
Current slack : -0.070 ns, density : 0.5888 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_399_/D
Current slack : -0.070 ns, density : 0.5888 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_399_/D
Current slack : -0.070 ns, density : 0.5888 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_399_/D
Current slack : -0.070 ns, density : 0.5888 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_399_/D
Current slack : -0.066 ns, density : 0.5889 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_257_/D
Current slack : -0.066 ns, density : 0.5889 End_Point: top/i_gmu_groestl/dp_fx2_256_state_reg_output_reg_411_/D
Current slack : -0.292 ns, density : 0.5889 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/keygen_gen/key_out_gen_7_output_reg_63_/D
Current slack : -0.245 ns, density : 0.5889 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/keygen_gen/key_out_gen_7_output_reg_63_/D
Current slack : -0.245 ns, density : 0.5889 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/keygen_gen/key_out_gen_7_output_reg_63_/D
Current slack : -0.243 ns, density : 0.5889 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/keygen_gen/key_out_gen_7_output_reg_63_/D
Current slack : -0.243 ns, density : 0.5889 End_Point: top/i_gmu_skein/datapathInst/keygen_gen/key_out_gen_7_output_reg_63_/D
Current slack : -0.208 ns, density : 0.5889 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_295_/D
Current slack : -0.208 ns, density : 0.5889 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_295_/D
Current slack : -0.208 ns, density : 0.5889 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_295_/D
Current slack : -0.208 ns, density : 0.5889 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_295_/D
Current slack : -0.208 ns, density : 0.5889 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_295_/D
Current slack : -0.173 ns, density : 0.5891 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_304_/D
Current slack : -0.167 ns, density : 0.5892 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_341_/D
Current slack : -0.167 ns, density : 0.5892 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_341_/D
Current slack : -0.163 ns, density : 0.5892 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_295_/D
Current slack : -0.163 ns, density : 0.5892 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_295_/D
Current slack : -0.163 ns, density : 0.5892 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_295_/D
Current slack : -0.163 ns, density : 0.5892 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_295_/D
Current slack : -0.163 ns, density : 0.5892 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_295_/D
Current slack : -0.148 ns, density : 0.5893 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_276_/D
Current slack : -0.148 ns, density : 0.5893 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_276_/D
Current slack : -0.144 ns, density : 0.5893 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_295_/D
Current slack : -0.142 ns, density : 0.5894 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_295_/D
Current slack : -0.142 ns, density : 0.5894 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_295_/D
Current slack : -0.142 ns, density : 0.5894 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_295_/D
Current slack : -0.142 ns, density : 0.5894 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_295_/D
Current slack : -0.142 ns, density : 0.5894 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_295_/D
Current slack : -0.132 ns, density : 0.5895 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_276_/D
Current slack : -0.132 ns, density : 0.5896 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_276_/D
Current slack : -0.129 ns, density : 0.5896 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_276_/D
Current slack : -0.129 ns, density : 0.5896 End_Point: top/i_gmu_skein/datapathInst/r_reg_510_/D
Current slack : -0.128 ns, density : 0.5896 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_510_/D
Current slack : -0.128 ns, density : 0.5896 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_510_/D
Current slack : -0.128 ns, density : 0.5896 End_Point: top/i_gmu_skein/datapathInst/r_reg_510_/D
Current slack : -0.128 ns, density : 0.5896 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_510_/D
Current slack : -0.119 ns, density : 0.5897 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_382_/D
Current slack : -0.118 ns, density : 0.5898 End_Point: top/i_gmu_skein/datapathInst/r_reg_382_/D
Current slack : -0.116 ns, density : 0.5898 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_262_/D
Current slack : -0.116 ns, density : 0.5898 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_262_/D
Current slack : -0.116 ns, density : 0.5898 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_262_/D
Current slack : -0.116 ns, density : 0.5898 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_262_/D
Current slack : -0.116 ns, density : 0.5898 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_262_/D
Current slack : -0.116 ns, density : 0.5898 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_262_/D
Current slack : -0.109 ns, density : 0.5898 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_276_/D
Current slack : -0.108 ns, density : 0.5899 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_276_/D
Current slack : -0.108 ns, density : 0.5899 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_276_/D
Current slack : -0.108 ns, density : 0.5899 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_276_/D
Current slack : -0.108 ns, density : 0.5899 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_276_/D
Current slack : -0.108 ns, density : 0.5899 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_276_/D
Current slack : -0.108 ns, density : 0.5899 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_276_/D
Current slack : -0.108 ns, density : 0.5899 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_276_/D
Current slack : -0.102 ns, density : 0.5899 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_268_/D
Current slack : -0.100 ns, density : 0.5899 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_280_/D
Current slack : -0.100 ns, density : 0.5899 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_280_/D
Current slack : -0.103 ns, density : 0.5899 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_253_/D
Current slack : -0.103 ns, density : 0.5899 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_253_/D
Current slack : -0.103 ns, density : 0.5899 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_253_/D
Current slack : -0.103 ns, density : 0.5899 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_253_/D
Current slack : -0.103 ns, density : 0.5899 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_253_/D
Current slack : -0.096 ns, density : 0.5899 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_295_/D
Current slack : -0.096 ns, density : 0.5899 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_295_/D
Current slack : -0.096 ns, density : 0.5898 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_295_/D
Current slack : -0.067 ns, density : 0.5906 Worst_View: gmu_jh_slow_view End_Point: top/i_gmu_jh/datapath_gen_rreg_gen_output_reg_73_/E
Current slack : -0.062 ns, density : 0.5922 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_493_/D
Current slack : -0.066 ns, density : 0.5923 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_493_/D
Current slack : -0.065 ns, density : 0.5923 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_493_/D
Current slack : -0.065 ns, density : 0.5923 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_493_/D
Current slack : -0.065 ns, density : 0.5923 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_493_/D
Current slack : -0.065 ns, density : 0.5923 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_493_/D
Current slack : -0.065 ns, density : 0.5923 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_493_/D
Current slack : -0.061 ns, density : 0.5923 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_state_reg_output_reg_26_/D
Current slack : -0.061 ns, density : 0.5923 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_304_/D
Current slack : -0.059 ns, density : 0.5922 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_state_reg_output_reg_336_/D
Current slack : -0.059 ns, density : 0.5922 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_state_reg_output_reg_336_/D
Current slack : -0.059 ns, density : 0.5922 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_state_reg_output_reg_336_/D
Current slack : -0.059 ns, density : 0.5922 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_state_reg_output_reg_336_/D
Current slack : -0.059 ns, density : 0.5922 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_state_reg_output_reg_336_/D
Current slack : -0.059 ns, density : 0.5922 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_state_reg_output_reg_336_/D
Current slack : -0.059 ns, density : 0.5922 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_state_reg_output_reg_336_/D
Current slack : -0.054 ns, density : 0.5922 Worst_View: gmu_keccak_slow_view End_Point: top/i_gmu_keccak/datapath_gen_stateRegInst_output_reg_1429_/D
Current slack : -0.054 ns, density : 0.5923 End_Point: top/i_gmu_keccak/datapath_gen_stateRegInst_output_reg_1429_/D
Current slack : -0.077 ns, density : 0.5922 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_state_reg_output_reg_190_/D
Current slack : -0.049 ns, density : 0.5932 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_195_/D
Current slack : -0.053 ns, density : 0.5946 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_480_/D
Current slack : -0.053 ns, density : 0.5946 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_480_/D
Current slack : -0.052 ns, density : 0.5946 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_480_/D
Current slack : -0.052 ns, density : 0.5946 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_480_/D
Current slack : -0.052 ns, density : 0.5946 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_480_/D
Current slack : -0.050 ns, density : 0.5947 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_25_/D
Current slack : -0.050 ns, density : 0.5947 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_25_/D
Current slack : -0.048 ns, density : 0.5947 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_209_/D
Current slack : -0.048 ns, density : 0.5947 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_481_/D
Current slack : -0.079 ns, density : 0.5947 Worst_View: ethz_jh_slow_view End_Point: top/i_ethz_jh/HxDP_reg_38__2_/D
Current slack : -0.079 ns, density : 0.5947 Worst_View: ethz_jh_slow_view End_Point: top/i_ethz_jh/HxDP_reg_38__2_/D
Current slack : -0.079 ns, density : 0.5947 Worst_View: ethz_jh_slow_view End_Point: top/i_ethz_jh/HxDP_reg_38__2_/D
Current slack : -0.055 ns, density : 0.5947 Worst_View: ethz_jh_slow_view End_Point: top/i_ethz_jh/HxDP_reg_38__2_/D
*** Starting refinePlace (2:16:19 mem=4080.3M) ***
default core: bins with density > 0.75 = 23.8 % ( 1846 / 7744 )
RPlace IncrNP: Rollback Lev = -3
RPlace: Density =1.020000, incremental np is triggered.
Checking spec file integrity...
Clock gating cells determined by native netlist tracing.
default core: bins with density > 0.75 = 24.8 % ( 1924 / 7744 )
RPlace postIncrNP: Density = 1.020000 -> 0.997175.
*** cpu time = 0:00:31.6.
move report: incrNP moves 73558 insts, mean move: 2.28 um, max move: 18.00 um
max move on inst (top/i_gmu_groestl/U4801): (554.40, 501.60) --> (545.40, 492.60)
Starting refinePlace ...
move report: placeLevelShifters moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Spread Effort: high, pre-route mode.
Finished Phase I. CPU Time = 0:00:23.1, Real Time = 0:00:23.0
move report: preRPlace moves 41519 insts, mean move: 0.65 um, max move: 7.60 um
max move on inst (top/i_gmu_blake/datapath_gen/r_gen_output_reg_209_): (1146.40, 237.00) --> (1138.80, 237.00)
move report: rPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: overall moves 41519 insts, mean move: 0.65 um, max move: 7.60 um
max move on inst (top/i_gmu_blake/datapath_gen/r_gen_output_reg_209_): (1146.40, 237.00) --> (1138.80, 237.00)
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 18.00 um
inst (top/i_gmu_groestl/U4801) with max move: (554.4, 501.6) -> (545.4, 492.6)
mean (X+Y) = 2.07 um
Total instances flipped for legalization: 533
Total instances moved : 86827
*** cpu=0:00:24.8 mem=4128.0M mem(used)=36.1M***
*** maximum move = 18.0um ***
*** Finished refinePlace (2:17:22 mem=4079.3M) ***
moveBlkTerm was implicitly turned on (since useM1).
*** Starting trialRoute (mem=4079.3M) ***
There are 0 pin guide points passed to trialRoute.
moveBlkTerm was implicitly turned on (since useM1).
Options: -moveBlkTerm -useM1 -handlePreroute -keepMarkedOptRoutes -noPinGuide
Nr of prerouted/Fixed nets = 42
Num blk terms moved = 970787.
routingBox: (100 200) (1874900 1874800)
coreBox: (148800 148800) (1726200 1726200)
Number of multi-gpin terms=0, multi-gpins=0, moved blk term=192/182081
Phase 1a route (0:00:03.0 4184.5M):
Est net length = 1.565e+07um = 7.433e+06H + 8.213e+06V
Usage: (26.7%H 30.1%V) = (7.846e+06um 8.058e+06um) = (7839869 4476816)
Obstruct: 784154 = 288147 (16.7%H) + 496007 (28.8%V)
Overflow: 12822 = 4055 (0.28% H) + 8767 (0.71% V)
Number obstruct path=58151 reroute=0
Phase 1b route (0:00:04.9 4184.5M):
Usage: (27.1%H 30.4%V) = (7.970e+06um 8.140e+06um) = (7964327 4522450)
Overflow: 36884 = 2691 (0.19% H) + 34193 (2.79% V)
Phase 1c route (0:00:03.2 4184.5M):
Usage: (27.1%H 30.4%V) = (7.961e+06um 8.144e+06um) = (7954996 4524509)
Overflow: 31605 = 2404 (0.17% H) + 29202 (2.38% V)
Phase 1d route (0:00:02.6 4184.5M):
Usage: (27.1%H 30.4%V) = (7.962e+06um 8.148e+06um) = (7956368 4526499)
Overflow: 20065 = 791 (0.06% H) + 19275 (1.57% V)
Phase 1e route (0:00:01.9 4248.5M):
Usage: (27.1%H 30.4%V) = (7.972e+06um 8.152e+06um) = (7965839 4528653)
Overflow: 254 = 15 (0.00% H) + 239 (0.02% V)
Phase 1f route (0:00:01.6 4248.5M):
Usage: (27.1%H 30.4%V) = (7.971e+06um 8.152e+06um) = (7965537 4528654)
Overflow: 32 = 3 (0.00% H) + 29 (0.00% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-1: 3 0.00% 29 0.00%
--------------------------------------
0: 342 0.02% 5093 0.42%
1: 1235 0.09% 13390 1.09%
2: 3106 0.22% 19499 1.59%
3: 8454 0.59% 34987 2.85%
4: 11666 0.81% 62717 5.11%
5: 16170 1.13% 284842 23.22%
6: 25258 1.76% 129706 10.57%
7: 29829 2.08% 85246 6.95%
8: 39020 2.72% 78472 6.40%
9: 57733 4.02% 71283 5.81%
10: 61757 4.31% 80052 6.53%
11: 73962 5.16% 57225 4.67%
12: 167284 11.66% 49094 4.00%
13: 207272 14.45% 36097 2.94%
14: 121854 8.49% 30155 2.46%
15: 77384 5.39% 140130 11.42%
16: 73411 5.12% 37917 3.09%
17: 66974 4.67% 442 0.04%
18: 60246 4.20% 5894 0.48%
19: 49679 3.46% 15 0.00%
20: 281814 19.65% 4308 0.35%
Global route (cpu=17.3s real=18.0s 4184.5M)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Phase 1l route (0:00:25.1 4105.6M):
*** After '-updateRemainTrks' operation:
Usage: (27.9%H 32.1%V) = (8.206e+06um 8.601e+06um) = (8200069 4778626)
Overflow: 2910 = 117 (0.01% H) + 2793 (0.23% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-4: 0 0.00% 7 0.00%
-3: 1 0.00% 69 0.01%
-2: 15 0.00% 471 0.04%
-1: 94 0.01% 1993 0.16%
--------------------------------------
0: 537 0.04% 8560 0.70%
1: 1639 0.11% 18843 1.54%
2: 3799 0.26% 27823 2.27%
3: 9654 0.67% 44475 3.63%
4: 13262 0.92% 66651 5.43%
5: 18830 1.31% 284336 23.18%
6: 28332 1.98% 126174 10.29%
7: 33712 2.35% 80453 6.56%
8: 42492 2.96% 73794 6.02%
9: 60307 4.20% 66877 5.45%
10: 63464 4.42% 75549 6.16%
11: 74283 5.18% 53640 4.37%
12: 166602 11.61% 46002 3.75%
13: 206013 14.36% 33829 2.76%
14: 119927 8.36% 28815 2.35%
15: 74593 5.20% 139700 11.39%
16: 70595 4.92% 37919 3.09%
17: 64161 4.47% 425 0.03%
18: 57587 4.01% 5865 0.48%
19: 47252 3.29% 17 0.00%
20: 277302 19.33% 4306 0.35%
Num blk terms moved back = 964029
*** Completed Phase 1 route (0:00:48.3 4105.6M) ***
Total length: 1.609e+07um, number of vias: 2546016
M1(H) length: 1.042e+04um, number of vias: 971675
M2(V) length: 2.704e+06um, number of vias: 972939
M3(H) length: 3.813e+06um, number of vias: 342567
M4(V) length: 3.055e+06um, number of vias: 168213
M5(H) length: 3.336e+06um, number of vias: 80745
M6(V) length: 2.788e+06um, number of vias: 9155
M7(H) length: 3.807e+05um, number of vias: 722
M8(V) length: 8.091e+03um
*** Completed Phase 2 route (0:00:45.5 4086.4M) ***
*** Finished all Phases (cpu=0:01:37 mem=4086.4M) ***
Peak Memory Usage was 4184.5M
*** Finished trialRoute (cpu=0:01:39 mem=4086.4M) ***
*** Starting delays update (2:19:56 mem=3469.0M) ***
*** Finished delays update (2:31:51 mem=4096.3M) ***
post refinePlace cleanup
post refinePlace cleanup
post refinePlace cleanup
post refinePlace cleanup
** Core optimization cpu=2:12:06 real=1:27:27 (88049 evaluations)
*** Done optCritPath (cpu=4:46:17 real=2:59:05 mem=4108.71M) ***
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
Summary (cpu=153.95min real=179.42min mem=4106.7M)
------------------------------------------------------------
+--------------------+---------+
| Setup mode | all |
+--------------------+---------+
| WNS (ns):| -0.129 |
| TNS (ns):| -37.292 |
| Violating Paths:| 980 |
| All Paths:| 85005 |
+--------------------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 2 (2) | -0.020 | 17 (17) |
| max_tran | 1 (3) | -0.693 | 14 (16) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 60.245%
Routing Overflow: 0.01% H and 0.23% V
------------------------------------------------------------
**optDesign ... cpu = 6:07:03, real = 4:06:18, mem = 4106.7M **
Reported timing to dir timingReports_final
**optDesign ... cpu = 6:07:11, real = 4:06:27, mem = 3783.7M **
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
optDesign Final Summary
------------------------------------------------------------
+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| -0.129 | -0.129 | 0.096 | 2.814 | 18.794 | 14.556 |
| TNS (ns):| -37.292 | -37.292 | 0.000 | 0.000 | 0.000 | 0.000 |
| Violating Paths:| 980 | 980 | 0 | 0 | 0 | 0 |
| All Paths:| 85005 | 46605 | 63302 | 19 | 2 | 15 |
+--------------------+---------+---------+---------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 2 (2) | -0.020 | 17 (17) |
| max_tran | 1 (3) | -0.693 | 14 (16) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 60.245%
Routing Overflow: 0.01% H and 0.23% V
------------------------------------------------------------
**optDesign ... cpu = 6:09:43, real = 4:07:51, mem = 3783.7M **
*info: Setting setup target slack to -0.050
*info: Hold target slack is 0.000
**INFO : removing temp dont-use cells (LVT only flow version : 2)
Deleting the dont_use list
*** Finished optDesign ***
timeDesign -reportOnly -expandedViews -outDir timingReports_final -prefix shabziger.preCTS-opt.expV
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
timeDesign Summary
------------------------------------------------------------
+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| -0.129 | -0.129 | 0.096 | 2.814 | 18.794 | 14.556 |
| TNS (ns):| -37.292 | -37.292 | 0.000 | 0.000 | 0.000 | 0.000 |
| Violating Paths:| 980 | 980 | 0 | 0 | 0 | 0 |
| All Paths:| 85005 | 46605 | 63302 | 19 | 2 | 15 |
+--------------------+---------+---------+---------+---------+---------+---------+
|dummy_slow_view | 7.956 | 7.956 | 8.538 | 11.214 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5131 | 2517 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_blake_slow_view| 0.070 | 0.070 | 3.538 | 6.214 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 8290 | 4385 | 3887 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_groestl_slow_view
| | -0.065 | -0.065 | 2.063 | 4.814 | N/A | N/A |
| | -0.262 | -0.262 | 0.000 | 0.000 | N/A | N/A |
| | 12 | 12 | 0 | 0 | N/A | N/A |
| | 8236 | 4070 | 4148 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_jh_slow_view | 0.121 | 0.121 | 1.315 | 4.214 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 8801 | 4640 | 4143 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_keccak_slow_view
| | -0.044 | -0.044 | 0.410 | 3.214 | N/A | N/A |
| | -0.267 | -0.267 | 0.000 | 0.000 | N/A | N/A |
| | 16 | 16 | 0 | 0 | N/A | N/A |
| | 8346 | 4125 | 4203 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_sha2_slow_view | 0.130 | 0.130 | 2.038 | 4.714 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 7204 | 3554 | 3632 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_skein_slow_view| -0.013 | -0.013 | 1.162 | 4.014 | N/A | N/A |
| | -0.041 | -0.041 | 0.000 | 0.000 | N/A | N/A |
| | 4 | 4 | 0 | 0 | N/A | N/A |
| | 9002 | 4517 | 4467 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_blake_slow_view | -0.109 | -0.109 | 2.438 | 5.114 | N/A | N/A |
| | -7.079 | -7.079 | 0.000 | 0.000 | N/A | N/A |
| | 125 | 125 | 0 | 0 | N/A | N/A |
| | 9724 | 5498 | 4208 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_groestl_slow_view
| | -0.102 | -0.102 | 0.458 | 3.314 | N/A | N/A |
| | -23.886 | -23.886 | 0.000 | 0.000 | N/A | N/A |
| | 670 | 670 | 0 | 0 | N/A | N/A |
| | 9252 | 5088 | 4146 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_jh_slow_view | -0.032 | -0.032 | 0.138 | 2.814 | N/A | N/A |
| | -0.116 | -0.116 | 0.000 | 0.000 | N/A | N/A |
| | 7 | 7 | 0 | 0 | N/A | N/A |
| | 10269 | 5853 | 4398 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_keccak_slow_view| -0.031 | -0.031 | 0.096 | 2.814 | N/A | N/A |
| | -0.570 | -0.570 | 0.000 | 0.000 | N/A | N/A |
| | 45 | 45 | 0 | 0 | N/A | N/A |
| | 9926 | 5702 | 4206 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_sha2_slow_view | -0.031 | -0.031 | 0.237 | 3.014 | N/A | N/A |
| | -0.316 | -0.316 | 0.000 | 0.000 | N/A | N/A |
| | 13 | 13 | 0 | 0 | N/A | N/A |
| | 7986 | 4238 | 3730 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_skein_slow_view | -0.129 | -0.129 | 0.917 | 6.714 | N/A | N/A |
| | -4.761 | -4.761 | 0.000 | 0.000 | N/A | N/A |
| | 89 | 89 | 0 | 0 | N/A | N/A |
| | 10156 | 5551 | 4587 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ram1_slow_view | 5.179 | 5.179 | 8.538 | 11.214 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5237 | 2623 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ram2_slow_view | 4.977 | 4.977 | 8.538 | 11.214 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5237 | 2623 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ram3_slow_view | 3.367 | 3.367 | 8.538 | 11.214 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5240 | 2626 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|test_slow_view | 11.783 | 13.329 | 11.783 | 21.135 | 18.794 | 14.556 |
| | 0.000 | 0.000 | 0.000 | 0.000 | 0.000 | 0.000 |
| | 0 | 0 | 0 | 0 | 0 | 0 |
| | 85005 | 46605 | 63302 | 19 | 2 | 15 |
+--------------------+---------+---------+---------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 2 (2) | -0.020 | 17 (17) |
| max_tran | 1 (3) | -0.693 | 14 (16) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 60.245%
------------------------------------------------------------
Reported timing to dir timingReports_final
Total CPU time: 211.94 sec
Total Real time: 154.0 sec
Total Memory Usage: 3745.976562 Mbytes
saveDesign save/chip_shabziger.preCTS-opt.enc
**WARN: (ENCSYT-3036): Design directory save/chip_shabziger.preCTS-opt.enc.dat exists, rename it to save/chip_shabziger.preCTS-opt.enc.dat.tmp.
If saveDesign succeeds, it will be deleted.
Writing Netlist "save/chip_shabziger.preCTS-opt.enc.dat/shabziger_chip.v.gz" ...
Saving configuration ...
Saving preference file save/chip_shabziger.preCTS-opt.enc.dat/enc.pref.tcl ...
Saving floorplan ...
Saving Drc markers ...
... 176 Drc markers are saved ...
Saving placement ...
*** Completed savePlace (cpu=0:00:00.4 real=0:00:01.0 mem=3746.0M) ***
Saving route ...
*** Completed saveRoute (cpu=0:00:06.2 real=0:00:14.0 mem=3746.0M) ***
Writing DEF file 'save/chip_shabziger.preCTS-opt.enc.dat/shabziger_chip.def.gz', current time is Thu Sep 29 17:54:47 2011 ...
unitPerMicron=1000, dbgMicronPerDBU=0.001000, unitPerDBU=1.000000
DEF file 'save/chip_shabziger.preCTS-opt.enc.dat/shabziger_chip.def.gz' is written, current time is Thu Sep 29 17:54:47 2011 ...
*** Completed saveYieldMap (cpu=: 0:00:00.0 real=0:00:00.0 mem=: 0.000M) ***
setCTSMode -reportHTML true
clockDesign -specFile src/shabziger.ctstch -outDir timingReports_final -fixedInstBeforeCTS
**clockDesign ... cpu = 0:00:00, real = 0:00:00, mem = 3746.0M **
setCTSMode -moveGateLimit 25 -reportHTML true
'setCTSMode -routeClkNet true' is set inside clockDesign.
cleanupSpecifyClockTree
specifyClockTree -file src/shabziger.ctstch
Checking spec file integrity...
Reading clock tree spec file 'src/shabziger.ctstch' ...
RouteType : FE_CTS_DEFAULT
PreferredExtraSpace : 1
Shield : NONE
PreferLayer : M3 M4
RC Information for View dummy_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View ethz_blake_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View ethz_groestl_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View ethz_jh_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View ethz_keccak_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View ethz_sha2_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View ethz_skein_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View gmu_blake_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View gmu_groestl_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View gmu_jh_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View gmu_keccak_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View gmu_sha2_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View gmu_skein_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View ram1_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View ram2_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View ram3_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View test_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View hold_fast_view :
Est. Cap : 0.1491(V=0.1491 H=0.1491) (ff/um) [0.0001491]
Est. Res : 1.30435(V=1.30435 H=1.30435)(ohm/um) [0.00130435]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0974885(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.145(ff/um) res=1.73(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.149(ff/um) res=1.3(ohm/um) viaRes=1.25758(ohm) viaCap=0.0959145(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.149(ff/um) res=1.3(ohm/um) viaRes=1.37179(ohm) viaCap=0.0974885(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.149(ff/um) res=1.3(ohm/um) viaRes=1.37179(ohm) viaCap=0.0974885(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.149(ff/um) res=1.3(ohm/um) viaRes=1.37179(ohm) viaCap=0.0974885(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.147(ff/um) res=1.3(ohm/um) viaRes=1.37179(ohm) viaCap=0.0969772(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.168(ff/um) res=0.309(ohm/um) viaRes=0.333333(ohm) viaCap=0.236025(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.37(ff/um) res=0.00215(ohm/um) viaRes=0.0489583(ohm) viaCap=1.72343(ff)
RouteType : FE_CTS_DEFAULT_LEAF
PreferredExtraSpace : 1
Shield : NONE
PreferLayer : M3 M4
RC Information for View dummy_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View ethz_blake_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View ethz_groestl_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View ethz_jh_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View ethz_keccak_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View ethz_sha2_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View ethz_skein_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View gmu_blake_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View gmu_groestl_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View gmu_jh_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View gmu_keccak_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View gmu_sha2_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View gmu_skein_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View ram1_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View ram2_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View ram3_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View test_slow_view :
Est. Cap : 0.1513(V=0.1513 H=0.1513) (ff/um) [0.0001513]
Est. Res : 1.76471(V=1.76471 H=1.76471)(ohm/um) [0.00176471]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0989269(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.134(ff/um) res=2.35(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.25758(ohm) viaCap=0.0926227(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.151(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0989269(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.143(ff/um) res=1.76(ohm/um) viaRes=1.37179(ohm) viaCap=0.0965208(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.161(ff/um) res=0.418(ohm/um) viaRes=0.333333(ohm) viaCap=0.22779(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.389(ff/um) res=0.00295(ohm/um) viaRes=0.0489583(ohm) viaCap=1.77396(ff)
RC Information for View hold_fast_view :
Est. Cap : 0.1491(V=0.1491 H=0.1491) (ff/um) [0.0001491]
Est. Res : 1.30435(V=1.30435 H=1.30435)(ohm/um) [0.00130435]
Est. Via Res : 1.37179(ohm) [2.62937]
Est. Via Cap : 0.0974885(ff)
M1(H) w=0.09(um) s=0.09(um) p=0.2(um) es=0.31(um) cap=0.145(ff/um) res=1.73(ohm/um) viaRes=0(ohm) viaCap=0(ff)
M2(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.149(ff/um) res=1.3(ohm/um) viaRes=1.25758(ohm) viaCap=0.0959145(ff)
M3(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.149(ff/um) res=1.3(ohm/um) viaRes=1.37179(ohm) viaCap=0.0974885(ff)
M4(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.149(ff/um) res=1.3(ohm/um) viaRes=1.37179(ohm) viaCap=0.0974885(ff)
M5(H) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.149(ff/um) res=1.3(ohm/um) viaRes=1.37179(ohm) viaCap=0.0974885(ff)
M6(V) w=0.1(um) s=0.1(um) p=0.2(um) es=0.3(um) cap=0.147(ff/um) res=1.3(ohm/um) viaRes=1.37179(ohm) viaCap=0.0969772(ff)
M7(H) w=0.2(um) s=0.2(um) p=0.4(um) es=0.6(um) cap=0.168(ff/um) res=0.309(ohm/um) viaRes=0.333333(ohm) viaCap=0.236025(ff)
M8(V) w=2(um) s=2(um) p=4(um) es=6(um) cap=0.37(ff/um) res=0.00215(ohm/um) viaRes=0.0489583(ohm) viaCap=1.72343(ff)
Total Macromodels Extracted = 0
Active Analysis Views for CTS are,
#1 dummy_slow_view
#2 ethz_blake_slow_view
#3 ethz_groestl_slow_view
#4 ethz_jh_slow_view
#5 ethz_keccak_slow_view
#6 ethz_sha2_slow_view
#7 ethz_skein_slow_view
#8 gmu_blake_slow_view
#9 gmu_groestl_slow_view
#10 gmu_jh_slow_view
#11 gmu_keccak_slow_view
#12 gmu_sha2_slow_view
#13 gmu_skein_slow_view
#14 ram1_slow_view
#15 ram2_slow_view
#16 ram3_slow_view
#17 test_slow_view
#18 hold_fast_view
Default Analysis Views is dummy_slow_view
****** AutoClockRootPin ******
AutoClockRootPin 1: ClkxCI
# NoGating NO
# SetDPinAsSync NO
# SetIoPinAsSync NO
# SetAsyncSRPinAsSync NO
# SetTriStEnPinAsSync NO
# SetBBoxPinAsSync NO
# RouteClkNet YES
# PostOpt YES
# RouteType FE_CTS_DEFAULT
# LeafRouteType FE_CTS_DEFAULT_LEAF
***** !! NOTE !! *****
CTS treats D-pins and I/O pins as non-synchronous pins by default.
If you want to change the behavior, you need to use the SetDPinAsSync
or SetIoPinAsSync statement in the clock tree specification file,
or use the setCTSMode -traceDPinAsLeaf {true|false} command,
or use the setCTSMode -traceIoPinAsLeaf {true|false} command
before specifyClockTree command.
*** End specifyClockTree (cpu=0:00:00.1, real=0:00:00.0, mem=3746.0M) ***
changeClockStatus -all -fixedBuffers
Redoing specifyClockTree ...
Checking spec file integrity...
*** Changed status on (21212) instances, and (0) nets in Clock ClkxCI.
*** End changeClockStatus (cpu=0:00:04.5, real=0:00:04.0, mem=3746.0M) ***
deleteClockTree -all
Redoing specifyClockTree ...
Checking spec file integrity...
deleteClockTree Option : -all
*** Removed (0) buffers and (0) inverters in Clock ClkxCI.
***** Delete Clock Tree Finished (CPU Time: 0:00:00.2 MEM: 3745.992M)
*** End deleteClockTree (cpu=0:00:00.3, real=0:00:01.0, mem=3746.0M) ***
ckSynthesis -report timingReports_final/clock.report -forceReconvergent -breakLoop
Redoing specifyClockTree ...
Checking spec file integrity...
***** Allocate Placement Memory Finished (MEM: 3595.406M)
Start to trace clock trees ...
*** Begin Tracer (mem=3595.4M) ***
Tracing Clock ClkxCI ...
Reconvergent mux Check for spec:ClkxCI
============================================================
Reconvergent mux Checks Finished, CPU=0:00:00.0
============================================================
*** End Tracer (mem=3595.4M) ***
***** Allocate Obstruction Memory Finished (MEM: 3595.406M)
#############################################################################
#
# Pre-Synthesis Checks and Parameters
#
#############################################################################
Types of Check : Enabled|Disabled
----------------------------------------------------------------------------
Check cell drive strength : enabled
Check root input transition : enabled
Check pin capacitance : enabled
Check multiple path through MUX : enabled
Check gating depth : enabled
Check placement near clock pins : enabled
Check route blockages over clock pins : enabled
Report FIXED, DontUse and DontTouch : enabled
clock gating checks : enabled
MacroModel checks : enabled
Parameters of checking :
CTS uses following values to determine if diagnostic checks are successful.
Use setCTSMode to change default values.
----------------------------------------------------------------------------
1) Pin capacitance check
Threshold for MaxCap check : 90% of constraint (default)
2) Gating depth check
Maximum gating depth : 10 levels (default)
3) Placement near clock pin check
Threshold distance for placeable location : 5.4(um) (default)
4) Clock gating location check
Allowed clock gate detour : 290(um) (default)
Allowed clock gate sinks' BBOx overlap ratio : 0.5 (default)
5) Macromodel check
MacroModel max delay threshold : 0.9 (default)
MacroModel max skew threshold : 0.9 (default)
MacroModel variance step size : 100ps (default)
****** Clock (ClkxCI) Diagnostic check Parameters
Assumed driver input transition : 49.4(ps) (derived from CKINVM48W)
Threshold for MaxBufTran check : 225(ps) derived from 90% (default) MaxBufTran constraint
Threshold for MaxSinkTran check : 315(ps) derived from 90% (default) MaxSinkTran constraint
Root Input Transition : [0.1(ps) 0.1(ps)]
Max Cap Limit Checks
============================================================
**WARN: (ENCCK-6003): The input capacitance of cell IUMB(PAD) is 2.487pF, (timing library u065gioll25mvir_25_wc is 2.487pF, macro-model definition is 0.000pF), which may make it difficult to meet max buf transition constraint. Number of gated instances having this cell type = 1.
Max Cap Limit Checks Finished, CPU=0:00:00.2
============================================================
Deep Gating Level Checks
============================================================
** INFO Clock ClkxCI has a maximum of 3 levels of logic before synthesis.
Deep Gating Level Checks Finished, CPU=0:00:00.0
============================================================
Max placement distance Checks
============================================================
**WARN: (ENCCK-6325): Clock ClkxCI has instance pin pad_Clk/PAD which is far from any legal placement location. The nearest available placement location is at (1139.8, 1723.8), which is 63.45 microns away.
It may be difficult to drive this pin with an acceptable transition time. Check to make sure that the placement of this instance and the floorplan are realistic.
Max placement distance Checks Finished, CPU=0:00:01.1
============================================================
Root input tran Checks
============================================================
Root input tran Checks Finished, CPU=0:00:01.1
============================================================
Attribute settings check
============================================================
Following standard cells instances have FIXED placement
---------------------------------------------------------
LAGCEM2R : top/i_clockgate_14/i_clkgate
LAGCEM2R : top/i_clockgate_13/i_clkgate
LAGCEM2R : top/i_clockgate_12/i_clkgate
LAGCEM2R : top/i_clockgate_11/i_clkgate
LAGCEM2R : top/i_clockgate_10/i_clkgate
LAGCEM2R : top/i_clockgate_9/i_clkgate
LAGCEM2R : top/i_clockgate_8/i_clkgate
LAGCEM2R : top/i_clockgate_7/i_clkgate
LAGCEM2R : top/i_clockgate_6/i_clkgate
LAGCEM2R : top/i_clockgate_5/i_clkgate
LAGCEM2R : top/i_clockgate_4/i_clkgate
LAGCEM2R : top/i_clockgate_3/i_clkgate
LAGCEM2R : top/i_clockgate_2/i_clkgate
LAGCEM2R : top/i_clockgate_1/i_clkgate
LAGCEM2R : top/i_clockgate_0/i_clkgate
CKXOR2M1RA : top/i_clkxor/i_xor
Following instances are marked as DontTouch
+------------------------------------------------------------------------------------------+---------------------------------------+
| Instance | Analysis Views |
+------------------------------------------------------------------------------------------+---------------------------------------+
+------------------------------------------------------------------------------------------+---------------------------------------+
Following Cells are marked as DontUse in library
+-----------------------------------+----------------------------------------------------------------------------------------------+
| Cell | Analysis Views |
+-----------------------------------+----------------------------------------------------------------------------------------------+
| XOR2M0RA | dummy_slow_views ethz_blake_slow_views ethz_groestl_slow_views ethz_jh_slow_views |
| | ethz_keccak_slow_view ethz_sha2_slow_views ethz_skein_slow_views gmu_blake_slow_views |
| | gmu_groestl_slow_view gmu_jh_slow_views gmu_keccak_slow_views gmu_sha2_slow_views |
| | gmu_skein_slow_view ram1_slow_views ram2_slow_views ram3_slow_views test_slow_views |
| XOR2M0SA | dummy_slow_views ethz_blake_slow_views ethz_groestl_slow_views ethz_jh_slow_views |
| | ethz_keccak_slow_view ethz_sha2_slow_views ethz_skein_slow_views gmu_blake_slow_views |
| | gmu_groestl_slow_view gmu_jh_slow_views gmu_keccak_slow_views gmu_sha2_slow_views |
| | gmu_skein_slow_view ram1_slow_views ram2_slow_views ram3_slow_views test_slow_views |
| XOR2M0WA | dummy_slow_views ethz_blake_slow_views ethz_groestl_slow_views ethz_jh_slow_views |
| | ethz_keccak_slow_view ethz_sha2_slow_views ethz_skein_slow_views gmu_blake_slow_views |
| | gmu_groestl_slow_view gmu_jh_slow_views gmu_keccak_slow_views gmu_sha2_slow_views |
| | gmu_skein_slow_view ram1_slow_views ram2_slow_views ram3_slow_views test_slow_views |
+-----------------------------------+----------------------------------------------------------------------------------------------+
Following Cells are marked as DontUse in SDC
+-----------------------------------+----------------------------------------------------------------------------------------------+
| Cell | Analysis Views |
+-----------------------------------+----------------------------------------------------------------------------------------------+
Following Cells are marked as DontTouch in library
+-----------------------------------+----------------------------------------------------------------------------------------------+
| Cell | Analysis Views |
+-----------------------------------+----------------------------------------------------------------------------------------------+
| XOR2M0RA | dummy_slow_views ethz_blake_slow_views ethz_groestl_slow_views ethz_jh_slow_views |
| | ethz_keccak_slow_view ethz_sha2_slow_views ethz_skein_slow_views gmu_blake_slow_views |
| | gmu_groestl_slow_view gmu_jh_slow_views gmu_keccak_slow_views gmu_sha2_slow_views |
| | gmu_skein_slow_view ram1_slow_views ram2_slow_views ram3_slow_views test_slow_views |
| XOR2M0SA | dummy_slow_views ethz_blake_slow_views ethz_groestl_slow_views ethz_jh_slow_views |
| | ethz_keccak_slow_view ethz_sha2_slow_views ethz_skein_slow_views gmu_blake_slow_views |
| | gmu_groestl_slow_view gmu_jh_slow_views gmu_keccak_slow_views gmu_sha2_slow_views |
| | gmu_skein_slow_view ram1_slow_views ram2_slow_views ram3_slow_views test_slow_views |
| XOR2M0WA | dummy_slow_views ethz_blake_slow_views ethz_groestl_slow_views ethz_jh_slow_views |
| | ethz_keccak_slow_view ethz_sha2_slow_views ethz_skein_slow_views gmu_blake_slow_views |
| | gmu_groestl_slow_view gmu_jh_slow_views gmu_keccak_slow_views gmu_sha2_slow_views |
| | gmu_skein_slow_view ram1_slow_views ram2_slow_views ram3_slow_views test_slow_views |
+-----------------------------------+----------------------------------------------------------------------------------------------+
Following Cells are marked as DontTouch in SDC
+-----------------------------------+----------------------------------------------------------------------------------------------+
| Cell | Analysis Views |
+-----------------------------------+----------------------------------------------------------------------------------------------+
Attribute settings check Finished, CPU=0:00:00.1
============================================================
Routing OBS checks
============================================================
Routing OBS Checks Finished, CPU=0:00:00.5
============================================================
Weak Cell Checks
============================================================
**WARN: (ENCCK-6316): The buffer cell choice CKBUFM1W (library uk65lscllmvbbl_108c125_wc clock ClkxCI) might not have sufficient strength to meet the maximum buffer transition constraint.
**WARN: (ENCCK-6316): The buffer cell choice CKBUFM2W (library uk65lscllmvbbl_108c125_wc clock ClkxCI) might not have sufficient strength to meet the maximum buffer transition constraint.
**WARN: (ENCCK-6316): The buffer cell choice CKBUFM3W (library uk65lscllmvbbl_108c125_wc clock ClkxCI) might not have sufficient strength to meet the maximum buffer transition constraint.
**WARN: (ENCCK-6316): The buffer cell choice CKBUFM4W (library uk65lscllmvbbl_108c125_wc clock ClkxCI) might not have sufficient strength to meet the maximum buffer transition constraint.
**WARN: (ENCCK-6316): The buffer cell choice CKINVM1W (library uk65lscllmvbbl_108c125_wc clock ClkxCI) might not have sufficient strength to meet the maximum buffer transition constraint.
**WARN: (ENCCK-6316): The buffer cell choice CKINVM2W (library uk65lscllmvbbl_108c125_wc clock ClkxCI) might not have sufficient strength to meet the maximum buffer transition constraint.
**WARN: (ENCCK-6316): The buffer cell choice CKINVM3W (library uk65lscllmvbbl_108c125_wc clock ClkxCI) might not have sufficient strength to meet the maximum buffer transition constraint.
**WARN: (ENCCK-6316): The buffer cell choice CKINVM4W (library uk65lscllmvbbl_108c125_wc clock ClkxCI) might not have sufficient strength to meet the maximum buffer transition constraint.
Weak Cell Checks Finished, CPU=0:00:00.0
============================================================
MacroModel Debugging Check
==========================
MacroModel Debugging Check Finished, CPU=0:00:00.0
============================================================
Clock gating checks
============================================================
Clock gating Checks Finished, CPU=0:00:00.1
============================================================
#############################################################################
#
# Summary of Pre-Synthesis Checks
#
#############################################################################
Types of Check : Number of warnings
----------------------------------------------------------------------------
Check cell drive strength : 8
Check root input transition : 0
Check pin capacitance : 1
Check multiple path through MUX : 0
Check gating depth : 0
Check placement near clock pins : 1
Check route blockages over clock pins : 0
Report FIXED, DontUse and DontTouch : 0
clock gating checks : 0
MacroModel checks : 0
#############################################################################
#
# During-Synthesis Checks and Parameters
#
#############################################################################
Types of Check : Enabled|Disabled
----------------------------------------------------------------------------
Check RefinePlacement move distance : enabled
Check route layer follows preference : enabled
Check route follows guide : enabled
clock gating checks : enabled
Parameters of checking :
CTS uses following values to determine if diagnostic checks are successful.
Use setCTSMode to change default values.
----------------------------------------------------------------------------
1) Route layer follows preference check
Minimum preferred layer utilization : 80% (default)
Minimum length to check threshold : 40(um) (default)
2) Route follows guide check
Deviation in length from route guide : 50% (user set)
Minimum length to check threshold : 40(um) (default)
Delay threshold : 10(ps) (default)
3) Saving intermediate database
Save long-running subtrees time : 0(min) (default)
Maximum number of saved databases : 1 (default)
4) Clock gating location check
Allowed clock gate detour : 290(um) (default)
****** Clock (ClkxCI) Diagnostic check Parameters
Assumed driver input transition : 49.4(ps) (derived from CKINVM48W)
Threshold for MaxBufTran check : 225(ps) derived from 90% (default) MaxBufTran constraint
Threshold for MaxSinkTran check : 315(ps) derived from 90% (default) MaxSinkTran constraint
Movement threshold : 46.875000(um) (derived 5% of MaxBuf strength)
Root Input Transition : [0.1(ps) 0.1(ps)]
****** Clock Tree (ClkxCI) Structure
Max. Skew : 250(ps)
Max. Sink Transition: 350(ps)
Max. Buf Transition : 250(ps)
Max. Delay : 1000(ps)
Min. Delay : 0(ps)
Buffer : (CKINVM1W) (CKBUFM1W) (CKINVM2W) (CKBUFM2W) (CKINVM3W) (CKBUFM3W) (CKINVM4W) (CKBUFM4W) (CKBUFM6W) (CKINVM6W) (CKBUFM8W) (CKINVM8W) (CKINVM12W) (CKBUFM12W) (CKINVM16W) (CKBUFM16W) (CKBUFM20W) (CKINVM20W) (CKBUFM22WA) (CKINVM22WA) (CKBUFM24W) (CKINVM24W) (CKBUFM26WA) (CKINVM26WA) (CKBUFM32W) (CKINVM32W) (CKBUFM40W) (CKINVM40W) (CKBUFM48W) (CKINVM48W)
Nr. Subtrees : 18
Nr. Sinks : 21199
Nr. Rising Sync Pins : 21199
Nr. Inverter Rising Sync Pins : 0
Nr. Falling Sync Pins : 0
Nr. Inverter Falling Sync Pins : 0
***********************************************************
SubTree No: 0
Input_Pin: (top/i_clockgate_14/i_clkgate/CK)
Output_Pin: (top/i_clockgate_14/i_clkgate/GCK)
Output_Net: (top/CoreClkxC[14])
**** CK_START: TopDown Tree Construction for top/CoreClkxC[14] (1-leaf) (mem=3595.4M)
Find 7 route_obs, 3 place_obs, 0 cut_obs 1 fence channel(s),
8 channel(s).
Total 0 topdown clustering.
Trig. Edge Skew=0[234,234*] N1 B1 G1 A4(4.0) L[2,2] C2/0 score=28405 cpu=0:00:00.0 mem=3595M
**** CK_END: TopDown Tree Construction for top/CoreClkxC[14] (cpu=0:00:00.1, real=0:00:00.0, mem=3595.4M)
**** CK_START: Update Database (mem=3595.4M)
1 Clock Buffers/Inverters inserted.
**** CK_END: Update Database (cpu=0:00:00.0, real=0:00:00.0, mem=3595.4M)
**** CK_START: Macro Models Generation (mem=3595.4M)
Macro model: Skew=0[234,234]ps N2 inTran=0/0ps.
**** CK_END: Macro Models Generation (cpu=0:00:00.0, real=0:00:00.0, mem=3595.4M)
SubTree No: 1
Input_Pin: (top/i_clockgate_13/i_clkgate/CK)
Output_Pin: (top/i_clockgate_13/i_clkgate/GCK)
Output_Net: (top/CoreClkxC[13])
**** CK_START: TopDown Tree Construction for top/CoreClkxC[13] (2002-leaf) (mem=3595.4M)
Total 3 topdown clustering.
Trig. Edge Skew=68[422,489*] N2002 B45 G1 A402(402.3) L[4,4] score=59809 cpu=0:00:50.0 mem=3595M
**** CK_END: TopDown Tree Construction for top/CoreClkxC[13] (cpu=0:00:50.0, real=0:00:50.0, mem=3595.4M)
**** CK_START: Update Database (mem=3595.4M)
45 Clock Buffers/Inverters inserted.
**** CK_END: Update Database (cpu=0:00:00.1, real=0:00:00.0, mem=3595.4M)
**** CK_START: Macro Models Generation (mem=3595.4M)
Macro model: Skew=69[419,488]ps N46 inTran=0/0ps.
**** CK_END: Macro Models Generation (cpu=0:00:00.1, real=0:00:00.0, mem=3595.4M)
SubTree No: 2
Input_Pin: (top/i_clockgate_12/i_clkgate/CK)
Output_Pin: (top/i_clockgate_12/i_clkgate/GCK)
Output_Net: (top/CoreClkxC[12])
**** CK_START: TopDown Tree Construction for top/CoreClkxC[12] (1610-leaf) (mem=3595.4M)
Total 3 topdown clustering.
Trig. Edge Skew=82[484,566*] N1610 B41 G1 A218(218.0) L[6,6] C3/1 score=67642 cpu=0:00:36.0 mem=3595M
**** CK_END: TopDown Tree Construction for top/CoreClkxC[12] (cpu=0:00:36.3, real=0:00:37.0, mem=3595.4M)
**** CK_START: Update Database (mem=3595.4M)
41 Clock Buffers/Inverters inserted.
**** CK_END: Update Database (cpu=0:00:00.1, real=0:00:00.0, mem=3595.4M)
**** CK_START: Macro Models Generation (mem=3595.4M)
Macro model: Skew=81[489,571]ps N42 inTran=0/0ps.
**** CK_END: Macro Models Generation (cpu=0:00:00.1, real=0:00:00.0, mem=3595.4M)
SubTree No: 3
Input_Pin: (top/i_clockgate_11/i_clkgate/CK)
Output_Pin: (top/i_clockgate_11/i_clkgate/GCK)
Output_Net: (top/CoreClkxC[11])
**** CK_START: TopDown Tree Construction for top/CoreClkxC[11] (1802-leaf) (mem=3595.4M)
Total 4 topdown clustering.
Trig. Edge Skew=48[480,528*] N1802 B46 G1 A263(263.0) L[5,5] C2/1 score=63579 cpu=0:00:43.0 mem=3595M
**** CK_END: TopDown Tree Construction for top/CoreClkxC[11] (cpu=0:00:43.3, real=0:00:43.0, mem=3595.4M)
**** CK_START: Update Database (mem=3595.4M)
46 Clock Buffers/Inverters inserted.
**** CK_END: Update Database (cpu=0:00:00.0, real=0:00:00.0, mem=3595.4M)
**** CK_START: Macro Models Generation (mem=3595.4M)
Macro model: Skew=47[478,525]ps N47 inTran=0/0ps.
**** CK_END: Macro Models Generation (cpu=0:00:00.1, real=0:00:00.0, mem=3595.4M)
SubTree No: 4
Input_Pin: (top/i_clockgate_10/i_clkgate/CK)
Output_Pin: (top/i_clockgate_10/i_clkgate/GCK)
Output_Net: (top/CoreClkxC[10])
**** CK_START: TopDown Tree Construction for top/CoreClkxC[10] (1550-leaf) (mem=3595.4M)
Total 3 topdown clustering.
Trig. Edge Skew=84[466,550*] N1550 B39 G1 A246(246.3) L[5,5] C2/1 score=65836 cpu=0:00:58.0 mem=3595M
**** CK_END: TopDown Tree Construction for top/CoreClkxC[10] (cpu=0:00:58.1, real=0:00:58.0, mem=3595.4M)
**** CK_START: Update Database (mem=3595.4M)
39 Clock Buffers/Inverters inserted.
**** CK_END: Update Database (cpu=0:00:00.1, real=0:00:00.0, mem=3595.4M)
**** CK_START: Macro Models Generation (mem=3595.4M)
Macro model: Skew=84[465,549]ps N40 inTran=0/0ps.
**** CK_END: Macro Models Generation (cpu=0:00:00.1, real=0:00:01.0, mem=3595.4M)
SubTree No: 5
Input_Pin: (top/i_clockgate_9/i_clkgate/CK)
Output_Pin: (top/i_clockgate_9/i_clkgate/GCK)
Output_Net: (top/CoreClkxC[9])
**** CK_START: TopDown Tree Construction for top/CoreClkxC[9] (1612-leaf) (mem=3595.4M)
Total 3 topdown clustering.
Trig. Edge Skew=43[449,492*] N1612 B33 G1 A201(200.7) L[3,3] score=58125 cpu=0:00:42.0 mem=3595M
**** CK_END: TopDown Tree Construction for top/CoreClkxC[9] (cpu=0:00:42.4, real=0:00:42.0, mem=3595.4M)
**** CK_START: Update Database (mem=3595.4M)
33 Clock Buffers/Inverters inserted.
**** CK_END: Update Database (cpu=0:00:00.1, real=0:00:00.0, mem=3595.4M)
**** CK_START: Macro Models Generation (mem=3595.4M)
Macro model: Skew=44[445,489]ps N34 inTran=0/0ps.
**** CK_END: Macro Models Generation (cpu=0:00:00.1, real=0:00:00.0, mem=3595.4M)
SubTree No: 6
Input_Pin: (top/i_clockgate_8/i_clkgate/CK)
Output_Pin: (top/i_clockgate_8/i_clkgate/GCK)
Output_Net: (top/CoreClkxC[8])
**** CK_START: TopDown Tree Construction for top/CoreClkxC[8] (1134-leaf) (mem=3595.4M)
Total 3 topdown clustering.
Trig. Edge Skew=40[413,454*] N1134 B53 G1 A177(176.7) L[4,4] score=56358 cpu=0:00:30.0 mem=3595M
**** CK_END: TopDown Tree Construction for top/CoreClkxC[8] (cpu=0:00:30.0, real=0:00:30.0, mem=3595.4M)
**** CK_START: Update Database (mem=3595.4M)
53 Clock Buffers/Inverters inserted.
**** CK_END: Update Database (cpu=0:00:00.0, real=0:00:00.0, mem=3595.4M)
**** CK_START: Macro Models Generation (mem=3595.4M)
Macro model: Skew=40[410,449]ps N54 inTran=0/0ps.
**** CK_END: Macro Models Generation (cpu=0:00:00.0, real=0:00:00.0, mem=3595.4M)
SubTree No: 7
Input_Pin: (top/i_clockgate_7/i_clkgate/CK)
Output_Pin: (top/i_clockgate_7/i_clkgate/GCK)
Output_Net: (top/CoreClkxC[7])
**** CK_START: TopDown Tree Construction for top/CoreClkxC[7] (1-leaf) (mem=3595.4M)
Total 0 topdown clustering.
Trig. Edge Skew=0[223,223*] N1 B1 G1 A4(4.0) L[2,2] C2/0 score=27315 cpu=0:00:00.0 mem=3595M
**** CK_END: TopDown Tree Construction for top/CoreClkxC[7] (cpu=0:00:00.0, real=0:00:00.0, mem=3595.4M)
**** CK_START: Update Database (mem=3595.4M)
1 Clock Buffers/Inverters inserted.
**** CK_END: Update Database (cpu=0:00:00.0, real=0:00:00.0, mem=3595.4M)
**** CK_START: Macro Models Generation (mem=3595.4M)
Macro model: Skew=0[225,225]ps N2 inTran=0/0ps.
**** CK_END: Macro Models Generation (cpu=0:00:00.0, real=0:00:00.0, mem=3595.4M)
SubTree No: 8
Input_Pin: (top/i_clockgate_6/i_clkgate/CK)
Output_Pin: (top/i_clockgate_6/i_clkgate/GCK)
Output_Net: (top/CoreClkxC[6])
**** CK_START: TopDown Tree Construction for top/CoreClkxC[6] (1-leaf) (mem=3595.4M)
Total 0 topdown clustering.
Trig. Edge Skew=0[197,197*] N1 B1 G1 A3(3.0) L[2,2] C2/0 score=24645 cpu=0:00:00.0 mem=3595M
**** CK_END: TopDown Tree Construction for top/CoreClkxC[6] (cpu=0:00:00.1, real=0:00:00.0, mem=3595.4M)
**** CK_START: Update Database (mem=3595.4M)
1 Clock Buffers/Inverters inserted.
**** CK_END: Update Database (cpu=0:00:00.0, real=0:00:00.0, mem=3595.4M)
**** CK_START: Macro Models Generation (mem=3595.4M)
Macro model: Skew=0[197,197]ps N2 inTran=0/0ps.
**** CK_END: Macro Models Generation (cpu=0:00:00.0, real=0:00:00.0, mem=3595.4M)
SubTree No: 9
Input_Pin: (top/i_clockgate_5/i_clkgate/CK)
Output_Pin: (top/i_clockgate_5/i_clkgate/GCK)
Output_Net: (top/CoreClkxC[5])
**** CK_START: TopDown Tree Construction for top/CoreClkxC[5] (1871-leaf) (mem=3595.4M)
Total 3 topdown clustering.
Trig. Edge Skew=48[443,492*] N1871 B46 G1 A252(252.0) L[6,6] C2/1 score=60809 cpu=0:00:44.0 mem=3595M
**** CK_END: TopDown Tree Construction for top/CoreClkxC[5] (cpu=0:00:44.3, real=0:00:45.0, mem=3595.4M)
**** CK_START: Update Database (mem=3595.4M)
46 Clock Buffers/Inverters inserted.
**** CK_END: Update Database (cpu=0:00:00.1, real=0:00:00.0, mem=3595.4M)
**** CK_START: Macro Models Generation (mem=3595.4M)
Macro model: Skew=48[447,495]ps N47 inTran=0/0ps.
**** CK_END: Macro Models Generation (cpu=0:00:00.1, real=0:00:00.0, mem=3595.4M)
SubTree No: 10
Input_Pin: (top/i_clockgate_4/i_clkgate/CK)
Output_Pin: (top/i_clockgate_4/i_clkgate/GCK)
Output_Net: (top/CoreClkxC[4])
**** CK_START: TopDown Tree Construction for top/CoreClkxC[4] (1607-leaf) (mem=3595.4M)
Total 3 topdown clustering.
Trig. Edge Skew=44[437,481*] N1607 B37 G1 A322(322.0) L[6,6] C3/1 score=58334 cpu=0:00:40.0 mem=3595M
**** CK_END: TopDown Tree Construction for top/CoreClkxC[4] (cpu=0:00:40.4, real=0:00:40.0, mem=3595.4M)
**** CK_START: Update Database (mem=3595.4M)
37 Clock Buffers/Inverters inserted.
**** CK_END: Update Database (cpu=0:00:00.0, real=0:00:00.0, mem=3595.4M)
**** CK_START: Macro Models Generation (mem=3595.4M)
Macro model: Skew=44[441,485]ps N38 inTran=0/0ps.
**** CK_END: Macro Models Generation (cpu=0:00:00.1, real=0:00:00.0, mem=3595.4M)
SubTree No: 11
Input_Pin: (top/i_clockgate_3/i_clkgate/CK)
Output_Pin: (top/i_clockgate_3/i_clkgate/GCK)
Output_Net: (top/CoreClkxC[3])
**** CK_START: TopDown Tree Construction for top/CoreClkxC[3] (1547-leaf) (mem=3595.4M)
Total 3 topdown clustering.
Trig. Edge Skew=42[402,444*] N1547 B36 G1 A319(319.3) L[4,4] score=54443 cpu=0:00:35.0 mem=3595M
**** CK_END: TopDown Tree Construction for top/CoreClkxC[3] (cpu=0:00:35.5, real=0:00:36.0, mem=3595.4M)
**** CK_START: Update Database (mem=3595.4M)
36 Clock Buffers/Inverters inserted.
**** CK_END: Update Database (cpu=0:00:00.0, real=0:00:00.0, mem=3595.4M)
**** CK_START: Macro Models Generation (mem=3595.4M)
Macro model: Skew=43[400,442]ps N37 inTran=0/0ps.
**** CK_END: Macro Models Generation (cpu=0:00:00.1, real=0:00:00.0, mem=3595.4M)
SubTree No: 12
Input_Pin: (top/i_clockgate_2/i_clkgate/CK)
Output_Pin: (top/i_clockgate_2/i_clkgate/GCK)
Output_Net: (top/CoreClkxC[2])
**** CK_START: TopDown Tree Construction for top/CoreClkxC[2] (1552-leaf) (mem=3595.4M)
Total 3 topdown clustering.
Trig. Edge Skew=44[441,485*] N1552 B33 G1 A200(199.7) L[3,3] score=57447 cpu=0:00:35.0 mem=3595M
**** CK_END: TopDown Tree Construction for top/CoreClkxC[2] (cpu=0:00:35.2, real=0:00:35.0, mem=3595.4M)
**** CK_START: Update Database (mem=3595.4M)
33 Clock Buffers/Inverters inserted.
**** CK_END: Update Database (cpu=0:00:00.0, real=0:00:00.0, mem=3595.4M)
**** CK_START: Macro Models Generation (mem=3595.4M)
Macro model: Skew=44[436,480]ps N34 inTran=0/0ps.
**** CK_END: Macro Models Generation (cpu=0:00:00.1, real=0:00:00.0, mem=3595.4M)
SubTree No: 13
Input_Pin: (top/i_clockgate_1/i_clkgate/CK)
Output_Pin: (top/i_clockgate_1/i_clkgate/GCK)
Output_Net: (top/CoreClkxC[1])
**** CK_START: TopDown Tree Construction for top/CoreClkxC[1] (1291-leaf) (mem=3595.4M)
Total 3 topdown clustering.
Trig. Edge Skew=49[399,448*] N1291 B28 G1 A196(196.0) L[3,3] score=53504 cpu=0:00:31.0 mem=3595M
**** CK_END: TopDown Tree Construction for top/CoreClkxC[1] (cpu=0:00:31.4, real=0:00:32.0, mem=3595.4M)
**** CK_START: Update Database (mem=3595.4M)
28 Clock Buffers/Inverters inserted.
**** CK_END: Update Database (cpu=0:00:00.0, real=0:00:00.0, mem=3595.4M)
**** CK_START: Macro Models Generation (mem=3595.4M)
Macro model: Skew=50[400,449]ps N29 inTran=0/0ps.
**** CK_END: Macro Models Generation (cpu=0:00:00.1, real=0:00:00.0, mem=3595.4M)
SubTree No: 14
Input_Pin: (top/i_clockgate_0/i_clkgate/CK)
Output_Pin: (top/i_clockgate_0/i_clkgate/GCK)
Output_Net: (top/CoreClkxC[0])
**** CK_START: TopDown Tree Construction for top/CoreClkxC[0] (1036-leaf) (mem=3595.4M)
Total 3 topdown clustering.
Trig. Edge Skew=29[417,446*] N1036 B23 G1 A139(139.0) L[3,3] score=52875 cpu=0:00:28.0 mem=3595M
**** CK_END: TopDown Tree Construction for top/CoreClkxC[0] (cpu=0:00:28.6, real=0:00:28.0, mem=3595.4M)
**** CK_START: Update Database (mem=3595.4M)
23 Clock Buffers/Inverters inserted.
**** CK_END: Update Database (cpu=0:00:00.0, real=0:00:00.0, mem=3595.4M)
**** CK_START: Macro Models Generation (mem=3595.4M)
Macro model: Skew=29[416,445]ps N24 inTran=0/0ps.
**** CK_END: Macro Models Generation (cpu=0:00:00.0, real=0:00:00.0, mem=3595.4M)
SubTree No: 15
Input_Pin: (top/i_clkxor/i_xor/A)
Output_Pin: (top/i_clkxor/i_xor/Z)
Output_Net: (top/ClkxC)
**** CK_START: TopDown Tree Construction for top/ClkxC (2597-leaf) (15 macro model) (mem=3595.4M)
0: ckNode L0_0_CKINVM12W: loc not Legalized (1120712 306210)=>(1118800 305400) 2um
Total 5 topdown clustering.
Trig. Edge Skew=149[959,1108*] N2597 B81 G16 A367(367.3) L[3,7] C1/4 score=128917 cpu=0:01:04 mem=3595M
**** CK_END: TopDown Tree Construction for top/ClkxC (cpu=0:01:04, real=0:01:04, mem=3595.4M)
**** CK_START: Update Database (mem=3595.4M)
81 Clock Buffers/Inverters inserted.
**** CK_END: Update Database (cpu=0:00:00.0, real=0:00:00.0, mem=3595.4M)
**** CK_START: Macro Models Generation (mem=3595.4M)
Macro model: Skew=149[956,1106]ps N560 inTran=0/0ps.
**** CK_END: Macro Models Generation (cpu=0:00:00.9, real=0:00:00.0, mem=3595.4M)
SubTree No: 16
Input_Pin: (pad_Clk/PAD)
Output_Pin: (pad_Clk/DI)
Output_Net: (ClkxC)
**** CK_START: TopDown Tree Construction for ClkxC (1-leaf) (1 macro model) (mem=3595.4M)
Total 0 topdown clustering.
Trig. Edge Skew=149[2318,2467*] N1 B1 G2 A13(12.7) L[2,2] C2/0 score=253562 cpu=0:00:00.0 mem=3595M
**** CK_END: TopDown Tree Construction for ClkxC (cpu=0:00:00.1, real=0:00:01.0, mem=3595.4M)
**** CK_START: Update Database (mem=3595.4M)
1 Clock Buffers/Inverters inserted.
**** CK_END: Update Database (cpu=0:00:00.0, real=0:00:00.0, mem=3595.4M)
**** CK_START: Macro Models Generation (mem=3595.4M)
Macro model: Skew=149[2321,2470]ps N562 inTran=0/0ps.
**** CK_END: Macro Models Generation (cpu=0:00:00.9, real=0:00:01.0, mem=3595.4M)
SubTree No: 17
Input_Pin: (NULL)
Output_Pin: (ClkxCI)
Output_Net: (ClkxCI)
**** CK_START: TopDown Tree Construction for ClkxCI (1-leaf) (1 macro model) (mem=3595.4M)
Total 0 topdown clustering.
Trig. Edge Skew=149[2340,2489*] N1 B0 G2 A0(0.0) L[1,1] score=255632 cpu=0:00:00.0 mem=3595M
**** CK_END: TopDown Tree Construction for ClkxCI (cpu=0:00:00.0, real=0:00:00.0, mem=3595.4M)
**** CK_START: Update Database (mem=3595.4M)
0 Clock Buffers/Inverters inserted.
**** CK_END: Update Database (cpu=0:00:00.0, real=0:00:00.0, mem=3595.4M)
gmu_keccak_mode gmu_skein_mode ethz_blake_mode ethz_sha2_mode gmu_groestl_mode ram3_mode ethz_groestl_mode ram2_mode dummy_mode gmu_blake_mode gmu_sha2_mode ethz_keccak_mode ram1_mode ethz_skein_mode ethz_jh_mode gmu_jh_mode test_mode
Refine place movement check
============================================================
**INFO: The distance threshold for maximum refine placement move is 46.875000 microns (5% of max driving distance).
***** Start Refine Placement.....
Starting refinePlace ...
move report: placeLevelShifters moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Spread Effort: high, pre-route mode.
Finished Phase I. CPU Time = 0:00:50.0, Real Time = 0:00:50.0
move report: preRPlace moves 4286 insts, mean move: 1.76 um, max move: 25.60 um
max move on inst (top/CoreClkxC_13___L3_I9): (1121.00, 1437.60) --> (1139.40, 1430.40)
move report: rPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: overall moves 4286 insts, mean move: 1.76 um, max move: 25.60 um
max move on inst (top/CoreClkxC_13___L3_I9): (1121.00, 1437.60) --> (1139.40, 1430.40)
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 25.60 um
inst (top/CoreClkxC_13___L3_I9) with max move: (1121, 1437.6) -> (1139.4, 1430.4)
mean (X+Y) = 1.76 um
Total instances moved : 4286
*** cpu=0:00:52.3 mem=3221.5M mem(used)=0.0M***
***** Refine Placement Finished (CPU Time: 0:00:54.3 MEM: 3221.473M)
**INFO: Total instances moved beyond threshold limit during refinePlace are 0...
Refine place movement check finished, CPU=0:00:56.2
============================================================
All-RC-Corners-Per-Net-In-Memory is turned ON...
# Analysis View: dummy_slow_view
********** Clock ClkxCI Pre-Route Timing Analysis **********
Nr. of Subtrees : 18
Nr. of Sinks : 21199
Nr. of Buffer : 545
Nr. of Level (including gates) : 11
Root Rise Input Tran : 0.1(ps)
Root Fall Input Tran : 0.1(ps)
Max trig. edge delay at sink(R): top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_350_/CK 2502.6(ps)
Min trig. edge delay at sink(R): top/i_gmu_sha2/datapathInst_dc/wires_reg_15__10_/CK 2362.9(ps)
(Actual) (Required)
Rise Phase Delay : 2362.9~2502.6(ps) 0~1000(ps)
Fall Phase Delay : 2382.1~2545.2(ps) 0~1000(ps)
Trig. Edge Skew : 139.7(ps) 250(ps)
Rise Skew : 139.7(ps)
Fall Skew : 163.1(ps)
Max. Rise Buffer Tran. : 225.7(ps) 250(ps)
Max. Fall Buffer Tran. : 234.8(ps) 250(ps)
Max. Rise Sink Tran. : 185.6(ps) 350(ps)
Max. Fall Sink Tran. : 187.7(ps) 350(ps)
Min. Rise Buffer Tran. : 13.8(ps) 0(ps)
Min. Fall Buffer Tran. : 13.3(ps) 0(ps)
Min. Rise Sink Tran. : 61(ps) 0(ps)
Min. Fall Sink Tran. : 61.8(ps) 0(ps)
view dummy_slow_view : skew = 139.7ps (required = 250ps)
view ethz_blake_slow_view : skew = 139.7ps (required = 250ps)
view ethz_groestl_slow_view : skew = 139.7ps (required = 250ps)
view ethz_jh_slow_view : skew = 139.7ps (required = 250ps)
view ethz_keccak_slow_view : skew = 139.7ps (required = 250ps)
view ethz_sha2_slow_view : skew = 139.7ps (required = 250ps)
view ethz_skein_slow_view : skew = 139.7ps (required = 250ps)
view gmu_blake_slow_view : skew = 139.7ps (required = 250ps)
view gmu_groestl_slow_view : skew = 139.7ps (required = 250ps)
view gmu_jh_slow_view : skew = 139.7ps (required = 250ps)
view gmu_keccak_slow_view : skew = 139.7ps (required = 250ps)
view gmu_sha2_slow_view : skew = 139.7ps (required = 250ps)
view gmu_skein_slow_view : skew = 139.7ps (required = 250ps)
view ram1_slow_view : skew = 139.7ps (required = 250ps)
view ram2_slow_view : skew = 139.7ps (required = 250ps)
view ram3_slow_view : skew = 139.7ps (required = 250ps)
view test_slow_view : skew = 139.7ps (required = 250ps)
view hold_fast_view : skew = 96.1ps (required = 250ps)
Clock Analysis (CPU Time 0:00:15.3)
All-RC-Corners-Per-Net-In-Memory is turned OFF...
Enabling 8 Threads ...
Multi-cpu acceleration using 8 CPU(s).
Switching to the default view 'dummy_slow_view'...
*** Look For Reconvergent Clock Component ***
The clock tree ClkxCI has no reconvergent cell.
Reducing the latency of clock tree 'ClkxCI' in 'dummy_slow_view' view ...
Calculating pre-route downstream delay for clock tree 'ClkxCI'...
*** Look For PreservePin And Optimized CrossOver Root Pin ***
moving 'top/ClkxC__L2_I1' from (747600 784200) to (775000 849000)
moving 'top/ClkxC__L2_I4' from (1349400 805800) to (1224400 859800)
moving 'top/CoreClkxC_10___L3_I2' from (401200 415200) to (413000 451200)
moving 'top/CoreClkxC_12___L4_I0' from (1573600 1138800) to (1538000 1137000)
moving 'top/ClkxC__L2_I6' from (1364800 805800) to (1331600 818400)
inserting cloning top/CoreClkxC_10___I0(CKBUFM48W) loc=(530200 487200) of the inst top/CoreClkxC_10___L2_I0
moving 'top/ClkxC__L2_I6' from (1331600 818400) to (1215400 863400)
moving 'top/ClkxC__L2_I6' from (1215400 863400) to (1216600 903000)
inserting cloning top/CoreClkxC_10___I1(CKBUFM48W) loc=(530200 487200) of the inst top/CoreClkxC_10___I0
moving 'top/ClkxC__L2_I5' from (1364400 802200) to (1298000 829200)
inserting cloning top/CoreClkxC_10___I2(CKINVM48W) loc=(413000 451200) of the inst top/CoreClkxC_10___L3_I2
moving 'top/ClkxC__L2_I4' from (1224400 859800) to (1221000 841800)
moving 'top/ClkxC__L2_I6' from (1216600 903000) to (1187200 904800)
inserting cloning top/CoreClkxC_12___I3(CKINVM48W) loc=(1432800 1131600) of the inst top/CoreClkxC_12___L3_I0
moving 'top/ClkxC__L2_I4' from (1221000 841800) to (1190600 858000)
moving 'top/CoreClkxC_10___L3_I3' from (548000 539400) to (554400 517800)
moving 'top/CoreClkxC_10___L3_I4' from (548000 541200) to (531400 512400)
moving 'top/CoreClkxC_10___L3_I0' from (389400 415200) to (408600 400800)
moving 'top/CoreClkxC_10___L4_I20' from (740400 701400) to (731800 681600)
moving 'top/CoreClkxC_10___L4_I8' from (341200 699600) to (357800 690600)
moving 'top/ClkxC__L2_I4' from (1190600 858000) to (1185400 841800)
moving 'top/CoreClkxC_10___L4_I8' from (357800 690600) to (370200 670800)
moving 'top/CoreClkxC_10___L3_I3' from (554400 517800) to (573600 532200)
MaxTriggerDelay: 2428.5 (ps)
MinTriggerDelay: 2354.7 (ps)
Skew: 73.8 (ps)
*** Finished Latency Reduction ((cpu=1:42:55 real=1:54:19 mem=3221.5M) ***
Reducing the skew of clock tree 'ClkxCI' in 'dummy_slow_view' view ...
MaxTriggerDelay: 2428.5 (ps)
MinTriggerDelay: 2354.7 (ps)
Skew: 73.8 (ps)
*** Finished Skew Reduction ((cpu=0:00:00.0 real=0:00:00.0 mem=3221.5M) ***
Resized (CKBUFM32W->CKBUFM26WA): top/CoreClkxC_5___L2_I0
Resized (CKINVM32W->CKINVM40W): top/CoreClkxC_5___L3_I0
Resized (CKINVM22WA->CKINVM24W): top/CoreClkxC_5___L5_I31
Resized (CKINVM22WA->CKINVM24W): top/CoreClkxC_5___L5_I33
Resized (CKBUFM40W->CKBUFM48W): top/ClkxC__L2_I0
Resized (CKBUFM40W->CKBUFM48W): top/ClkxC__L2_I1
Resized (CKBUFM40W->CKBUFM48W): top/ClkxC__L2_I3
Resized (CKBUFM40W->CKBUFM48W): top/ClkxC__L2_I4
Resized (CKBUFM40W->CKBUFM48W): top/ClkxC__L2_I5
Resized (CKBUFM40W->CKBUFM48W): top/ClkxC__L2_I6
Resized (CKINVM8W->CKINVM12W): top/ClkxC__L4_I3
Resized (CKINVM8W->CKINVM12W): top/ClkxC__L4_I4
Resized (CKINVM8W->CKINVM12W): top/ClkxC__L4_I5
Resized (CKBUFM20W->CKBUFM22WA): top/CoreClkxC_2___L2_I10
Resized (CKBUFM20W->CKBUFM22WA): top/CoreClkxC_2___L2_I14
Resized (CKBUFM20W->CKBUFM22WA): top/CoreClkxC_2___L2_I19
Resized (CKBUFM20W->CKBUFM22WA): top/CoreClkxC_2___L2_I21
Resized (CKBUFM32W->CKBUFM48W): top/CoreClkxC_13___L3_I16
Resized (CKBUFM26WA->CKBUFM32W): top/CoreClkxC_12___L2_I0
Resized (CKINVM40W->CKINVM48W): top/CoreClkxC_12___L4_I0
Resized (CKINVM40W->CKINVM48W): top/CoreClkxC_12___L4_I1
Resized (CKINVM40W->CKINVM48W): top/CoreClkxC_12___L4_I3
Resized (CKINVM20W->CKINVM22WA): top/CoreClkxC_12___L5_I9
Resized (CKINVM20W->CKINVM22WA): top/CoreClkxC_12___L5_I19
Resized (CKINVM20W->CKINVM22WA): top/CoreClkxC_12___L5_I21
Resized (CKINVM20W->CKINVM24W): top/CoreClkxC_12___L5_I26
Resized (CKINVM20W->CKINVM22WA): top/CoreClkxC_12___L5_I30
Resized (CKINVM26WA->CKINVM32W): top/CoreClkxC_10___L4_I5
Resized (CKINVM26WA->CKINVM40W): top/CoreClkxC_10___L4_I8
Resized (CKINVM26WA->CKINVM32W): top/CoreClkxC_10___L4_I11
Resized (CKINVM26WA->CKINVM32W): top/CoreClkxC_10___L4_I13
Resized (CKINVM26WA->CKINVM48W): top/CoreClkxC_10___L4_I20
Resized (CKINVM26WA->CKINVM32W): top/CoreClkxC_10___L4_I27
Resized (CKINVM26WA->CKINVM32W): top/CoreClkxC_10___L4_I28
Resized (CKBUFM32W->CKBUFM26WA): top/CoreClkxC_9___L1_I0
Resized (CKBUFM20W->CKBUFM24W): top/CoreClkxC_9___L2_I10
Resized (CKBUFM20W->CKBUFM22WA): top/CoreClkxC_9___L2_I12
Resized (CKBUFM20W->CKBUFM24W): top/CoreClkxC_9___L2_I15
Resized (CKBUFM20W->CKBUFM24W): top/CoreClkxC_9___L2_I18
Resized (CKBUFM20W->CKBUFM22WA): top/CoreClkxC_9___L2_I27
Inserted cell (CKBUFM48W): top/CoreClkxC_10___I0
Inserted cell (CKBUFM48W): top/CoreClkxC_10___I1
Inserted cell (CKINVM48W): top/CoreClkxC_10___I2
Inserted cell (CKINVM48W): top/CoreClkxC_12___I3
resized 40 standard cell(s).
inserted 4 standard cell(s).
deleted 0 standard cell(s).
moved 19 standard cell(s).
*** Optimized Clock Tree Latency (cpu=1:42:55 real=1:54:19 mem=3221.5M) ***
Doing the final refine placement ...
***** Start Refine Placement.....
Starting refinePlace ...
move report: placeLevelShifters moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Spread Effort: high, pre-route mode.
Finished Phase I. CPU Time = 0:00:26.8, Real Time = 0:00:27.0
move report: preRPlace moves 280 insts, mean move: 1.03 um, max move: 6.80 um
max move on inst (top/i_gmu_groestl/U13140): (533.60, 485.40) --> (540.40, 485.40)
move report: rPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: overall moves 280 insts, mean move: 1.03 um, max move: 6.80 um
max move on inst (top/i_gmu_groestl/U13140): (533.60, 485.40) --> (540.40, 485.40)
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 6.80 um
inst (top/i_gmu_groestl/U13140) with max move: (533.6, 485.4) -> (540.4, 485.4)
mean (X+Y) = 1.03 um
Total instances moved : 280
*** cpu=0:00:29.2 mem=3221.5M mem(used)=0.0M***
***** Refine Placement Finished (CPU Time: 0:00:33.8 MEM: 3221.473M)
All-RC-Corners-Per-Net-In-Memory is turned ON...
# Analysis View: dummy_slow_view
********** Clock ClkxCI Pre-Route Timing Analysis **********
Nr. of Subtrees : 18
Nr. of Sinks : 21199
Nr. of Buffer : 549
Nr. of Level (including gates) : 11
Root Rise Input Tran : 0.1(ps)
Root Fall Input Tran : 0.1(ps)
Max trig. edge delay at sink(R): top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_306_/CK 2430(ps)
Min trig. edge delay at sink(R): top/i_gmu_sha2/datapathInst_dc/wires_reg_15__10_/CK 2355(ps)
(Actual) (Required)
Rise Phase Delay : 2355~2430(ps) 0~1000(ps)
Fall Phase Delay : 2375.2~2474(ps) 0~1000(ps)
Trig. Edge Skew : 75(ps) 250(ps)
Rise Skew : 75(ps)
Fall Skew : 98.8(ps)
Max. Rise Buffer Tran. : 231.2(ps) 250(ps)
Max. Fall Buffer Tran. : 241.6(ps) 250(ps)
Max. Rise Sink Tran. : 185.7(ps) 350(ps)
Max. Fall Sink Tran. : 187.7(ps) 350(ps)
Min. Rise Buffer Tran. : 13.8(ps) 0(ps)
Min. Fall Buffer Tran. : 13.4(ps) 0(ps)
Min. Rise Sink Tran. : 61(ps) 0(ps)
Min. Fall Sink Tran. : 61.8(ps) 0(ps)
view dummy_slow_view : skew = 75ps (required = 250ps)
view ethz_blake_slow_view : skew = 75ps (required = 250ps)
view ethz_groestl_slow_view : skew = 75ps (required = 250ps)
view ethz_jh_slow_view : skew = 75ps (required = 250ps)
view ethz_keccak_slow_view : skew = 75ps (required = 250ps)
view ethz_sha2_slow_view : skew = 75ps (required = 250ps)
view ethz_skein_slow_view : skew = 75ps (required = 250ps)
view gmu_blake_slow_view : skew = 75ps (required = 250ps)
view gmu_groestl_slow_view : skew = 75ps (required = 250ps)
view gmu_jh_slow_view : skew = 75ps (required = 250ps)
view gmu_keccak_slow_view : skew = 75ps (required = 250ps)
view gmu_sha2_slow_view : skew = 75ps (required = 250ps)
view gmu_skein_slow_view : skew = 75ps (required = 250ps)
view ram1_slow_view : skew = 75ps (required = 250ps)
view ram2_slow_view : skew = 75ps (required = 250ps)
view ram3_slow_view : skew = 75ps (required = 250ps)
view test_slow_view : skew = 75ps (required = 250ps)
view hold_fast_view : skew = 68.8ps (required = 250ps)
Generating Clock Analysis Report timingReports_final/clock.report ....
Clock Analysis (CPU Time 0:00:13.0)
All-RC-Corners-Per-Net-In-Memory is turned OFF...
*** ckSynthesis Opt Latency (cpu=1:43:57 real=1:55:22 mem=3221.5M) ***
***** Start Refine Placement.....
Starting refinePlace ...
move report: placeLevelShifters moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Spread Effort: high, pre-route mode.
Finished Phase I. CPU Time = 0:00:24.6, Real Time = 0:00:24.0
move report: preRPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: rPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: overall moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 0.00 um
mean (X+Y) = 0.00 um
Total instances moved : 0
*** cpu=0:00:26.9 mem=3221.5M mem(used)=0.0M***
***** Refine Placement Finished (CPU Time: 0:00:31.0 MEM: 3221.473M)
All-RC-Corners-Per-Net-In-Memory is turned ON...
# Analysis View: dummy_slow_view
********** Clock ClkxCI Pre-Route Timing Analysis **********
Nr. of Subtrees : 18
Nr. of Sinks : 21199
Nr. of Buffer : 549
Nr. of Level (including gates) : 11
Root Rise Input Tran : 0.1(ps)
Root Fall Input Tran : 0.1(ps)
Max trig. edge delay at sink(R): top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_306_/CK 2430(ps)
Min trig. edge delay at sink(R): top/i_gmu_sha2/datapathInst_dc/wires_reg_15__10_/CK 2355(ps)
(Actual) (Required)
Rise Phase Delay : 2355~2430(ps) 0~1000(ps)
Fall Phase Delay : 2375.2~2474(ps) 0~1000(ps)
Trig. Edge Skew : 75(ps) 250(ps)
Rise Skew : 75(ps)
Fall Skew : 98.8(ps)
Max. Rise Buffer Tran. : 231.2(ps) 250(ps)
Max. Fall Buffer Tran. : 241.6(ps) 250(ps)
Max. Rise Sink Tran. : 185.7(ps) 350(ps)
Max. Fall Sink Tran. : 187.7(ps) 350(ps)
Min. Rise Buffer Tran. : 13.8(ps) 0(ps)
Min. Fall Buffer Tran. : 13.4(ps) 0(ps)
Min. Rise Sink Tran. : 61(ps) 0(ps)
Min. Fall Sink Tran. : 61.8(ps) 0(ps)
view dummy_slow_view : skew = 75ps (required = 250ps)
view ethz_blake_slow_view : skew = 75ps (required = 250ps)
view ethz_groestl_slow_view : skew = 75ps (required = 250ps)
view ethz_jh_slow_view : skew = 75ps (required = 250ps)
view ethz_keccak_slow_view : skew = 75ps (required = 250ps)
view ethz_sha2_slow_view : skew = 75ps (required = 250ps)
view ethz_skein_slow_view : skew = 75ps (required = 250ps)
view gmu_blake_slow_view : skew = 75ps (required = 250ps)
view gmu_groestl_slow_view : skew = 75ps (required = 250ps)
view gmu_jh_slow_view : skew = 75ps (required = 250ps)
view gmu_keccak_slow_view : skew = 75ps (required = 250ps)
view gmu_sha2_slow_view : skew = 75ps (required = 250ps)
view gmu_skein_slow_view : skew = 75ps (required = 250ps)
view ram1_slow_view : skew = 75ps (required = 250ps)
view ram2_slow_view : skew = 75ps (required = 250ps)
view ram3_slow_view : skew = 75ps (required = 250ps)
view test_slow_view : skew = 75ps (required = 250ps)
view hold_fast_view : skew = 68.8ps (required = 250ps)
Clock Analysis (CPU Time 0:00:12.7)
All-RC-Corners-Per-Net-In-Memory is turned OFF...
globalDetailRoute
#Start globalDetailRoute on Thu Sep 29 20:01:39 2011
#
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 3221.00 (Mb)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_0 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_1 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_2 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_3 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_4 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_5 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_6 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_7 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_8 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_9 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_10 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_11 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_12 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_13 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_14 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_15 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_16 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_17 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_18 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34 Repeated 20 times. Will be suppressed.) Power/Ground pin VSSIO of instance fillperi_N_19 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (EMS-27) Message (NRIG-34) has exceeded the current message display limit of 20.
#To increase the message display limit, refer to the product command reference manual.
#WARNING (NRDB-733) PIN AlgSelxSI[0] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN AlgSelxSI[1] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN AlgSelxSI[2] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN AlgSelxSI[3] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN ClkDxCI in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN ClkxCI in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN CoreScanEnxTI in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN CoreScanInxTI in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[0] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[10] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[11] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[12] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[13] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[14] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[15] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[1] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[2] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[3] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[4] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733 Repeated 20 times. Will be suppressed.) PIN DataOutxDO[5] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (EMS-27) Message (NRDB-733) has exceeded the current message display limit of 20.
#To increase the message display limit, refer to the product command reference manual.
#NanoRoute Version v10.12-s010 NR110720-1815/10_10_USR2-UB
#Using multithreading with 8 threads.
# ME1 H Track-Pitch = 0.200 Line-2-Via Pitch = 0.185
# ME2 V Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME3 H Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME4 V Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME5 H Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME6 V Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME7 H Track-Pitch = 0.400 Line-2-Via Pitch = 0.400
# ME8 V Track-Pitch = 4.000 Line-2-Via Pitch = 4.000
#Merging special wires using 8 threads...
#reading routing guides ......
#Number of eco nets is 0
#
#Start data preparation...
#Force regenerating Ggrids.
#Auto generating G-grids with size=15 tracks, using layer ME2's pitch = 0.200.
#Using automatically generated G-grids.
#
#Data preparation is done on Thu Sep 29 20:02:36 2011
#
#Analyzing routing resource...
#Routing resource analysis is done on Thu Sep 29 20:02:39 2011
#
# Resource Analysis:
#
# Routing #Avail #Track #Total %Gcell
# Layer Direction Track Blocked Gcell Blocked
# --------------------------------------------------------------
# Metal 1 H 5808 3565 391250 74.46%
# Metal 2 V 5718 3657 391250 43.74%
# Metal 3 H 5885 3489 391250 36.36%
# Metal 4 V 5858 3516 391250 42.89%
# Metal 5 H 7164 2209 391250 22.09%
# Metal 6 V 7101 2273 391250 29.79%
# Metal 7 H 2749 1937 391250 24.29%
# Metal 8 V 239 228 391250 61.74%
# --------------------------------------------------------------
# Total 40525 36.22% 3130000 41.92%
#
# 567 nets (0.20%) with 1 preferred extra spacing.
#
#
#Routing guide is on.
#cpu time = 00:00:06, elapsed time = 00:00:06, memory = 3699.00 (Mb)
#
#start global routing iteration 1...
#cpu time = 00:00:06, elapsed time = 00:00:06, memory = 3726.00 (Mb)
#
#start global routing iteration 2...
#cpu time = 00:00:06, elapsed time = 00:00:06, memory = 3728.00 (Mb)
#
#start global routing iteration 3...
#cpu time = 00:00:05, elapsed time = 00:00:05, memory = 3728.00 (Mb)
#
#
# Congestion Analysis: (blocked Gcells are excluded)
#
# OverCon OverCon OverCon
# #Gcell #Gcell #Gcell %Gcell
# Layer (1) (2) (3) OverCon
# ------------------------------------------------------------
# Metal 1 0(0.00%) 0(0.00%) 0(0.00%) (0.00%)
# Metal 2 2145(0.87%) 304(0.12%) 5(0.00%) (0.99%)
# Metal 3 0(0.00%) 0(0.00%) 0(0.00%) (0.00%)
# Metal 4 846(0.34%) 119(0.05%) 0(0.00%) (0.38%)
# Metal 5 0(0.00%) 0(0.00%) 0(0.00%) (0.00%)
# Metal 6 111(0.04%) 1(0.00%) 0(0.00%) (0.04%)
# Metal 7 0(0.00%) 0(0.00%) 0(0.00%) (0.00%)
# Metal 8 0(0.00%) 0(0.00%) 0(0.00%) (0.00%)
# ------------------------------------------------------------
# Total 3102(0.16%) 424(0.02%) 5(0.00%) (0.18%)
#
# The worst congested Gcell overcon (routing demand over resource in number of tracks) = 3
#
#Complete Global Routing.
#Total number of nets with non-default rule or having extra spacing = 567
#Total wire length = 181484 um.
#Total half perimeter of net bounding box = 92498 um.
#Total wire length on LAYER ME1 = 0 um.
#Total wire length on LAYER ME2 = 3083 um.
#Total wire length on LAYER ME3 = 98359 um.
#Total wire length on LAYER ME4 = 79271 um.
#Total wire length on LAYER ME5 = 113 um.
#Total wire length on LAYER ME6 = 645 um.
#Total wire length on LAYER ME7 = 12 um.
#Total wire length on LAYER ME8 = 0 um.
#Total number of vias = 61525
#Up-Via Summary (total 61525):
#
#-----------------------
# Metal 1 21119
# Metal 2 20950
# Metal 3 19336
# Metal 4 63
# Metal 5 53
# Metal 6 4
#-----------------------
# 61525
#
#Max overcon = 3 tracks.
#Total overcon = 0.18%.
#Worst layer Gcell overcon rate = 0.38%.
#Cpu time = 00:01:10
#Elapsed time = 00:01:10
#Increased memory = 156.00 (Mb)
#Total memory = 3676.00 (Mb)
#Peak memory = 4184.00 (Mb)
#Using multithreading with 8 threads.
#
#Start Detail Routing...
#start initial detail routing ...
# completing 10% with 111 violations
# elapsed time = 00:00:17, memory = 3870.00 (Mb)
# completing 20% with 139 violations
# elapsed time = 00:00:31, memory = 3820.00 (Mb)
# completing 30% with 129 violations
# elapsed time = 00:00:43, memory = 3815.00 (Mb)
# completing 40% with 165 violations
# elapsed time = 00:01:00, memory = 3844.00 (Mb)
# completing 50% with 166 violations
# elapsed time = 00:01:17, memory = 3836.00 (Mb)
# completing 60% with 165 violations
# elapsed time = 00:01:27, memory = 3869.00 (Mb)
# completing 70% with 143 violations
# elapsed time = 00:01:45, memory = 3846.00 (Mb)
# completing 80% with 135 violations
# elapsed time = 00:02:02, memory = 3855.00 (Mb)
# completing 90% with 101 violations
# elapsed time = 00:02:13, memory = 3869.00 (Mb)
# completing 100% with 8 violations
# elapsed time = 00:02:31, memory = 3756.00 (Mb)
# ECO: 1.3% of the total area was rechecked for DRC, and 39.8% required routing.
# number of violations = 8
#cpu time = 00:09:33, elapsed time = 00:02:31, memory = 3706.00 (Mb)
#start 1st optimization iteration ...
# number of violations = 8
#cpu time = 00:00:01, elapsed time = 00:00:01, memory = 3706.00 (Mb)
#start 2nd optimization iteration ...
# number of violations = 8
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 3706.00 (Mb)
#start 3rd optimization iteration ...
# number of violations = 8
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 3706.00 (Mb)
#start 4th optimization iteration ...
# number of violations = 8
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 3706.00 (Mb)
#start 5th optimization iteration ...
# number of violations = 8
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 3706.00 (Mb)
#Complete Detail Routing.
#Total number of nets with non-default rule or having extra spacing = 567
#Total wire length = 183655 um.
#Total half perimeter of net bounding box = 92498 um.
#Total wire length on LAYER ME1 = 275 um.
#Total wire length on LAYER ME2 = 3758 um.
#Total wire length on LAYER ME3 = 95973 um.
#Total wire length on LAYER ME4 = 83607 um.
#Total wire length on LAYER ME5 = 1 um.
#Total wire length on LAYER ME6 = 42 um.
#Total wire length on LAYER ME7 = 0 um.
#Total wire length on LAYER ME8 = 0 um.
#Total number of vias = 70495
#Up-Via Summary (total 70495):
#
#-----------------------
# Metal 1 22337
# Metal 2 21908
# Metal 3 26230
# Metal 4 10
# Metal 5 10
#-----------------------
# 70495
#
#Total number of DRC violations = 8
#Total number of violations on LAYER ME1 = 0
#Total number of violations on LAYER ME2 = 0
#Total number of violations on LAYER ME3 = 0
#Total number of violations on LAYER ME4 = 8
#Total number of violations on LAYER ME5 = 0
#Total number of violations on LAYER ME6 = 0
#Total number of violations on LAYER ME7 = 0
#Total number of violations on LAYER ME8 = 0
#Cpu time = 00:09:39
#Elapsed time = 00:02:36
#Increased memory = 22.00 (Mb)
#Total memory = 3698.00 (Mb)
#Peak memory = 4184.00 (Mb)
#detailRoute Statistics:
#Cpu time = 00:09:39
#Elapsed time = 00:02:36
#Increased memory = 22.00 (Mb)
#Total memory = 3698.00 (Mb)
#Peak memory = 4184.00 (Mb)
#
#globalDetailRoute statistics:
#Cpu time = 00:11:01
#Elapsed time = 00:03:57
#Increased memory = 323.00 (Mb)
#Total memory = 3544.00 (Mb)
#Peak memory = 4184.00 (Mb)
#Number of warnings = 42
#Total number of warnings = 42
#Number of fails = 0
#Total number of fails = 0
#Complete globalDetailRoute on Thu Sep 29 20:05:36 2011
#
There are 8 violation left....
globalDetailRoute
#Start globalDetailRoute on Thu Sep 29 20:05:36 2011
#
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
#NanoRoute Version v10.12-s010 NR110720-1815/10_10_USR2-UB
#Using multithreading with 8 threads.
# ME1 H Track-Pitch = 0.200 Line-2-Via Pitch = 0.185
# ME2 V Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME3 H Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME4 V Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME5 H Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME6 V Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME7 H Track-Pitch = 0.400 Line-2-Via Pitch = 0.400
# ME8 V Track-Pitch = 4.000 Line-2-Via Pitch = 4.000
#Merging special wires using 8 threads...
#Number of eco nets is 0
#
#Start data preparation...
#Force regenerating Ggrids.
#Auto generating G-grids with size=15 tracks, using layer ME2's pitch = 0.200.
#Using automatically generated G-grids.
#
#Data preparation is done on Thu Sep 29 20:05:54 2011
#
#Analyzing routing resource...
#Routing resource analysis is done on Thu Sep 29 20:05:58 2011
#
# Resource Analysis:
#
# Routing #Avail #Track #Total %Gcell
# Layer Direction Track Blocked Gcell Blocked
# --------------------------------------------------------------
# Metal 1 H 5808 3565 391250 74.46%
# Metal 2 V 5718 3657 391250 43.74%
# Metal 3 H 5885 3489 391250 36.36%
# Metal 4 V 5858 3516 391250 42.89%
# Metal 5 H 7164 2209 391250 22.09%
# Metal 6 V 7101 2273 391250 29.79%
# Metal 7 H 2749 1937 391250 24.29%
# Metal 8 V 239 228 391250 61.74%
# --------------------------------------------------------------
# Total 40525 36.22% 3130000 41.92%
#
# 567 nets (0.20%) with 1 preferred extra spacing.
#
#
#cpu time = 00:00:06, elapsed time = 00:00:06, memory = 3724.00 (Mb)
#
#start global routing iteration 1...
#cpu time = 00:00:09, elapsed time = 00:00:02, memory = 3724.00 (Mb)
#
#start global routing iteration 2...
#cpu time = 00:00:01, elapsed time = 00:00:01, memory = 3732.00 (Mb)
#
#start global routing iteration 3...
#cpu time = 00:00:06, elapsed time = 00:00:02, memory = 3724.00 (Mb)
#
#
# Congestion Analysis: (blocked Gcells are excluded)
#
# OverCon
# #Gcell %Gcell
# Layer (1) OverCon
# --------------------------------
# Metal 1 0(0.00%) (0.00%)
# Metal 2 0(0.00%) (0.00%)
# Metal 3 0(0.00%) (0.00%)
# Metal 4 0(0.00%) (0.00%)
# Metal 5 0(0.00%) (0.00%)
# Metal 6 0(0.00%) (0.00%)
# Metal 7 0(0.00%) (0.00%)
# Metal 8 0(0.00%) (0.00%)
# --------------------------------
# Total 0(0.00%) (0.00%)
#
# The worst congested Gcell overcon (routing demand over resource in number of tracks) = 1
#
#Complete Global Routing.
#Total number of nets with non-default rule or having extra spacing = 567
#Total wire length = 183657 um.
#Total half perimeter of net bounding box = 92498 um.
#Total wire length on LAYER ME1 = 275 um.
#Total wire length on LAYER ME2 = 3758 um.
#Total wire length on LAYER ME3 = 95969 um.
#Total wire length on LAYER ME4 = 83612 um.
#Total wire length on LAYER ME5 = 1 um.
#Total wire length on LAYER ME6 = 42 um.
#Total wire length on LAYER ME7 = 0 um.
#Total wire length on LAYER ME8 = 0 um.
#Total number of vias = 70495
#Up-Via Summary (total 70495):
#
#-----------------------
# Metal 1 22337
# Metal 2 21908
# Metal 3 26230
# Metal 4 10
# Metal 5 10
#-----------------------
# 70495
#
#Max overcon = 0 track.
#Total overcon = 0.00%.
#Worst layer Gcell overcon rate = 0.00%.
#Cpu time = 00:00:34
#Elapsed time = 00:00:23
#Increased memory = 13.00 (Mb)
#Total memory = 3676.00 (Mb)
#Peak memory = 4184.00 (Mb)
#Using multithreading with 8 threads.
#
#Start Detail Routing...
#start initial detail routing ...
# completing 10% with 0 violations
# elapsed time = 00:00:00, memory = 3741.00 (Mb)
# completing 20% with 0 violations
# elapsed time = 00:00:01, memory = 3741.00 (Mb)
# completing 30% with 0 violations
# elapsed time = 00:00:01, memory = 3741.00 (Mb)
# completing 40% with 0 violations
# elapsed time = 00:00:01, memory = 3741.00 (Mb)
# completing 50% with 0 violations
# elapsed time = 00:00:01, memory = 3741.00 (Mb)
# completing 60% with 0 violations
# elapsed time = 00:00:02, memory = 3741.00 (Mb)
# completing 70% with 0 violations
# elapsed time = 00:00:02, memory = 3741.00 (Mb)
# completing 80% with 0 violations
# elapsed time = 00:00:02, memory = 3741.00 (Mb)
# completing 90% with 3 violations
# elapsed time = 00:00:02, memory = 3742.00 (Mb)
# completing 100% with 8 violations
# elapsed time = 00:00:03, memory = 3743.00 (Mb)
# ECO: 0.0% of the total area was rechecked for DRC, and 0.1% required routing.
# number of violations = 8
#cpu time = 00:00:07, elapsed time = 00:00:03, memory = 3693.00 (Mb)
#start 1st optimization iteration ...
# number of violations = 8
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 3693.00 (Mb)
#start 2nd optimization iteration ...
# number of violations = 8
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 3693.00 (Mb)
#start 3rd optimization iteration ...
# number of violations = 8
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 3693.00 (Mb)
#start 4th optimization iteration ...
# number of violations = 8
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 3693.00 (Mb)
#start 5th optimization iteration ...
# number of violations = 8
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 3693.00 (Mb)
#Complete Detail Routing.
#Total number of nets with non-default rule or having extra spacing = 567
#Total wire length = 183655 um.
#Total half perimeter of net bounding box = 92498 um.
#Total wire length on LAYER ME1 = 275 um.
#Total wire length on LAYER ME2 = 3758 um.
#Total wire length on LAYER ME3 = 95973 um.
#Total wire length on LAYER ME4 = 83607 um.
#Total wire length on LAYER ME5 = 1 um.
#Total wire length on LAYER ME6 = 42 um.
#Total wire length on LAYER ME7 = 0 um.
#Total wire length on LAYER ME8 = 0 um.
#Total number of vias = 70495
#Up-Via Summary (total 70495):
#
#-----------------------
# Metal 1 22337
# Metal 2 21908
# Metal 3 26230
# Metal 4 10
# Metal 5 10
#-----------------------
# 70495
#
#Total number of DRC violations = 8
#Total number of violations on LAYER ME1 = 0
#Total number of violations on LAYER ME2 = 0
#Total number of violations on LAYER ME3 = 0
#Total number of violations on LAYER ME4 = 8
#Total number of violations on LAYER ME5 = 0
#Total number of violations on LAYER ME6 = 0
#Total number of violations on LAYER ME7 = 0
#Total number of violations on LAYER ME8 = 0
#Cpu time = 00:00:12
#Elapsed time = 00:00:07
#Increased memory = 0.00 (Mb)
#Total memory = 3676.00 (Mb)
#Peak memory = 4184.00 (Mb)
#detailRoute Statistics:
#Cpu time = 00:00:12
#Elapsed time = 00:00:07
#Increased memory = 0.00 (Mb)
#Total memory = 3676.00 (Mb)
#Peak memory = 4184.00 (Mb)
#
#globalDetailRoute statistics:
#Cpu time = 00:00:53
#Elapsed time = 00:00:37
#Increased memory = 2.00 (Mb)
#Total memory = 3546.00 (Mb)
#Peak memory = 4184.00 (Mb)
#Number of warnings = 0
#Total number of warnings = 42
#Number of fails = 0
#Total number of fails = 0
#Complete globalDetailRoute on Thu Sep 29 20:06:13 2011
#
*** Look For Un-Routed Clock Tree Net ***
Routing correlation check
============================================================
Min length threshold value is :: 40 microns
Allowed deviation from route guide is 50%
Routing correlation check finished, CPU=0:00:00.0
============================================================
All-RC-Corners-Per-Net-In-Memory is turned ON...
# Analysis View: dummy_slow_view
********** Clock ClkxCI Clk-Route-Only Timing Analysis **********
Nr. of Subtrees : 18
Nr. of Sinks : 21199
Nr. of Buffer : 549
Nr. of Level (including gates) : 11
Root Rise Input Tran : 0.1(ps)
Root Fall Input Tran : 0.1(ps)
Max trig. edge delay at sink(R): top/i_ethz_groestl/HxDP_reg_458_/CK 2378.7(ps)
Min trig. edge delay at sink(R): top/i_gmu_sha2/datapathInst_dc/wires_reg_15__10_/CK 2299.6(ps)
(Actual) (Required)
Rise Phase Delay : 2299.6~2378.7(ps) 0~1000(ps)
Fall Phase Delay : 2319.9~2414.4(ps) 0~1000(ps)
Trig. Edge Skew : 79.1(ps) 250(ps)
Rise Skew : 79.1(ps)
Fall Skew : 94.5(ps)
Max. Rise Buffer Tran. : 202.8(ps) 250(ps)
Max. Fall Buffer Tran. : 209.6(ps) 250(ps)
Max. Rise Sink Tran. : 200.2(ps) 350(ps)
Max. Fall Sink Tran. : 202.5(ps) 350(ps)
Min. Rise Buffer Tran. : 13.8(ps) 0(ps)
Min. Fall Buffer Tran. : 13.3(ps) 0(ps)
Min. Rise Sink Tran. : 62.9(ps) 0(ps)
Min. Fall Sink Tran. : 63.8(ps) 0(ps)
view dummy_slow_view : skew = 79.1ps (required = 250ps)
view ethz_blake_slow_view : skew = 79.1ps (required = 250ps)
view ethz_groestl_slow_view : skew = 79.1ps (required = 250ps)
view ethz_jh_slow_view : skew = 79.1ps (required = 250ps)
view ethz_keccak_slow_view : skew = 79.1ps (required = 250ps)
view ethz_sha2_slow_view : skew = 79.1ps (required = 250ps)
view ethz_skein_slow_view : skew = 79.1ps (required = 250ps)
view gmu_blake_slow_view : skew = 79.1ps (required = 250ps)
view gmu_groestl_slow_view : skew = 79.1ps (required = 250ps)
view gmu_jh_slow_view : skew = 79.1ps (required = 250ps)
view gmu_keccak_slow_view : skew = 79.1ps (required = 250ps)
view gmu_sha2_slow_view : skew = 79.1ps (required = 250ps)
view gmu_skein_slow_view : skew = 79.1ps (required = 250ps)
view ram1_slow_view : skew = 79.1ps (required = 250ps)
view ram2_slow_view : skew = 79.1ps (required = 250ps)
view ram3_slow_view : skew = 79.1ps (required = 250ps)
view test_slow_view : skew = 79.1ps (required = 250ps)
view hold_fast_view : skew = 46.4ps (required = 250ps)
Clock Analysis (CPU Time 0:00:05.2)
All-RC-Corners-Per-Net-In-Memory is turned OFF...
setting up for view 'dummy_slow_view'...
setting up for view 'ethz_blake_slow_view'...
setting up for view 'ethz_groestl_slow_view'...
setting up for view 'ethz_jh_slow_view'...
setting up for view 'ethz_keccak_slow_view'...
setting up for view 'ethz_sha2_slow_view'...
setting up for view 'ethz_skein_slow_view'...
setting up for view 'gmu_blake_slow_view'...
setting up for view 'gmu_groestl_slow_view'...
setting up for view 'gmu_jh_slow_view'...
setting up for view 'gmu_keccak_slow_view'...
setting up for view 'gmu_sha2_slow_view'...
setting up for view 'gmu_skein_slow_view'...
setting up for view 'ram1_slow_view'...
setting up for view 'ram2_slow_view'...
setting up for view 'ram3_slow_view'...
setting up for view 'test_slow_view'...
setting up for view 'hold_fast_view'...
View 'ethz_blake_slow_view' in clock tree 'ClkxCI' is redundant
View 'ethz_groestl_slow_view' in clock tree 'ClkxCI' is redundant
View 'ethz_jh_slow_view' in clock tree 'ClkxCI' is redundant
View 'ethz_keccak_slow_view' in clock tree 'ClkxCI' is redundant
View 'ethz_sha2_slow_view' in clock tree 'ClkxCI' is redundant
View 'ethz_skein_slow_view' in clock tree 'ClkxCI' is redundant
View 'gmu_blake_slow_view' in clock tree 'ClkxCI' is redundant
View 'gmu_groestl_slow_view' in clock tree 'ClkxCI' is redundant
View 'gmu_jh_slow_view' in clock tree 'ClkxCI' is redundant
View 'gmu_keccak_slow_view' in clock tree 'ClkxCI' is redundant
View 'gmu_sha2_slow_view' in clock tree 'ClkxCI' is redundant
View 'gmu_skein_slow_view' in clock tree 'ClkxCI' is redundant
View 'ram1_slow_view' in clock tree 'ClkxCI' is redundant
View 'ram2_slow_view' in clock tree 'ClkxCI' is redundant
View 'ram3_slow_view' in clock tree 'ClkxCI' is redundant
View 'test_slow_view' in clock tree 'ClkxCI' is redundant
Enabling 8 Threads ...
Multi-cpu acceleration using 8 CPU(s).
Selecting the worst MMMC view of clock tree 'ClkxCI' ...
resized 0 standard cell(s).
inserted 0 standard cell(s).
*** Gated Clock Tree Optimization (cpu=0:00:00.6 real=0:00:01.0 mem=3546.6M) ***
*** Finished Clock Tree Skew Optimization (cpu=0:00:00.6 real=0:00:01.0 mem=3546.6M) ***
None of the clock tree buffers/gates are modified by the skew optimization.
Switching to the default view 'dummy_slow_view' ...
*** None of the buffer chains at roots are modified by the fine-tune process.
All-RC-Corners-Per-Net-In-Memory is turned ON...
*** Look For Reconvergent Clock Component ***
The clock tree ClkxCI has no reconvergent cell.
# Analysis View: dummy_slow_view
********** Clock ClkxCI Clk-Route-Only Timing Analysis **********
Nr. of Subtrees : 18
Nr. of Sinks : 21199
Nr. of Buffer : 549
Nr. of Level (including gates) : 11
Root Rise Input Tran : 0.1(ps)
Root Fall Input Tran : 0.1(ps)
Max trig. edge delay at sink(R): top/i_ethz_groestl/HxDP_reg_458_/CK 2378.7(ps)
Min trig. edge delay at sink(R): top/i_gmu_sha2/datapathInst_dc/wires_reg_15__10_/CK 2299.6(ps)
(Actual) (Required)
Rise Phase Delay : 2299.6~2378.7(ps) 0~1000(ps)
Fall Phase Delay : 2319.9~2414.4(ps) 0~1000(ps)
Trig. Edge Skew : 79.1(ps) 250(ps)
Rise Skew : 79.1(ps)
Fall Skew : 94.5(ps)
Max. Rise Buffer Tran. : 202.8(ps) 250(ps)
Max. Fall Buffer Tran. : 209.6(ps) 250(ps)
Max. Rise Sink Tran. : 200.2(ps) 350(ps)
Max. Fall Sink Tran. : 202.5(ps) 350(ps)
Min. Rise Buffer Tran. : 13.8(ps) 0(ps)
Min. Fall Buffer Tran. : 13.3(ps) 0(ps)
Min. Rise Sink Tran. : 62.9(ps) 0(ps)
Min. Fall Sink Tran. : 63.8(ps) 0(ps)
view dummy_slow_view : skew = 79.1ps (required = 250ps)
view ethz_blake_slow_view : skew = 79.1ps (required = 250ps)
view ethz_groestl_slow_view : skew = 79.1ps (required = 250ps)
view ethz_jh_slow_view : skew = 79.1ps (required = 250ps)
view ethz_keccak_slow_view : skew = 79.1ps (required = 250ps)
view ethz_sha2_slow_view : skew = 79.1ps (required = 250ps)
view ethz_skein_slow_view : skew = 79.1ps (required = 250ps)
view gmu_blake_slow_view : skew = 79.1ps (required = 250ps)
view gmu_groestl_slow_view : skew = 79.1ps (required = 250ps)
view gmu_jh_slow_view : skew = 79.1ps (required = 250ps)
view gmu_keccak_slow_view : skew = 79.1ps (required = 250ps)
view gmu_sha2_slow_view : skew = 79.1ps (required = 250ps)
view gmu_skein_slow_view : skew = 79.1ps (required = 250ps)
view ram1_slow_view : skew = 79.1ps (required = 250ps)
view ram2_slow_view : skew = 79.1ps (required = 250ps)
view ram3_slow_view : skew = 79.1ps (required = 250ps)
view test_slow_view : skew = 79.1ps (required = 250ps)
view hold_fast_view : skew = 46.4ps (required = 250ps)
Clock ClkxCI has been routed. Routing guide will not be generated.
Generating Clock Analysis Report timingReports_final/clock.report ....
Generating Clock Routing Guide shabziger_chip.rguide ....
Clock Analysis (CPU Time 0:00:05.6)
All-RC-Corners-Per-Net-In-Memory is turned OFF...
Clock gating checks
============================================================
Clock gating Checks Finished, CPU=0:00:00.0
============================================================
#############################################################################
#
# Summary of During-Synthesis Checks
#
#############################################################################
Types of Check : Number of warnings
----------------------------------------------------------------------------
Check RefinePlacement move distance : 0
Check route layer follows preference : 0
Check route follows guide : 0
clock gating checks : 0
*** End ckSynthesis (cpu=2:07:31, real=2:11:36, mem=3546.6M) ***
specifyClockTree -update {AutoCTSRootPin * PostOpt YES}
ckECO -postCTS -useSpecFileCellsOnly
Redoing specifyClockTree ...
Checking spec file integrity...
***** Doing trialRoute -handlePreroute.
moveBlkTerm was implicitly turned on (since useM1).
*** Starting trialRoute (mem=3546.6M) ***
There are 0 pin guide points passed to trialRoute.
moveBlkTerm was implicitly turned on (since useM1).
Options: -moveBlkTerm -useM1 -handlePreroute -keepMarkedOptRoutes -noPinGuide
Nr of prerouted/Fixed nets = 606
There are 567 nets with 1 extra space.
Num blk terms moved = 949575.
routingBox: (100 200) (1874900 1874800)
coreBox: (148800 148800) (1726200 1726200)
There are 567 prerouted nets with extraSpace.
Number of multi-gpin terms=0, multi-gpins=0, moved blk term=191/177778
Phase 1a route (0:00:03.2 3683.9M):
Est net length = 1.552e+07um = 7.372e+06H + 8.151e+06V
Usage: (27.6%H 31.2%V) = (8.115e+06um 8.368e+06um) = (8109379 4649033)
Obstruct: 784156 = 288147 (16.7%H) + 496009 (28.8%V)
Overflow: 16036 = 5010 (0.35% H) + 11026 (0.90% V)
Number obstruct path=58156 reroute=0
There are 567 prerouted nets with extraSpace.
Phase 1b route (0:00:05.5 3693.9M):
Usage: (28.0%H 31.5%V) = (8.237e+06um 8.448e+06um) = (8230805 4693538)
Overflow: 42704 = 3276 (0.23% H) + 39428 (3.21% V)
There are 567 prerouted nets with extraSpace.
Phase 1c route (0:00:03.7 3693.9M):
Usage: (28.0%H 31.5%V) = (8.229e+06um 8.453e+06um) = (8222742 4696055)
Overflow: 36510 = 2787 (0.19% H) + 33722 (2.75% V)
Phase 1d route (0:00:03.3 3693.9M):
Usage: (28.0%H 31.5%V) = (8.230e+06um 8.457e+06um) = (8224477 4698521)
Overflow: 23852 = 840 (0.06% H) + 23013 (1.88% V)
Phase 1e route (0:00:02.3 3760.8M):
Usage: (28.0%H 31.5%V) = (8.242e+06um 8.462e+06um) = (8235937 4701079)
Overflow: 715 = 20 (0.00% H) + 695 (0.06% V)
Phase 1f route (0:00:02.1 3760.8M):
Usage: (28.0%H 31.5%V) = (8.242e+06um 8.462e+06um) = (8235723 4701151)
Overflow: 392 = 3 (0.00% H) + 389 (0.03% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-7: 0 0.00% 1 0.00%
-4: 0 0.00% 4 0.00%
-3: 0 0.00% 16 0.00%
-2: 0 0.00% 30 0.00%
-1: 3 0.00% 308 0.03%
--------------------------------------
0: 541 0.04% 6180 0.50%
1: 1921 0.13% 14949 1.22%
2: 4230 0.29% 22861 1.86%
3: 10134 0.71% 40347 3.29%
4: 14055 0.98% 67624 5.51%
5: 18963 1.32% 286682 23.37%
6: 28437 1.98% 130358 10.63%
7: 33201 2.31% 83563 6.81%
8: 42956 2.99% 75819 6.18%
9: 60828 4.24% 68854 5.61%
10: 63798 4.45% 76863 6.27%
11: 74839 5.22% 54499 4.44%
12: 166482 11.61% 46412 3.78%
13: 205690 14.34% 34184 2.79%
14: 118819 8.28% 28812 2.35%
15: 74459 5.19% 139690 11.39%
16: 70650 4.93% 37877 3.09%
17: 63429 4.42% 441 0.04%
18: 58097 4.05% 5894 0.48%
19: 47574 3.32% 15 0.00%
20: 275347 19.20% 4308 0.35%
Global route (cpu=20.2s real=20.0s 3691.4M)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Phase 1l route (0:00:19.8 3617.6M):
There are 567 prerouted nets with extraSpace.
*** After '-updateRemainTrks' operation:
Usage: (28.8%H 33.2%V) = (8.468e+06um 8.896e+06um) = (8461567 4942249)
Overflow: 3606 = 166 (0.01% H) + 3441 (0.28% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-7: 0 0.00% 1 0.00%
-5: 0 0.00% 1 0.00%
-4: 0 0.00% 17 0.00%
-3: 3 0.00% 80 0.01%
-2: 23 0.00% 592 0.05%
-1: 128 0.01% 2426 0.20%
--------------------------------------
0: 787 0.05% 10091 0.82%
1: 2373 0.17% 20720 1.69%
2: 5028 0.35% 30834 2.51%
3: 11516 0.80% 49020 4.00%
4: 15883 1.11% 70223 5.73%
5: 21409 1.49% 285950 23.31%
6: 31630 2.21% 126822 10.34%
7: 36664 2.56% 78896 6.43%
8: 46174 3.22% 71302 5.81%
9: 63176 4.40% 64748 5.28%
10: 65171 4.54% 72525 5.91%
11: 74740 5.21% 51215 4.18%
12: 165425 11.53% 43639 3.56%
13: 204221 14.24% 32163 2.62%
14: 117036 8.16% 27546 2.25%
15: 71835 5.01% 139290 11.36%
16: 68115 4.75% 37879 3.09%
17: 60894 4.25% 422 0.03%
18: 55608 3.88% 5866 0.48%
19: 45458 3.17% 17 0.00%
20: 271156 18.90% 4306 0.35%
Num blk terms moved back = 942821
*** Completed Phase 1 route (0:00:45.9 3652.2M) ***
Total length: 1.616e+07um, number of vias: 2552510
M1(H) length: 1.092e+04um, number of vias: 972768
M2(V) length: 2.694e+06um, number of vias: 970411
M3(H) length: 3.915e+06um, number of vias: 359515
M4(V) length: 3.142e+06um, number of vias: 162914
M5(H) length: 3.302e+06um, number of vias: 77699
M6(V) length: 2.739e+06um, number of vias: 8415
M7(H) length: 3.483e+05um, number of vias: 788
M8(V) length: 9.343e+03um
*** Completed Phase 2 route (0:01:11 3721.3M) ***
*** Finished all Phases (cpu=0:02:00 mem=3721.3M) ***
Peak Memory Usage was 3704.4M
*** Finished trialRoute (cpu=0:02:04 mem=3721.3M) ***
Extraction called for design 'shabziger_chip' of instances=310701 and nets=283616 using extraction engine 'preRoute' .
Default RC Extraction called for design shabziger_chip.
RC Extraction called in multi-corner(2) mode.
RCMode: Default
RC Corner Indexes 0 1
Capacitance Scaling Factor : 1.00000 1.00000
Resistance Scaling Factor : 1.00000 1.00000
Clock Cap. Scaling Factor : 1.00000 1.00000
Clock Res. Scaling Factor : 1.00000 1.00000
Shrink Factor : 1.00000
Default RC extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Default RC Extraction DONE (CPU Time: 0:00:02.6 Real Time: 0:00:03.0 MEM: 3721.270M)
All-RC-Corners-Per-Net-In-Memory is turned ON...
**WARN: (ENCCK-180): CTS has ignored the 'RouteClkNet = YES' statement for the clock tree ClkxCI.
setting up for view 'dummy_slow_view'...
setting up for view 'ethz_blake_slow_view'...
setting up for view 'ethz_groestl_slow_view'...
setting up for view 'ethz_jh_slow_view'...
setting up for view 'ethz_keccak_slow_view'...
setting up for view 'ethz_sha2_slow_view'...
setting up for view 'ethz_skein_slow_view'...
setting up for view 'gmu_blake_slow_view'...
setting up for view 'gmu_groestl_slow_view'...
setting up for view 'gmu_jh_slow_view'...
setting up for view 'gmu_keccak_slow_view'...
setting up for view 'gmu_sha2_slow_view'...
setting up for view 'gmu_skein_slow_view'...
setting up for view 'ram1_slow_view'...
setting up for view 'ram2_slow_view'...
setting up for view 'ram3_slow_view'...
setting up for view 'test_slow_view'...
setting up for view 'hold_fast_view'...
View 'ethz_blake_slow_view' in clock tree 'ClkxCI' is redundant
View 'ethz_groestl_slow_view' in clock tree 'ClkxCI' is redundant
View 'ethz_jh_slow_view' in clock tree 'ClkxCI' is redundant
View 'ethz_keccak_slow_view' in clock tree 'ClkxCI' is redundant
View 'ethz_sha2_slow_view' in clock tree 'ClkxCI' is redundant
View 'ethz_skein_slow_view' in clock tree 'ClkxCI' is redundant
View 'gmu_blake_slow_view' in clock tree 'ClkxCI' is redundant
View 'gmu_groestl_slow_view' in clock tree 'ClkxCI' is redundant
View 'gmu_jh_slow_view' in clock tree 'ClkxCI' is redundant
View 'gmu_keccak_slow_view' in clock tree 'ClkxCI' is redundant
View 'gmu_sha2_slow_view' in clock tree 'ClkxCI' is redundant
View 'gmu_skein_slow_view' in clock tree 'ClkxCI' is redundant
View 'ram1_slow_view' in clock tree 'ClkxCI' is redundant
View 'ram2_slow_view' in clock tree 'ClkxCI' is redundant
View 'ram3_slow_view' in clock tree 'ClkxCI' is redundant
View 'test_slow_view' in clock tree 'ClkxCI' is redundant
# Analysis View: dummy_slow_view
********** Clock ClkxCI Post-CTS Timing Analysis **********
Nr. of Subtrees : 18
Nr. of Sinks : 21199
Nr. of Buffer : 549
Nr. of Level (including gates) : 11
Root Rise Input Tran : 0.1(ps)
Root Fall Input Tran : 0.1(ps)
Max trig. edge delay at sink(R): top/i_ethz_skein/KeyxDP_reg_2__37_/CK 2354.8(ps)
Min trig. edge delay at sink(R): top/i_inputblock_Data2xDP_reg_358_/CK 2266.1(ps)
(Actual) (Required)
Rise Phase Delay : 2266.1~2354.8(ps) 0~1000(ps)
Fall Phase Delay : 2290.2~2380.5(ps) 0~1000(ps)
Trig. Edge Skew : 88.7(ps) 250(ps)
Rise Skew : 88.7(ps)
Fall Skew : 90.3(ps)
Max. Rise Buffer Tran. : 246.4(ps) 250(ps)
Max. Fall Buffer Tran. : 256.1(ps) 250(ps)
Max. Rise Sink Tran. : 227(ps) 350(ps)
Max. Fall Sink Tran. : 227.8(ps) 350(ps)
Min. Rise Buffer Tran. : 14(ps) 0(ps)
Min. Fall Buffer Tran. : 13.5(ps) 0(ps)
Min. Rise Sink Tran. : 32.9(ps) 0(ps)
Min. Fall Sink Tran. : 32.6(ps) 0(ps)
view dummy_slow_view : skew = 88.7ps (required = 250ps)
view ethz_blake_slow_view : skew = 88.7ps (required = 250ps)
view ethz_groestl_slow_view : skew = 88.7ps (required = 250ps)
view ethz_jh_slow_view : skew = 88.7ps (required = 250ps)
view ethz_keccak_slow_view : skew = 88.7ps (required = 250ps)
view ethz_sha2_slow_view : skew = 88.7ps (required = 250ps)
view ethz_skein_slow_view : skew = 88.7ps (required = 250ps)
view gmu_blake_slow_view : skew = 88.7ps (required = 250ps)
view gmu_groestl_slow_view : skew = 88.7ps (required = 250ps)
view gmu_jh_slow_view : skew = 88.7ps (required = 250ps)
view gmu_keccak_slow_view : skew = 88.7ps (required = 250ps)
view gmu_sha2_slow_view : skew = 88.7ps (required = 250ps)
view gmu_skein_slow_view : skew = 88.7ps (required = 250ps)
view ram1_slow_view : skew = 88.7ps (required = 250ps)
view ram2_slow_view : skew = 88.7ps (required = 250ps)
view ram3_slow_view : skew = 88.7ps (required = 250ps)
view test_slow_view : skew = 88.7ps (required = 250ps)
view hold_fast_view : skew = 53.9ps (required = 250ps)
Clock Analysis (CPU Time 0:00:20.8)
Switching to the default view 'dummy_slow_view' ...
Enabling 8 Threads ...
Multi-cpu acceleration using 8 CPU(s).
*** Finished Rebuilding Buffer Chain (cpu=0:00:00.0 real=0:00:00.0 mem=3831.6M) ***
*** None of the buffer chains at roots are modified by the re-build process.
Enabling 8 Threads ...
Multi-cpu acceleration using 8 CPU(s).
Selecting the worst MMMC view of clock tree 'ClkxCI' ...
resized 0 standard cell(s).
inserted 0 standard cell(s).
*** Gated Clock Tree Optimization (cpu=0:00:02.4 real=0:00:02.0 mem=3836.9M) ***
*** Finished Clock Tree Skew Optimization (cpu=0:00:02.4 real=0:00:02.0 mem=3832.6M) ***
*** None of the clock tree buffers/gates are modified by the skew optimization.
Switching to the default view 'dummy_slow_view' ...
*** None of the buffer chains at roots are modified by the fine-tune process.
*** Look For Reconvergent Clock Component ***
The clock tree ClkxCI has no reconvergent cell.
# Analysis View: dummy_slow_view
********** Clock ClkxCI Post-CTS Timing Analysis **********
Nr. of Subtrees : 18
Nr. of Sinks : 21199
Nr. of Buffer : 549
Nr. of Level (including gates) : 11
Root Rise Input Tran : 0.1(ps)
Root Fall Input Tran : 0.1(ps)
Max trig. edge delay at sink(R): top/i_ethz_skein/KeyxDP_reg_2__37_/CK 2354.8(ps)
Min trig. edge delay at sink(R): top/i_inputblock_Data2xDP_reg_358_/CK 2266.1(ps)
(Actual) (Required)
Rise Phase Delay : 2266.1~2354.8(ps) 0~1000(ps)
Fall Phase Delay : 2290.2~2380.5(ps) 0~1000(ps)
Trig. Edge Skew : 88.7(ps) 250(ps)
Rise Skew : 88.7(ps)
Fall Skew : 90.3(ps)
Max. Rise Buffer Tran. : 246.4(ps) 250(ps)
Max. Fall Buffer Tran. : 256.1(ps) 250(ps)
Max. Rise Sink Tran. : 227(ps) 350(ps)
Max. Fall Sink Tran. : 227.8(ps) 350(ps)
Min. Rise Buffer Tran. : 14(ps) 0(ps)
Min. Fall Buffer Tran. : 13.5(ps) 0(ps)
Min. Rise Sink Tran. : 32.9(ps) 0(ps)
Min. Fall Sink Tran. : 32.6(ps) 0(ps)
view dummy_slow_view : skew = 88.7ps (required = 250ps)
view ethz_blake_slow_view : skew = 88.7ps (required = 250ps)
view ethz_groestl_slow_view : skew = 88.7ps (required = 250ps)
view ethz_jh_slow_view : skew = 88.7ps (required = 250ps)
view ethz_keccak_slow_view : skew = 88.7ps (required = 250ps)
view ethz_sha2_slow_view : skew = 88.7ps (required = 250ps)
view ethz_skein_slow_view : skew = 88.7ps (required = 250ps)
view gmu_blake_slow_view : skew = 88.7ps (required = 250ps)
view gmu_groestl_slow_view : skew = 88.7ps (required = 250ps)
view gmu_jh_slow_view : skew = 88.7ps (required = 250ps)
view gmu_keccak_slow_view : skew = 88.7ps (required = 250ps)
view gmu_sha2_slow_view : skew = 88.7ps (required = 250ps)
view gmu_skein_slow_view : skew = 88.7ps (required = 250ps)
view ram1_slow_view : skew = 88.7ps (required = 250ps)
view ram2_slow_view : skew = 88.7ps (required = 250ps)
view ram3_slow_view : skew = 88.7ps (required = 250ps)
view test_slow_view : skew = 88.7ps (required = 250ps)
view hold_fast_view : skew = 53.9ps (required = 250ps)
Generating Clock Analysis Report shabziger_chip.ctsrpt ....
Clock Analysis (CPU Time 0:00:20.8)
All-RC-Corners-Per-Net-In-Memory is turned OFF...
*** End ckECO (cpu=0:04:08, real=0:04:08, mem=3794.4M) ***
**clockDesign ... cpu = 2:11:44, real = 2:15:49, mem = 3794.4M **
timeDesign -reportOnly -expandedViews -outDir timingReports_final -prefix shabziger.postCTS.expV
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
timeDesign Summary
------------------------------------------------------------
+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| -0.227 | -0.227 | 2.405 | 0.370 | 18.789 | 16.425 |
| TNS (ns):| -80.999 | -80.999 | 0.000 | 0.000 | 0.000 | 0.000 |
| Violating Paths:| 1447 | 1447 | 0 | 0 | 0 | 0 |
| All Paths:| 85005 | 46605 | 63302 | 19 | 2 | 15 |
+--------------------+---------+---------+---------+---------+---------+---------+
|dummy_slow_view | 7.934 | 7.934 | 10.825 | 8.770 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5131 | 2517 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_blake_slow_view| 0.022 | 0.022 | 5.825 | 3.770 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 8290 | 4385 | 3887 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_groestl_slow_view
| | -0.097 | -0.097 | 4.421 | 2.370 | N/A | N/A |
| | -1.113 | -1.113 | 0.000 | 0.000 | N/A | N/A |
| | 34 | 34 | 0 | 0 | N/A | N/A |
| | 8236 | 4070 | 4148 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_jh_slow_view | 0.071 | 0.071 | 3.633 | 1.770 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 8801 | 4640 | 4143 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_keccak_slow_view
| | -0.048 | -0.048 | 2.717 | 0.770 | N/A | N/A |
| | -0.218 | -0.218 | 0.000 | 0.000 | N/A | N/A |
| | 13 | 13 | 0 | 0 | N/A | N/A |
| | 8346 | 4125 | 4203 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_sha2_slow_view | 0.126 | 0.126 | 4.325 | 2.270 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 7204 | 3554 | 3632 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_skein_slow_view| -0.047 | -0.047 | 3.502 | 1.570 | N/A | N/A |
| | -0.172 | -0.172 | 0.000 | 0.000 | N/A | N/A |
| | 7 | 7 | 0 | 0 | N/A | N/A |
| | 9002 | 4517 | 4467 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_blake_slow_view | -0.153 | -0.153 | 4.725 | 2.670 | N/A | N/A |
| | -11.052 | -11.052 | 0.000 | 0.000 | N/A | N/A |
| | 141 | 141 | 0 | 0 | N/A | N/A |
| | 9724 | 5498 | 4208 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_groestl_slow_view
| | -0.170 | -0.170 | 2.799 | 0.870 | N/A | N/A |
| | -55.577 | -55.577 | 0.000 | 0.000 | N/A | N/A |
| | 942 | 942 | 0 | 0 | N/A | N/A |
| | 9252 | 5088 | 4146 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_jh_slow_view | -0.070 | -0.070 | 2.425 | 0.370 | N/A | N/A |
| | -0.482 | -0.482 | 0.000 | 0.000 | N/A | N/A |
| | 28 | 28 | 0 | 0 | N/A | N/A |
| | 10269 | 5853 | 4398 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_keccak_slow_view| -0.088 | -0.088 | 2.405 | 0.370 | N/A | N/A |
| | -2.977 | -2.977 | 0.000 | 0.000 | N/A | N/A |
| | 127 | 127 | 0 | 0 | N/A | N/A |
| | 9926 | 5702 | 4206 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_sha2_slow_view | -0.035 | -0.035 | 2.549 | 0.570 | N/A | N/A |
| | -0.443 | -0.443 | 0.000 | 0.000 | N/A | N/A |
| | 30 | 30 | 0 | 0 | N/A | N/A |
| | 7986 | 4238 | 3730 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_skein_slow_view | -0.227 | -0.227 | 3.207 | 4.270 | N/A | N/A |
| | -9.022 | -9.022 | 0.000 | 0.000 | N/A | N/A |
| | 129 | 129 | 0 | 0 | N/A | N/A |
| | 10156 | 5551 | 4587 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ram1_slow_view | 5.252 | 5.252 | 10.825 | 8.770 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5237 | 2623 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ram2_slow_view | 5.015 | 5.015 | 10.825 | 8.770 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5237 | 2623 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ram3_slow_view | 3.443 | 3.443 | 10.825 | 8.770 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5240 | 2626 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|test_slow_view | 13.399 | 13.399 | 14.096 | 18.770 | 18.789 | 16.425 |
| | 0.000 | 0.000 | 0.000 | 0.000 | 0.000 | 0.000 |
| | 0 | 0 | 0 | 0 | 0 | 0 |
| | 85005 | 46605 | 63302 | 19 | 2 | 15 |
+--------------------+---------+---------+---------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 4 (4) | -0.019 | 4 (4) |
| max_tran | 4 (12) | -0.655 | 4 (12) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 60.441%
------------------------------------------------------------
Reported timing to dir timingReports_final
Total CPU time: 1518.41 sec
Total Real time: 1462.0 sec
Total Memory Usage: 4097.664062 Mbytes
setOptMode -setupTargetSlack -.050
*info: Setting setup target slack to -0.050
*info: Hold target slack is 0.000
optDesign -postCTS -outDir timingReports_final
**WARN: (PRL-55): Reducing the number of threads from 8 to 4 due to memory limitations
Enabling multi-CPU acceleration with 4 CPU(s) for optimization
Connected to aotearoa.ee.ethz.ch 35883 0
Connected to aotearoa.ee.ethz.ch 36151 1
Connected to aotearoa.ee.ethz.ch 46565 2
Connected to aotearoa.ee.ethz.ch 36732 3
*** Finished dispatch of slaves (cpu=0:02:31) (real=0:03:23) ***
**WARN: (ENCOPT-6055): The following cells have a dont_touch property but without being dont_use.
Such configuration can impact the timing closure because they can be inserted in the netlist but never transformed again.
It is recommended that you apply a dont_use attribute on them.
Cell SYKA65_2048X32X1CM8 is dont_touch but not dont_use
Cell SHKA65_2048X32X1CM4 is dont_touch but not dont_use
Cell SHKA65_16384X32X1CM16 is dont_touch but not dont_use
...
Reporting only the 20 first cells found...
**optDesign ... cpu = 0:00:00, real = 0:00:00, mem = 4109.0M **
*** optDesign -postCTS ***
DRC Margin: user margin 0.0; extra margin 0.2
Hold Target Slack: user slack 0.0
Setup Target Slack: user slack -0.05; extra slack 0.1
*info: Setting setup target slack to 0.050
*info: Hold target slack is 0.000
**INFO : Adding temp dont-use cells (LVT only flow version : 4)
Creating information for LVT Only Flow
Num of Buffers : 123
Num of Inverters : 105
Num of VTs : 3
Executing LVT Only Same Size Flow (setting 4)
*Info* Num dontuse cells 311
*Info* Num dontuse cells 2259
moveBlkTerm was implicitly turned on (since useM1).
*** Starting trialRoute (mem=4113.0M) ***
There are 0 pin guide points passed to trialRoute.
Start to check current routing status for nets...
All nets are already routed correctly.
*** Finishing trialRoute (mem=4122.0M) ***
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
Initial Summary
------------------------------------------------------------
+--------------------+---------+
| Setup mode | all |
+--------------------+---------+
| WNS (ns):| -0.227 |
| TNS (ns):| -80.999 |
| Violating Paths:| 1447 |
| All Paths:| 85005 |
+--------------------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 4 (4) | -0.019 | 4 (4) |
| max_tran | 4 (12) | -0.655 | 4 (12) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 60.441%
------------------------------------------------------------
**optDesign ... cpu = 0:02:14, real = 0:01:17, mem = 4438.4M **
*** Starting optimizing excluded clock nets MEM= 4438.4M) ***
*info: No excluded clock nets to be optimized.
*** Completed optimizing excluded clock nets (CPU Time= 0:00:00.0 MEM= 4438.4M) ***
*** Starting optimizing excluded clock nets MEM= 4438.4M) ***
*info: No excluded clock nets to be optimized.
*** Completed optimizing excluded clock nets (CPU Time= 0:00:00.0 MEM= 4438.4M) ***
************ Started Recovering Area and Global Resizing for Timing Improvement ***************
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
Info: 40 io nets excluded
Info: 566 nets with fixed/cover wires excluded.
Info: 567 clock nets excluded from IPO operation.
** Density before transform = 60.441% **
*** starting 1-st resizing pass: 32398 instances
*** starting 2-nd resizing pass: 31973 instances
*** starting 3-rd resizing pass: 19109 instances
*** starting 4-th resizing pass: 4298 instances
*** starting 5-th resizing pass: 712 instances
*** starting 6-th resizing pass: 110 instances
** Summary: Buffer Deletion = 11 Declone = 414 Downsize = 7801 Upsize = 1505 **
** Density Change = 0.992% **
** Density after transform = 59.448% **
*** Finish transform (0:07:34) ***
density before resizing = 59.448%
* summary of transition time violation fixes:
*summary: 526 instances changed cell type
density after resizing = 59.466%
************ Finished Recovering Area and Global Resizing for Timing Improvement ***************
default core: bins with density > 0.75 = 23.3 % ( 1804 / 7744 )
Starting refinePlace ...
move report: placeLevelShifters moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Spread Effort: high, pre-route mode.
Finished Phase I. CPU Time = 0:00:28.3, Real Time = 0:00:28.0
move report: preRPlace moves 1904 insts, mean move: 0.54 um, max move: 6.20 um
max move on inst (top/i_gmu_skein/datapathInst/keygen_gen/key_reg_gen_5_output_reg_50_): (1137.20, 1443.00) --> (1139.80, 1439.40)
move report: rPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: overall moves 1904 insts, mean move: 0.54 um, max move: 6.20 um
max move on inst (top/i_gmu_skein/datapathInst/keygen_gen/key_reg_gen_5_output_reg_50_): (1137.20, 1443.00) --> (1139.80, 1439.40)
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 6.20 um
inst (top/i_gmu_skein/datapathInst/keygen_gen/key_reg_gen_5_output_reg_50_) with max move: (1137.2, 1443) -> (1139.8, 1439.4)
mean (X+Y) = 0.54 um
Total instances moved : 1904
*** cpu=0:00:30.3 mem=4419.6M mem(used)=24.1M***
moveBlkTerm was implicitly turned on (since useM1).
*** Starting trialRoute (mem=4446.7M) ***
There are 0 pin guide points passed to trialRoute.
moveBlkTerm was implicitly turned on (since useM1).
Options: -moveBlkTerm -useM1 -handlePreroute -keepMarkedOptRoutes -noPinGuide
Nr of prerouted/Fixed nets = 606
There are 567 nets with 1 extra space.
Num blk terms moved = 948725.
routingBox: (100 200) (1874900 1874800)
coreBox: (148800 148800) (1726200 1726200)
There are 567 prerouted nets with extraSpace.
Number of multi-gpin terms=0, multi-gpins=0, moved blk term=191/177866
Phase 1a route (0:00:03.0 4553.1M):
Est net length = 1.553e+07um = 7.375e+06H + 8.157e+06V
Usage: (27.6%H 31.2%V) = (8.118e+06um 8.375e+06um) = (8112111 4652572)
Obstruct: 784153 = 288147 (16.7%H) + 496006 (28.8%V)
Overflow: 15660 = 4916 (0.34% H) + 10744 (0.88% V)
Number obstruct path=58191 reroute=0
There are 567 prerouted nets with extraSpace.
Phase 1b route (0:00:06.4 4558.6M):
Usage: (28.0%H 31.5%V) = (8.240e+06um 8.454e+06um) = (8234329 4696472)
Overflow: 42896 = 3268 (0.23% H) + 39628 (3.23% V)
There are 567 prerouted nets with extraSpace.
Phase 1c route (0:00:04.3 4558.6M):
Usage: (27.9%H 31.5%V) = (8.232e+06um 8.458e+06um) = (8226313 4699113)
Overflow: 36508 = 2757 (0.19% H) + 33751 (2.75% V)
Phase 1d route (0:00:03.6 4558.6M):
Usage: (27.9%H 31.5%V) = (8.234e+06um 8.463e+06um) = (8228025 4701550)
Overflow: 23650 = 826 (0.06% H) + 22825 (1.86% V)
Phase 1e route (0:00:02.4 4623.6M):
Usage: (28.0%H 31.6%V) = (8.245e+06um 8.467e+06um) = (8239524 4704098)
Overflow: 719 = 19 (0.00% H) + 699 (0.06% V)
Phase 1f route (0:00:02.1 4623.6M):
Usage: (28.0%H 31.6%V) = (8.245e+06um 8.467e+06um) = (8239298 4704124)
Overflow: 402 = 4 (0.00% H) + 398 (0.03% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-7: 0 0.00% 1 0.00%
-4: 0 0.00% 4 0.00%
-3: 0 0.00% 16 0.00%
-2: 0 0.00% 31 0.00%
-1: 4 0.00% 316 0.03%
--------------------------------------
0: 577 0.04% 6189 0.50%
1: 1925 0.13% 15053 1.23%
2: 4180 0.29% 22698 1.85%
3: 10107 0.70% 40684 3.32%
4: 13893 0.97% 67266 5.48%
5: 19163 1.34% 287480 23.44%
6: 28267 1.97% 129564 10.56%
7: 32836 2.29% 84164 6.86%
8: 42482 2.96% 75778 6.18%
9: 60058 4.19% 68576 5.59%
10: 63202 4.41% 76511 6.24%
11: 74190 5.17% 54345 4.43%
12: 166157 11.58% 46755 3.81%
13: 205212 14.31% 34162 2.79%
14: 118358 8.25% 28888 2.36%
15: 74275 5.18% 139721 11.39%
16: 70840 4.94% 37735 3.08%
17: 63711 4.44% 440 0.04%
18: 58709 4.09% 5894 0.48%
19: 48163 3.36% 15 0.00%
20: 278144 19.39% 4308 0.35%
Global route (cpu=21.9s real=22.0s 4553.7M)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Phase 1l route (0:00:21.5 4480.9M):
There are 567 prerouted nets with extraSpace.
*** After '-updateRemainTrks' operation:
Usage: (28.8%H 33.2%V) = (8.471e+06um 8.901e+06um) = (8465187 4945253)
Overflow: 3645 = 185 (0.01% H) + 3460 (0.28% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-7: 0 0.00% 1 0.00%
-4: 0 0.00% 14 0.00%
-3: 3 0.00% 94 0.01%
-2: 22 0.00% 575 0.05%
-1: 149 0.01% 2453 0.20%
--------------------------------------
0: 808 0.06% 10110 0.82%
1: 2375 0.17% 20904 1.70%
2: 5016 0.35% 30750 2.51%
3: 11442 0.80% 49103 4.00%
4: 15841 1.10% 69733 5.69%
5: 21581 1.50% 286881 23.39%
6: 31325 2.18% 126361 10.30%
7: 36248 2.53% 79335 6.47%
8: 45856 3.20% 70938 5.78%
9: 62275 4.34% 64520 5.26%
10: 64420 4.49% 72438 5.91%
11: 74280 5.18% 51056 4.16%
12: 165031 11.50% 43869 3.58%
13: 203718 14.20% 32147 2.62%
14: 116710 8.14% 27629 2.25%
15: 71794 5.00% 139336 11.36%
16: 68142 4.75% 37736 3.08%
17: 61283 4.27% 423 0.03%
18: 56373 3.93% 5865 0.48%
19: 45788 3.19% 17 0.00%
20: 273973 19.10% 4306 0.35%
Num blk terms moved back = 941953
*** Completed Phase 1 route (0:00:49.6 4479.0M) ***
Total length: 1.617e+07um, number of vias: 2551180
M1(H) length: 1.092e+04um, number of vias: 971942
M2(V) length: 2.693e+06um, number of vias: 969215
M3(H) length: 3.905e+06um, number of vias: 359430
M4(V) length: 3.138e+06um, number of vias: 163176
M5(H) length: 3.312e+06um, number of vias: 78033
M6(V) length: 2.748e+06um, number of vias: 8616
M7(H) length: 3.519e+05um, number of vias: 768
M8(V) length: 9.320e+03um
*** Completed Phase 2 route (0:00:58.6 4450.7M) ***
*** Finished all Phases (cpu=0:01:50 mem=4450.7M) ***
Peak Memory Usage was 4568.0M
*** Finished trialRoute (cpu=0:01:54 mem=4450.7M) ***
Extraction called for design 'shabziger_chip' of instances=310276 and nets=283191 using extraction engine 'preRoute' .
Default RC Extraction called for design shabziger_chip.
RC Extraction called in multi-corner(2) mode.
RCMode: Default
RC Corner Indexes 0 1
Capacitance Scaling Factor : 1.00000 1.00000
Resistance Scaling Factor : 1.00000 1.00000
Clock Cap. Scaling Factor : 1.00000 1.00000
Clock Res. Scaling Factor : 1.00000 1.00000
Shrink Factor : 1.00000
Default RC extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Default RC Extraction DONE (CPU Time: 0:00:02.5 Real Time: 0:00:02.0 MEM: 4450.676M)
Using new Cte TW Api base...#################################################################################
# Design Stage: PreRoute
# Design Mode: 65nm
# Analysis Mode: MMMC non-OCV
# Extraction Mode: default
# Delay Calculation Options: engine=signalStorm signOff=true SIAware=false(opt)
# Switching Delay Calculation Engine to signalStorm
#################################################################################
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:02.0, MEM = 3861.6M, InitMEM = 3861.6M)
Start delay calculation using Signal Storm (mem=3861.594M)...
Delay calculation completed. (cpu=0:01:17 real=0:01:17 mem=4159.996M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:02.1, MEM = 4160.0M, InitMEM = 4160.0M)
Start delay calculation using Signal Storm (mem=4159.996M)...
Delay calculation completed. (cpu=0:00:47.3 real=0:00:47.0 mem=4159.996M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.9, MEM = 4160.0M, InitMEM = 4160.0M)
Start delay calculation using Signal Storm (mem=4159.996M)...
Delay calculation completed. (cpu=0:00:48.3 real=0:00:48.0 mem=4159.996M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:02.0, MEM = 4160.0M, InitMEM = 4160.0M)
Start delay calculation using Signal Storm (mem=4159.996M)...
Delay calculation completed. (cpu=0:00:47.2 real=0:00:47.0 mem=4159.996M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:02.0, MEM = 4160.0M, InitMEM = 4160.0M)
Start delay calculation using Signal Storm (mem=4159.996M)...
Delay calculation completed. (cpu=0:00:48.0 real=0:00:48.0 mem=4159.996M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:02.1, MEM = 4160.0M, InitMEM = 4160.0M)
Start delay calculation using Signal Storm (mem=4159.996M)...
Delay calculation completed. (cpu=0:00:46.8 real=0:00:47.0 mem=4159.996M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:02.0, MEM = 4160.0M, InitMEM = 4160.0M)
Start delay calculation using Signal Storm (mem=4159.996M)...
Delay calculation completed. (cpu=0:00:48.9 real=0:00:49.0 mem=4159.996M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:02.2, MEM = 4160.0M, InitMEM = 4160.0M)
Start delay calculation using Signal Storm (mem=4159.996M)...
Delay calculation completed. (cpu=0:00:49.0 real=0:00:49.0 mem=4159.996M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:02.0, MEM = 4160.0M, InitMEM = 4160.0M)
Start delay calculation using Signal Storm (mem=4159.996M)...
Delay calculation completed. (cpu=0:00:51.9 real=0:00:52.0 mem=4159.996M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:02.0, MEM = 4160.0M, InitMEM = 4160.0M)
Start delay calculation using Signal Storm (mem=4159.996M)...
Delay calculation completed. (cpu=0:00:49.6 real=0:00:50.0 mem=4159.996M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:02.1, MEM = 4160.0M, InitMEM = 4160.0M)
Start delay calculation using Signal Storm (mem=4159.996M)...
Delay calculation completed. (cpu=0:00:51.8 real=0:00:52.0 mem=4159.996M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:02.1, MEM = 4160.0M, InitMEM = 4160.0M)
Start delay calculation using Signal Storm (mem=4159.996M)...
Delay calculation completed. (cpu=0:00:49.9 real=0:00:50.0 mem=4159.996M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:02.2, MEM = 4160.0M, InitMEM = 4160.0M)
Start delay calculation using Signal Storm (mem=4159.996M)...
Delay calculation completed. (cpu=0:00:52.3 real=0:00:53.0 mem=4159.996M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:02.1, MEM = 4160.0M, InitMEM = 4160.0M)
Start delay calculation using Signal Storm (mem=4159.996M)...
Delay calculation completed. (cpu=0:00:50.2 real=0:00:50.0 mem=4159.996M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:02.0, MEM = 4160.0M, InitMEM = 4160.0M)
Start delay calculation using Signal Storm (mem=4159.996M)...
Delay calculation completed. (cpu=0:00:50.0 real=0:00:50.0 mem=4159.996M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:02.1, MEM = 4160.0M, InitMEM = 4160.0M)
Start delay calculation using Signal Storm (mem=4159.996M)...
Delay calculation completed. (cpu=0:00:50.6 real=0:00:51.0 mem=4159.996M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:02.2, MEM = 4160.0M, InitMEM = 4160.0M)
Start delay calculation using Signal Storm (mem=4159.996M)...
Delay calculation completed. (cpu=0:01:08 real=0:01:08 mem=4159.996M 0)
*** CDM Built up (cpu=0:15:29 real=0:15:29 mem= 4160.0M) ***
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
Summary (cpu=31.02min real=25.87min mem=4477.7M)
------------------------------------------------------------
+--------------------+---------+
| Setup mode | all |
+--------------------+---------+
| WNS (ns):| -0.483 |
| TNS (ns):| -81.265 |
| Violating Paths:| 1373 |
| All Paths:| 85005 |
+--------------------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 8 (8) | -0.030 | 8 (8) |
| max_tran | 7 (22) | -0.667 | 7 (22) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 59.466%
Routing Overflow: 0.01% H and 0.28% V
------------------------------------------------------------
**optDesign ... cpu = 0:34:40, real = 0:28:08, mem = 4477.7M **
*info: Start fixing DRV (Mem = 4514.58M) ...
*info: Options = -maxCap -maxTran -noMaxFanout -noSensitivity -backward -reduceBuffer -maxIter 1
*info: Start fixing DRV iteration 1 ...
*** Starting dpFixDRCViolation (4514.6M)
*info: 40 io nets excluded
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
*info: 567 clock nets excluded
*info: 4 special nets excluded.
*info: 2406 no-driver nets excluded.
*info: 566 nets with fixed/cover wires excluded.
*** Starting multi-driver net buffering ***
*summary: 0 non-ignored multi-driver nets.
*** Finished buffering multi-driver nets (CPU=0:00:00.0, MEM=4514.6M) ***
*info: 21 multi-driver nets excluded.
*info: There are 20 candidate Buffer cells
*info: There are 20 candidate Inverter cells
Initializing placement sections/sites ...
Density before buffering = 0.594660
Start fixing design rules ... (0:00:07.9 4588.5M)
Done fixing design rule (0:01:39 4592.7M)
Summary:
33 buffers added on 33 nets (with 214 drivers resized)
Density after buffering = 0.594728
default core: bins with density > 0.75 = 23.3 % ( 1807 / 7744 )
Starting refinePlace ...
move report: placeLevelShifters moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Spread Effort: high, pre-route mode.
Finished Phase I. CPU Time = 0:00:39.0, Real Time = 0:00:39.0
move report: preRPlace moves 175 insts, mean move: 0.38 um, max move: 1.80 um
max move on inst (top/i_gmu_skein/datapathInst/FE_OFC15559_round_2__3__19_): (1304.60, 1293.60) --> (1304.60, 1295.40)
move report: rPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: overall moves 175 insts, mean move: 0.38 um, max move: 1.80 um
max move on inst (top/i_gmu_skein/datapathInst/FE_OFC15559_round_2__3__19_): (1304.60, 1293.60) --> (1304.60, 1295.40)
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 1.80 um
inst (top/i_gmu_skein/datapathInst/FE_OFC15559_round_2__3__19_) with max move: (1304.6, 1293.6) -> (1304.6, 1295.4)
mean (X+Y) = 0.38 um
Total instances moved : 175
*** cpu=0:00:42.4 mem=4487.6M mem(used)=0.0M***
Ripped up 0 affected routes.
Re-routing 40 un-routed nets (0:02:34 4481.1M)
Total net count = 283224; Percent unrouted = 0.0
Done re-routing un-routed nets (0:02:35 4481.1M)
*** Completed dpFixDRCViolation (0:02:36 4480.1M)
Extraction called for design 'shabziger_chip' of instances=310309 and nets=283224 using extraction engine 'preRoute' .
Default RC Extraction called for design shabziger_chip.
RC Extraction called in multi-corner(2) mode.
RCMode: Default
RC Corner Indexes 0 1
Capacitance Scaling Factor : 1.00000 1.00000
Resistance Scaling Factor : 1.00000 1.00000
Clock Cap. Scaling Factor : 1.00000 1.00000
Clock Res. Scaling Factor : 1.00000 1.00000
Shrink Factor : 1.00000
Default RC extraction is honoring NDR/Shielding/ExtraSpace for clock nets.
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Default RC Extraction DONE (CPU Time: 0:00:03.4 Real Time: 0:00:03.0 MEM: 4479.855M)
Using new Cte TW Api base...#################################################################################
# Design Stage: PreRoute
# Design Mode: 65nm
# Analysis Mode: MMMC non-OCV
# Extraction Mode: default
# Delay Calculation Options: engine=signalStorm signOff=true SIAware=false(opt)
# Switching Delay Calculation Engine to signalStorm
#################################################################################
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:02.8, MEM = 3849.5M, InitMEM = 3849.5M)
Start delay calculation using Signal Storm (mem=3849.547M)...
Delay calculation completed. (cpu=0:01:31 real=0:01:31 mem=4152.133M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.8, MEM = 4152.1M, InitMEM = 4152.1M)
Start delay calculation using Signal Storm (mem=4152.133M)...
Delay calculation completed. (cpu=0:00:45.1 real=0:00:45.0 mem=4152.133M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.8, MEM = 4152.1M, InitMEM = 4152.1M)
Start delay calculation using Signal Storm (mem=4152.133M)...
Delay calculation completed. (cpu=0:00:46.1 real=0:00:46.0 mem=4152.133M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.8, MEM = 4152.1M, InitMEM = 4152.1M)
Start delay calculation using Signal Storm (mem=4152.133M)...
Delay calculation completed. (cpu=0:00:47.2 real=0:00:47.0 mem=4152.133M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:02.2, MEM = 4152.1M, InitMEM = 4152.1M)
Start delay calculation using Signal Storm (mem=4152.133M)...
Delay calculation completed. (cpu=0:00:47.5 real=0:00:48.0 mem=4152.133M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:02.0, MEM = 4152.1M, InitMEM = 4152.1M)
Start delay calculation using Signal Storm (mem=4152.133M)...
Delay calculation completed. (cpu=0:00:44.5 real=0:00:44.0 mem=4152.133M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:02.0, MEM = 4152.1M, InitMEM = 4152.1M)
Start delay calculation using Signal Storm (mem=4152.133M)...
Delay calculation completed. (cpu=0:00:45.6 real=0:00:46.0 mem=4152.133M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.9, MEM = 4152.1M, InitMEM = 4152.1M)
Start delay calculation using Signal Storm (mem=4152.133M)...
Delay calculation completed. (cpu=0:00:46.1 real=0:00:46.0 mem=4152.133M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.8, MEM = 4152.1M, InitMEM = 4152.1M)
Start delay calculation using Signal Storm (mem=4152.133M)...
Delay calculation completed. (cpu=0:00:47.7 real=0:00:48.0 mem=4152.133M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:02.1, MEM = 4152.1M, InitMEM = 4152.1M)
Start delay calculation using Signal Storm (mem=4152.133M)...
Delay calculation completed. (cpu=0:00:46.2 real=0:00:46.0 mem=4152.133M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:02.1, MEM = 4152.1M, InitMEM = 4152.1M)
Start delay calculation using Signal Storm (mem=4152.133M)...
Delay calculation completed. (cpu=0:00:47.7 real=0:00:48.0 mem=4152.133M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.9, MEM = 4152.1M, InitMEM = 4152.1M)
Start delay calculation using Signal Storm (mem=4152.133M)...
Delay calculation completed. (cpu=0:00:46.9 real=0:00:47.0 mem=4152.133M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.9, MEM = 4152.1M, InitMEM = 4152.1M)
Start delay calculation using Signal Storm (mem=4152.133M)...
Delay calculation completed. (cpu=0:00:50.2 real=0:00:50.0 mem=4152.133M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:02.0, MEM = 4152.1M, InitMEM = 4152.1M)
Start delay calculation using Signal Storm (mem=4152.133M)...
Delay calculation completed. (cpu=0:00:49.2 real=0:00:50.0 mem=4152.133M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.8, MEM = 4152.1M, InitMEM = 4152.1M)
Start delay calculation using Signal Storm (mem=4152.133M)...
Delay calculation completed. (cpu=0:00:47.6 real=0:00:48.0 mem=4152.133M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.8, MEM = 4152.1M, InitMEM = 4152.1M)
Start delay calculation using Signal Storm (mem=4152.133M)...
Delay calculation completed. (cpu=0:00:47.9 real=0:00:48.0 mem=4152.133M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.9, MEM = 4152.1M, InitMEM = 4152.1M)
Start delay calculation using Signal Storm (mem=4152.133M)...
Delay calculation completed. (cpu=0:01:05 real=0:01:04 mem=4152.133M 0)
*** CDM Built up (cpu=0:16:19 real=0:16:19 mem= 4152.1M) ***
*info: DRV Fixing Iteration 1.
*info: Remaining violations:
*info: Max cap violations: 0
*info: Max tran violations: 0
*info: Prev Max cap violations: 8
*info: Prev Max tran violations: 22
*info:
*info: Completed fixing DRV (CPU Time = 0:22:06, Mem = 4469.09M).
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
Summary (cpu=22.10min real=21.15min mem=4469.1M)
------------------------------------------------------------
+--------------------+---------+
| Setup mode | all |
+--------------------+---------+
| WNS (ns):| -0.204 |
| TNS (ns):| -80.110 |
| Violating Paths:| 1363 |
| All Paths:| 85005 |
+--------------------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 0 (0) | 0.000 | 0 (0) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 59.473%
Routing Overflow: 0.01% H and 0.28% V
------------------------------------------------------------
**optDesign ... cpu = 0:58:55, real = 0:51:04, mem = 4469.1M **
Started binary server on port 48996
*** Starting optCritPath ***
*info: 40 io nets excluded
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
*info: 567 clock nets excluded
*info: 4 special nets excluded.
*info: 21 multi-driver nets excluded.
*info: 2406 no-driver nets excluded.
*info: 566 nets with fixed/cover wires excluded.
Density : 0.5947
Max route overflow : 0.0028
Current slack : -0.204 ns, density : 0.5947 End_Point: top/i_gmu_skein/datapathInst/r_reg_108_/D
Current slack : -0.204 ns, density : 0.5947 Worst_View: gmu_skein_slow_view End_Point: top/i_gmu_skein/datapathInst/r_reg_108_/D
Current slack : -0.204 ns, density : 0.5947 End_Point: top/i_gmu_skein/datapathInst/r_reg_108_/D
Current slack : -0.181 ns, density : 0.5947 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_135_/D
Current slack : -0.151 ns, density : 0.5947 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_384_/D
Current slack : -0.151 ns, density : 0.5947 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_384_/D
Current slack : -0.151 ns, density : 0.5947 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_384_/D
Current slack : -0.151 ns, density : 0.5947 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_384_/D
Current slack : -0.145 ns, density : 0.5947 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_375_/D
Current slack : -0.126 ns, density : 0.5947 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_385_/D
Current slack : -0.123 ns, density : 0.5947 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_481_/D
Current slack : -0.123 ns, density : 0.5947 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_481_/D
Current slack : -0.123 ns, density : 0.5947 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_481_/D
Current slack : -0.121 ns, density : 0.5946 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_181_/D
Current slack : -0.112 ns, density : 0.5946 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_178_/D
Current slack : -0.111 ns, density : 0.5946 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_178_/D
Current slack : -0.111 ns, density : 0.5946 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_178_/D
Current slack : -0.111 ns, density : 0.5946 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_178_/D
Current slack : -0.111 ns, density : 0.5946 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_178_/D
Current slack : -0.111 ns, density : 0.5946 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_178_/D
Current slack : -0.109 ns, density : 0.5947 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_359_/D
Current slack : -0.109 ns, density : 0.5947 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_359_/D
Current slack : -0.109 ns, density : 0.5947 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_359_/D
Current slack : -0.103 ns, density : 0.5947 Worst_View: gmu_blake_slow_view End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_300_/D
Current slack : -0.103 ns, density : 0.5947 End_Point: top/i_gmu_blake/datapath_gen/r_gen_output_reg_300_/D
Current slack : -0.105 ns, density : 0.5944 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_390_/D
Current slack : -0.100 ns, density : 0.5951 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_357_/D
Current slack : -0.100 ns, density : 0.5959 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_357_/D
Current slack : -0.102 ns, density : 0.5959 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_290_/D
Current slack : -0.102 ns, density : 0.5959 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_290_/D
Current slack : -0.102 ns, density : 0.5959 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_290_/D
Current slack : -0.102 ns, density : 0.5959 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_290_/D
Current slack : -0.100 ns, density : 0.5959 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_357_/D
Current slack : -0.096 ns, density : 0.5959 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_182_/D
Current slack : -0.096 ns, density : 0.5959 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_182_/D
Current slack : -0.092 ns, density : 0.5959 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_96_/D
Current slack : -0.092 ns, density : 0.5959 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_96_/D
Current slack : -0.092 ns, density : 0.5959 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_96_/D
Current slack : -0.092 ns, density : 0.5959 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_96_/D
Current slack : -0.092 ns, density : 0.5959 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_96_/D
Current slack : -0.092 ns, density : 0.5959 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_96_/D
Current slack : -0.085 ns, density : 0.5959 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_410_/D
Current slack : -0.085 ns, density : 0.5959 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_410_/D
Current slack : -0.085 ns, density : 0.5959 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_410_/D
Current slack : -0.084 ns, density : 0.5959 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_243_/D
Current slack : -0.084 ns, density : 0.5959 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_243_/D
Current slack : -0.084 ns, density : 0.5959 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_243_/D
Current slack : -0.084 ns, density : 0.5959 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_243_/D
Current slack : -0.084 ns, density : 0.5959 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_243_/D
Current slack : -0.081 ns, density : 0.5959 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_242_/D
Current slack : -0.081 ns, density : 0.5959 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_242_/D
Current slack : -0.081 ns, density : 0.5958 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_242_/D
Current slack : -0.075 ns, density : 0.5967 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_290_/D
Current slack : -0.075 ns, density : 0.5977 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_290_/D
Current slack : -0.075 ns, density : 0.5977 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_290_/D
Current slack : -0.074 ns, density : 0.5978 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_290_/D
Current slack : -0.074 ns, density : 0.5978 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_290_/D
Current slack : -0.074 ns, density : 0.5978 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_290_/D
Current slack : -0.074 ns, density : 0.5978 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_290_/D
Current slack : -0.076 ns, density : 0.5978 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_290_/D
Current slack : -0.076 ns, density : 0.5978 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_290_/D
Current slack : -0.076 ns, density : 0.5978 End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_290_/D
*** Starting refinePlace (0:13:08 mem=4370.9M) ***
default core: bins with density > 0.75 = 23.4 % ( 1813 / 7744 )
RPlace IncrNP: Rollback Lev = -3
RPlace: Density =1.030000, incremental np is triggered.
default core: bins with density > 0.75 = 23.8 % ( 1846 / 7744 )
RPlace postIncrNP: Density = 1.030000 -> 0.977401.
*** cpu time = 0:00:24.6.
move report: incrNP moves 40759 insts, mean move: 3.39 um, max move: 39.40 um
max move on inst (top/i_gmu_groestl/U3036): (510.40, 390.00) --> (531.80, 408.00)
Starting refinePlace ...
move report: placeLevelShifters moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Spread Effort: high, pre-route mode.
Finished Phase I. CPU Time = 0:00:35.2, Real Time = 0:00:36.0
move report: preRPlace moves 21006 insts, mean move: 0.72 um, max move: 7.00 um
max move on inst (top/i_gmu_skein/datapathInst/keygen_gen/key_reg_gen_4_output_reg_6_): (1094.80, 1326.00) --> (1087.80, 1326.00)
move report: rPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: overall moves 21006 insts, mean move: 0.72 um, max move: 7.00 um
max move on inst (top/i_gmu_skein/datapathInst/keygen_gen/key_reg_gen_4_output_reg_6_): (1094.80, 1326.00) --> (1087.80, 1326.00)
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 41.40 um
inst (top/i_gmu_groestl/U3036) with max move: (510.4, 390) -> (533.8, 408)
mean (X+Y) = 3.18 um
Total instances flipped for legalization: 63
Total instances moved : 45144
*** cpu=0:00:37.1 mem=4377.4M mem(used)=0.0M***
*** maximum move = 41.4um ***
*** Finished refinePlace (0:14:20 mem=4370.9M) ***
*** Done re-routing un-routed nets (4370.9M) ***
*** Starting delays update (0:14:23 mem=4370.9M) ***
*** Finished delays update (0:21:34 mem=4322.3M) ***
Current slack : -0.103 ns, density : 0.5978 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_293_/D
Current slack : -0.103 ns, density : 0.5978 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_293_/D
Current slack : -0.103 ns, density : 0.5978 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_293_/D
Current slack : -0.099 ns, density : 0.5978 Worst_View: gmu_groestl_slow_view End_Point: top/i_gmu_groestl/dp_fx2_256_rounds_pl_reg_output_reg_293_/D
*** Starting refinePlace (0:49:29 mem=4550.7M) ***
default core: bins with density > 0.75 = 24.4 % ( 1892 / 7744 )
Starting refinePlace ...
move report: placeLevelShifters moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Spread Effort: high, pre-route mode.
Finished Phase I. CPU Time = 0:00:26.0, Real Time = 0:00:26.0
move report: preRPlace moves 11305 insts, mean move: 0.46 um, max move: 5.40 um
max move on inst (top/i_gmu_skein/datapathInst/U10561): (1243.60, 1282.80) --> (1240.00, 1281.00)
move report: rPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: overall moves 11305 insts, mean move: 0.46 um, max move: 5.40 um
max move on inst (top/i_gmu_skein/datapathInst/U10561): (1243.60, 1282.80) --> (1240.00, 1281.00)
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 5.40 um
inst (top/i_gmu_skein/datapathInst/U10561) with max move: (1243.6, 1282.8) -> (1240, 1281)
mean (X+Y) = 0.46 um
Total instances moved : 11305
*** cpu=0:00:27.6 mem=4585.3M mem(used)=26.1M***
*** maximum move = 5.4um ***
*** Finished refinePlace (0:50:04 mem=4552.7M) ***
moveBlkTerm was implicitly turned on (since useM1).
*** Starting trialRoute (mem=4552.7M) ***
There are 0 pin guide points passed to trialRoute.
moveBlkTerm was implicitly turned on (since useM1).
Options: -moveBlkTerm -useM1 -handlePreroute -keepMarkedOptRoutes -noPinGuide
Nr of prerouted/Fixed nets = 607
There are 567 nets with 1 extra space.
Num blk terms moved = 949701.
routingBox: (100 200) (1874900 1874800)
coreBox: (148800 148800) (1726200 1726200)
There are 567 prerouted nets with extraSpace.
Number of multi-gpin terms=0, multi-gpins=0, moved blk term=191/179318
Phase 1a route (0:00:02.7 4657.8M):
Est net length = 1.556e+07um = 7.397e+06H + 8.167e+06V
Usage: (27.7%H 31.3%V) = (8.142e+06um 8.386e+06um) = (8136404 4659163)
Obstruct: 784147 = 288147 (16.7%H) + 496000 (28.8%V)
Overflow: 15841 = 5011 (0.35% H) + 10830 (0.88% V)
Number obstruct path=58939 reroute=0
There are 567 prerouted nets with extraSpace.
Phase 1b route (0:00:04.9 4657.8M):
Usage: (28.1%H 31.6%V) = (8.265e+06um 8.468e+06um) = (8258839 4704380)
Overflow: 43991 = 3258 (0.23% H) + 40733 (3.32% V)
There are 567 prerouted nets with extraSpace.
Phase 1c route (0:00:03.5 4657.8M):
Usage: (28.1%H 31.6%V) = (8.256e+06um 8.473e+06um) = (8250560 4707045)
Overflow: 37743 = 2781 (0.19% H) + 34962 (2.85% V)
Phase 1d route (0:00:02.8 4657.8M):
Usage: (28.1%H 31.6%V) = (8.258e+06um 8.477e+06um) = (8252349 4709587)
Overflow: 24570 = 829 (0.06% H) + 23741 (1.94% V)
Phase 1e route (0:00:02.0 4721.9M):
Usage: (28.1%H 31.6%V) = (8.270e+06um 8.482e+06um) = (8264272 4712275)
Overflow: 722 = 17 (0.00% H) + 704 (0.06% V)
Phase 1f route (0:00:01.7 4721.9M):
Usage: (28.1%H 31.6%V) = (8.270e+06um 8.482e+06um) = (8264076 4712316)
Overflow: 395 = 2 (0.00% H) + 393 (0.03% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-7: 0 0.00% 1 0.00%
-4: 0 0.00% 4 0.00%
-3: 0 0.00% 16 0.00%
-2: 0 0.00% 30 0.00%
-1: 2 0.00% 312 0.03%
--------------------------------------
0: 572 0.04% 6234 0.51%
1: 1956 0.14% 15090 1.23%
2: 4378 0.31% 23048 1.88%
3: 10382 0.72% 40752 3.32%
4: 14120 0.98% 67339 5.49%
5: 19267 1.34% 287758 23.46%
6: 28501 1.99% 129497 10.56%
7: 33499 2.34% 84020 6.85%
8: 43341 3.02% 75621 6.17%
9: 60353 4.21% 68750 5.60%
10: 63548 4.43% 76575 6.24%
11: 74505 5.19% 53982 4.40%
12: 166123 11.58% 46806 3.82%
13: 204754 14.27% 34030 2.77%
14: 119239 8.31% 29048 2.37%
15: 74495 5.19% 139310 11.36%
16: 70800 4.94% 37717 3.07%
17: 63446 4.42% 437 0.04%
18: 57694 4.02% 5900 0.48%
19: 47401 3.30% 15 0.00%
20: 276077 19.25% 4308 0.35%
Global route (cpu=17.7s real=18.0s 4657.8M)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Phase 1l route (0:00:23.8 4579.0M):
There are 567 prerouted nets with extraSpace.
*** After '-updateRemainTrks' operation:
Usage: (28.9%H 33.2%V) = (8.497e+06um 8.918e+06um) = (8491160 4954566)
Overflow: 3736 = 177 (0.01% H) + 3560 (0.29% V)
Congestion distribution:
Remain cntH cntV
--------------------------------------
-7: 0 0.00% 1 0.00%
-4: 0 0.00% 11 0.00%
-3: 1 0.00% 77 0.01%
-2: 24 0.00% 586 0.05%
-1: 141 0.01% 2573 0.21%
--------------------------------------
0: 868 0.06% 10236 0.83%
1: 2397 0.17% 20861 1.70%
2: 5195 0.36% 31101 2.54%
3: 11853 0.83% 48831 3.98%
4: 15920 1.11% 70337 5.73%
5: 21903 1.53% 286989 23.40%
6: 31431 2.19% 125894 10.26%
7: 37037 2.58% 79519 6.48%
8: 46686 3.25% 71157 5.80%
9: 62342 4.35% 64239 5.24%
10: 64778 4.52% 72439 5.91%
11: 74532 5.20% 50724 4.14%
12: 165371 11.53% 44041 3.59%
13: 203250 14.17% 31968 2.61%
14: 117331 8.18% 27791 2.27%
15: 71786 5.00% 138894 11.32%
16: 68263 4.76% 37723 3.08%
17: 60819 4.24% 413 0.03%
18: 55470 3.87% 5872 0.48%
19: 45246 3.15% 17 0.00%
20: 271809 18.95% 4306 0.35%
Num blk terms moved back = 943057
*** Completed Phase 1 route (0:00:46.6 4579.0M) ***
Total length: 1.620e+07um, number of vias: 2558307
M1(H) length: 1.107e+04um, number of vias: 972928
M2(V) length: 2.696e+06um, number of vias: 972230
M3(H) length: 3.916e+06um, number of vias: 360893
M4(V) length: 3.139e+06um, number of vias: 164427
M5(H) length: 3.326e+06um, number of vias: 78472
M6(V) length: 2.758e+06um, number of vias: 8635
M7(H) length: 3.502e+05um, number of vias: 722
M8(V) length: 8.862e+03um
*** Completed Phase 2 route (0:00:43.0 4555.7M) ***
*** Finished all Phases (cpu=0:01:31 mem=4555.7M) ***
Peak Memory Usage was 4665.9M
*** Finished trialRoute (cpu=0:01:34 mem=4555.7M) ***
*** Starting delays update (0:52:33 mem=3923.8M) ***
*** Finished delays update (1:01:32 mem=4517.2M) ***
post refinePlace cleanup
post refinePlace cleanup
** Core optimization cpu=0:31:19 real=0:29:40 (18635 evaluations)
*** Done optCritPath (cpu=1:33:59 real=1:09:31 mem=4541.23M) ***
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
Summary (cpu=62.44min real=69.60min mem=4541.2M)
------------------------------------------------------------
+--------------------+---------+
| Setup mode | all |
+--------------------+---------+
| WNS (ns):| -0.101 |
| TNS (ns):| -34.983 |
| Violating Paths:| 920 |
| All Paths:| 85005 |
+--------------------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 1 (1) | -0.002 | 1 (1) |
| max_tran | 2 (5) | -0.092 | 2 (5) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 60.175%
Routing Overflow: 0.01% H and 0.29% V
------------------------------------------------------------
**optDesign ... cpu = 2:33:43, real = 2:01:13, mem = 4541.2M **
Reported timing to dir timingReports_final
**optDesign ... cpu = 2:33:52, real = 2:01:22, mem = 4221.3M **
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
optDesign Final Summary
------------------------------------------------------------
+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| -0.101 | -0.101 | 0.536 | 0.417 | 18.854 | 16.472 |
| TNS (ns):| -34.983 | -34.983 | 0.000 | 0.000 | 0.000 | 0.000 |
| Violating Paths:| 920 | 920 | 0 | 0 | 0 | 0 |
| All Paths:| 85005 | 46605 | 63302 | 19 | 2 | 15 |
+--------------------+---------+---------+---------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 1 (1) | -0.002 | 1 (1) |
| max_tran | 2 (5) | -0.092 | 2 (5) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 60.175%
Routing Overflow: 0.01% H and 0.29% V
------------------------------------------------------------
**optDesign ... cpu = 2:36:28, real = 2:02:51, mem = 4221.3M **
*info: Setting setup target slack to -0.050
*info: Hold target slack is 0.000
**INFO : removing temp dont-use cells (LVT only flow version : 4)
Deleting the dont_use list
*** Finished optDesign ***
timeDesign -reportOnly -expandedViews -outDir timingReports_final -prefix shabziger.postCTS-opt.expV
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
timeDesign Summary
------------------------------------------------------------
+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| -0.101 | -0.101 | 0.536 | 0.417 | 18.854 | 16.472 |
| TNS (ns):| -34.983 | -34.983 | 0.000 | 0.000 | 0.000 | 0.000 |
| Violating Paths:| 920 | 920 | 0 | 0 | 0 | 0 |
| All Paths:| 85005 | 46605 | 63302 | 19 | 2 | 15 |
+--------------------+---------+---------+---------+---------+---------+---------+
|dummy_slow_view | 7.961 | 7.961 | 9.150 | 8.817 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5131 | 2517 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_blake_slow_view| 0.036 | 0.036 | 3.916 | 3.817 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 8290 | 4385 | 3887 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_groestl_slow_view
| | -0.024 | -0.024 | 2.750 | 2.417 | N/A | N/A |
| | -0.054 | -0.054 | 0.000 | 0.000 | N/A | N/A |
| | 6 | 6 | 0 | 0 | N/A | N/A |
| | 8236 | 4070 | 4148 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_jh_slow_view | 0.051 | 0.051 | 2.150 | 1.817 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 8801 | 4640 | 4143 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_keccak_slow_view
| | -0.011 | -0.011 | 0.755 | 0.817 | N/A | N/A |
| | -0.023 | -0.023 | 0.000 | 0.000 | N/A | N/A |
| | 5 | 5 | 0 | 0 | N/A | N/A |
| | 8346 | 4125 | 4203 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_sha2_slow_view | 0.129 | 0.129 | 2.504 | 2.317 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 7204 | 3554 | 3632 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_skein_slow_view| -0.028 | -0.028 | 1.656 | 1.617 | N/A | N/A |
| | -0.062 | -0.062 | 0.000 | 0.000 | N/A | N/A |
| | 4 | 4 | 0 | 0 | N/A | N/A |
| | 9002 | 4517 | 4467 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_blake_slow_view | -0.069 | -0.069 | 3.050 | 2.717 | N/A | N/A |
| | -3.057 | -3.057 | 0.000 | 0.000 | N/A | N/A |
| | 89 | 89 | 0 | 0 | N/A | N/A |
| | 9724 | 5498 | 4208 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_groestl_slow_view
| | -0.101 | -0.101 | 1.079 | 0.917 | N/A | N/A |
| | -28.894 | -28.894 | 0.000 | 0.000 | N/A | N/A |
| | 679 | 679 | 0 | 0 | N/A | N/A |
| | 9252 | 5088 | 4146 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_jh_slow_view | -0.049 | -0.049 | 0.750 | 0.417 | N/A | N/A |
| | -0.098 | -0.098 | 0.000 | 0.000 | N/A | N/A |
| | 5 | 5 | 0 | 0 | N/A | N/A |
| | 10269 | 5853 | 4398 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_keccak_slow_view| -0.069 | -0.069 | 0.750 | 0.417 | N/A | N/A |
| | -2.079 | -2.079 | 0.000 | 0.000 | N/A | N/A |
| | 102 | 102 | 0 | 0 | N/A | N/A |
| | 9926 | 5702 | 4206 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_sha2_slow_view | -0.025 | -0.025 | 0.536 | 0.617 | N/A | N/A |
| | -0.046 | -0.046 | 0.000 | 0.000 | N/A | N/A |
| | 4 | 4 | 0 | 0 | N/A | N/A |
| | 7986 | 4238 | 3730 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_skein_slow_view | -0.056 | -0.056 | 2.795 | 4.317 | N/A | N/A |
| | -0.669 | -0.669 | 0.000 | 0.000 | N/A | N/A |
| | 26 | 26 | 0 | 0 | N/A | N/A |
| | 10156 | 5551 | 4587 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ram1_slow_view | 5.299 | 5.299 | 9.150 | 8.817 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5237 | 2623 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ram2_slow_view | 5.059 | 5.059 | 9.150 | 8.817 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5237 | 2623 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ram3_slow_view | 3.453 | 3.453 | 9.150 | 8.817 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5240 | 2626 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|test_slow_view | 13.432 | 13.432 | 14.124 | 18.810 | 18.854 | 16.472 |
| | 0.000 | 0.000 | 0.000 | 0.000 | 0.000 | 0.000 |
| | 0 | 0 | 0 | 0 | 0 | 0 |
| | 85005 | 46605 | 63302 | 19 | 2 | 15 |
+--------------------+---------+---------+---------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 1 (1) | -0.002 | 1 (1) |
| max_tran | 2 (5) | -0.092 | 2 (5) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 60.175%
------------------------------------------------------------
Reported timing to dir timingReports_final
Total CPU time: 229.12 sec
Total Real time: 172.0 sec
Total Memory Usage: 4206.019531 Mbytes
saveDesign save/chip_shabziger_postCTS.enc
Redoing specifyClockTree ...
Checking spec file integrity...
**WARN: (ENCSYT-3036): Design directory save/chip_shabziger_postCTS.enc.dat exists, rename it to save/chip_shabziger_postCTS.enc.dat.tmp.
If saveDesign succeeds, it will be deleted.
Writing Netlist "save/chip_shabziger_postCTS.enc.dat/shabziger_chip.v.gz" ...
Saving clock tree spec file 'save/chip_shabziger_postCTS.enc.dat/shabziger_chip.ctstch' ...
Saving configuration ...
Saving preference file save/chip_shabziger_postCTS.enc.dat/enc.pref.tcl ...
Saving floorplan ...
Saving Drc markers ...
... 8 Drc markers are saved ...
Saving placement ...
*** Completed savePlace (cpu=0:00:00.4 real=0:00:01.0 mem=4204.0M) ***
Saving route ...
*** Completed saveRoute (cpu=0:00:05.6 real=0:00:12.0 mem=4204.0M) ***
Writing DEF file 'save/chip_shabziger_postCTS.enc.dat/shabziger_chip.def.gz', current time is Thu Sep 29 23:02:23 2011 ...
unitPerMicron=1000, dbgMicronPerDBU=0.001000, unitPerDBU=1.000000
DEF file 'save/chip_shabziger_postCTS.enc.dat/shabziger_chip.def.gz' is written, current time is Thu Sep 29 23:02:24 2011 ...
*** Completed saveYieldMap (cpu=: 0:00:00.0 real=0:00:00.0 mem=: 0.000M) ***
setNanoRouteMode -quiet -routeInsertAntennaDiode 1
setNanoRouteMode -quiet -routeWithTimingDriven 1
setNanoRouteMode -quiet -drouteStartIteration default
setNanoRouteMode -quiet -routeTopRoutingLayer default
setNanoRouteMode -quiet -routeBottomRoutingLayer default
setNanoRouteMode -quiet -drouteEndIteration default
setNanoRouteMode -quiet -routeWithTimingDriven true
setNanoRouteMode -quiet -routeWithSiDriven false
routeDesign -globalDetail
Begin checking placement ... (start mem=4204.0M, init mem=4204.0M)
*info: Placed = 252081
*info: Unplaced = 0
Placement Density:60.17%(1135020/1886211)
Finished checkPlace (cpu: total=0:00:02.8, vio checks=0:00:00.2; mem=4204.0M)
changeUseClockNetStatus Option : -noFixedNetWires
*** Changed status on (566) nets in Clock.
*** End changeUseClockNetStatus (cpu=0:00:00.0, real=0:00:00.0, mem=4204.0M) ***
Net ClkxCI has less one routable term.
Start route 173 clock nets ...
changeUseClockNetStatus Option : -noFixedNetWires
*** Changed status on (0) nets in Clock.
*** End changeUseClockNetStatus (cpu=0:00:00.0, real=0:00:00.0, mem=4204.0M) ***
globalDetailRoute
#Start globalDetailRoute on Thu Sep 29 23:03:05 2011
#
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_0 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_1 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_2 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_3 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_4 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_5 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_6 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_7 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_8 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_9 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_10 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_11 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_12 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_13 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_14 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_15 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_16 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_17 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_18 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34 Repeated 20 times. Will be suppressed.) Power/Ground pin VSSIO of instance fillperi_N_19 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRDB-733) PIN AlgSelxSI[0] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN AlgSelxSI[1] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN AlgSelxSI[2] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN AlgSelxSI[3] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN ClkDxCI in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN ClkxCI in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN CoreScanEnxTI in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN CoreScanInxTI in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[0] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[10] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[11] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[12] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[13] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[14] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[15] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[1] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[2] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[3] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[4] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733 Repeated 20 times. Will be suppressed.) PIN DataOutxDO[5] in CELL_VIEW shabziger_chip,init does not have physical port
#NanoRoute Version v10.12-s010 NR110720-1815/10_10_USR2-UB
#Using multithreading with 8 threads.
# ME1 H Track-Pitch = 0.200 Line-2-Via Pitch = 0.185
# ME2 V Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME3 H Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME4 V Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME5 H Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME6 V Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME7 H Track-Pitch = 0.400 Line-2-Via Pitch = 0.400
# ME8 V Track-Pitch = 4.000 Line-2-Via Pitch = 4.000
#Merging special wires using 8 threads...
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (1323.690 572.640) on ME1 for NET top/ClkxC__L6_N0. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (1390.350 736.565) on ME1 for NET top/ClkxC__L6_N1. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (1385.350 749.035) on ME1 for NET top/ClkxC__L6_N1. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (1427.750 885.835) on ME1 for NET top/ClkxC__L6_N10. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (1398.550 851.765) on ME1 for NET top/ClkxC__L6_N10. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (1459.750 876.965) on ME1 for NET top/ClkxC__L6_N12. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (1552.950 815.765) on ME1 for NET top/ClkxC__L6_N19. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (1549.550 810.235) on ME1 for NET top/ClkxC__L6_N19. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (1449.750 722.165) on ME1 for NET top/ClkxC__L6_N2. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (974.105 808.560) on ME1 for NET top/ClkxC__L6_N25. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (969.350 808.565) on ME1 for NET top/ClkxC__L6_N25. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (859.350 783.365) on ME1 for NET top/ClkxC__L6_N27. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (892.750 777.835) on ME1 for NET top/ClkxC__L6_N27. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (908.310 723.880) on ME1 for NET top/ClkxC__L6_N28. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (978.510 808.520) on ME1 for NET top/ClkxC__L6_N31. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (1034.505 687.840) on ME1 for NET top/ClkxC__L6_N36. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (1024.510 686.120) on ME1 for NET top/ClkxC__L6_N36. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (1018.310 684.280) on ME1 for NET top/ClkxC__L6_N36. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (1035.750 686.165) on ME1 for NET top/ClkxC__L6_N36. The NET is considered partially routed.
#WARNING (NRDB-1005 Repeated 20 times. Will be suppressed.) Can not establish connection to PIN CK at (1030.110 686.120) on ME1 for NET top/ClkxC__L6_N36. The NET is considered partially routed.
#WARNING (EMS-27) Message (NRDB-1005) has exceeded the current message display limit of 20.
#To increase the message display limit, refer to the product command reference manual.
#253 routed nets are extracted.
# 173 (0.06%) extracted nets are partially routed.
#313 routed nets are imported.
#283117 routed nets are fixed|skipped|trivial (not extracted).
#Total number of nets = 283683.
#Number of eco nets is 173
#
#Start data preparation...
#Force regenerating Ggrids.
#Auto generating G-grids with size=15 tracks, using layer ME2's pitch = 0.200.
#Using automatically generated G-grids.
#
#Data preparation is done on Thu Sep 29 23:03:20 2011
#
#Analyzing routing resource...
#Routing resource analysis is done on Thu Sep 29 23:03:23 2011
#
# Resource Analysis:
#
# Routing #Avail #Track #Total %Gcell
# Layer Direction Track Blocked Gcell Blocked
# --------------------------------------------------------------
# Metal 1 H 5808 3565 391250 74.22%
# Metal 2 V 5718 3657 391250 43.74%
# Metal 3 H 5885 3489 391250 36.36%
# Metal 4 V 5858 3516 391250 42.89%
# Metal 5 H 7164 2209 391250 22.09%
# Metal 6 V 7101 2273 391250 29.79%
# Metal 7 H 2749 1937 391250 24.29%
# Metal 8 V 239 228 391250 61.74%
# --------------------------------------------------------------
# Total 40525 36.22% 3130000 41.89%
#
# 567 nets (0.20%) with 1 preferred extra spacing.
#
#
#cpu time = 00:00:04, elapsed time = 00:00:04, memory = 4409.00 (Mb)
#
#start global routing iteration 1...
#cpu time = 00:00:02, elapsed time = 00:00:01, memory = 4409.00 (Mb)
#
#start global routing iteration 2...
#cpu time = 00:00:01, elapsed time = 00:00:01, memory = 4424.00 (Mb)
#
#start global routing iteration 3...
#cpu time = 00:00:05, elapsed time = 00:00:02, memory = 4410.00 (Mb)
#
#
# Congestion Analysis: (blocked Gcells are excluded)
#
# OverCon OverCon
# #Gcell #Gcell %Gcell
# Layer (1) (2) OverCon
# ----------------------------------------------
# Metal 1 179(0.12%) 0(0.00%) (0.12%)
# Metal 2 909(0.37%) 44(0.02%) (0.39%)
# Metal 3 0(0.00%) 0(0.00%) (0.00%)
# Metal 4 127(0.05%) 1(0.00%) (0.05%)
# Metal 5 0(0.00%) 0(0.00%) (0.00%)
# Metal 6 0(0.00%) 0(0.00%) (0.00%)
# Metal 7 0(0.00%) 0(0.00%) (0.00%)
# Metal 8 0(0.00%) 0(0.00%) (0.00%)
# ----------------------------------------------
# Total 1215(0.06%) 45(0.00%) (0.06%)
#
# The worst congested Gcell overcon (routing demand over resource in number of tracks) = 2
#
#Complete Global Routing.
#Total number of nets with non-default rule or having extra spacing = 567
#Total wire length = 184996 um.
#Total half perimeter of net bounding box = 92540 um.
#Total wire length on LAYER ME1 = 270 um.
#Total wire length on LAYER ME2 = 3690 um.
#Total wire length on LAYER ME3 = 97238 um.
#Total wire length on LAYER ME4 = 83755 um.
#Total wire length on LAYER ME5 = 1 um.
#Total wire length on LAYER ME6 = 42 um.
#Total wire length on LAYER ME7 = 0 um.
#Total wire length on LAYER ME8 = 0 um.
#Total number of vias = 70307
#Up-Via Summary (total 70307):
#
#-----------------------
# Metal 1 22259
# Metal 2 21874
# Metal 3 26154
# Metal 4 10
# Metal 5 10
#-----------------------
# 70307
#
#Max overcon = 2 tracks.
#Total overcon = 0.06%.
#Worst layer Gcell overcon rate = 0.05%.
#Cpu time = 00:00:22
#Elapsed time = 00:00:16
#Increased memory = 22.00 (Mb)
#Total memory = 4362.00 (Mb)
#Peak memory = 4658.00 (Mb)
#Using multithreading with 8 threads.
#
#Start Detail Routing...
#start initial detail routing ...
# completing 10% with 13 violations
# elapsed time = 00:00:10, memory = 4518.00 (Mb)
# completing 20% with 14 violations
# elapsed time = 00:00:16, memory = 4496.00 (Mb)
# completing 30% with 12 violations
# elapsed time = 00:00:24, memory = 4523.00 (Mb)
# completing 40% with 19 violations
# elapsed time = 00:00:33, memory = 4526.00 (Mb)
# completing 50% with 16 violations
# elapsed time = 00:00:41, memory = 4498.00 (Mb)
# completing 60% with 15 violations
# elapsed time = 00:00:48, memory = 4528.00 (Mb)
# completing 70% with 12 violations
# elapsed time = 00:00:57, memory = 4526.00 (Mb)
# completing 80% with 10 violations
# elapsed time = 00:01:06, memory = 4511.00 (Mb)
# completing 90% with 8 violations
# elapsed time = 00:01:13, memory = 4540.00 (Mb)
# completing 100% with 8 violations
# elapsed time = 00:01:23, memory = 4442.00 (Mb)
# ECO: 23.2% of the total area was rechecked for DRC, and 5.7% required routing.
# number of violations = 8
#45.8% of the total area is being checked for drcs
#45.8% of the total area was checked
# number of violations = 14
#cpu time = 00:06:14, elapsed time = 00:02:06, memory = 4394.00 (Mb)
#start 1st optimization iteration ...
# number of violations = 14
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 4392.00 (Mb)
#start 2nd optimization iteration ...
# number of violations = 14
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 4392.00 (Mb)
#start 3rd optimization iteration ...
# number of violations = 8
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 4392.00 (Mb)
#start 4th optimization iteration ...
# number of violations = 8
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 4392.00 (Mb)
#start 5th optimization iteration ...
# number of violations = 8
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 4392.00 (Mb)
#Complete Detail Routing.
#Total number of nets with non-default rule or having extra spacing = 567
#Total wire length = 184183 um.
#Total half perimeter of net bounding box = 92540 um.
#Total wire length on LAYER ME1 = 274 um.
#Total wire length on LAYER ME2 = 3756 um.
#Total wire length on LAYER ME3 = 96175 um.
#Total wire length on LAYER ME4 = 83935 um.
#Total wire length on LAYER ME5 = 1 um.
#Total wire length on LAYER ME6 = 42 um.
#Total wire length on LAYER ME7 = 0 um.
#Total wire length on LAYER ME8 = 0 um.
#Total number of vias = 70756
#Up-Via Summary (total 70756):
#
#-----------------------
# Metal 1 22336
# Metal 2 21928
# Metal 3 26472
# Metal 4 10
# Metal 5 10
#-----------------------
# 70756
#
#Total number of DRC violations = 8
#Total number of violations on LAYER ME1 = 0
#Total number of violations on LAYER ME2 = 0
#Total number of violations on LAYER ME3 = 0
#Total number of violations on LAYER ME4 = 8
#Total number of violations on LAYER ME5 = 0
#Total number of violations on LAYER ME6 = 0
#Total number of violations on LAYER ME7 = 0
#Total number of violations on LAYER ME8 = 0
#Cpu time = 00:06:17
#Elapsed time = 00:02:09
#Increased memory = 18.00 (Mb)
#Total memory = 4380.00 (Mb)
#Peak memory = 4658.00 (Mb)
#detailRoute Statistics:
#Cpu time = 00:06:17
#Elapsed time = 00:02:09
#Increased memory = 18.00 (Mb)
#Total memory = 4380.00 (Mb)
#Peak memory = 4658.00 (Mb)
#
#globalDetailRoute statistics:
#Cpu time = 00:06:47
#Elapsed time = 00:02:33
#Increased memory = -338.00 (Mb)
#Total memory = 3866.00 (Mb)
#Peak memory = 4658.00 (Mb)
#Number of warnings = 61
#Total number of warnings = 103
#Number of fails = 0
#Total number of fails = 0
#Complete globalDetailRoute on Thu Sep 29 23:05:39 2011
#
globalDetailRoute
#Start globalDetailRoute on Thu Sep 29 23:05:41 2011
#
#Generating timing graph information, please wait...
#281277 total nets, 566 already routed, 566 will ignore in trialRoute
#Dump tif for version 2.1
#Write timing file took: cpu time = 00:10:56, elapsed time = 00:10:01, memory = 3865.00 (Mb)
#Done generating timing graph information.
#Start reading timing information from file .timing_file_9079.tif.gz ...
#Read in timing information for 40 ports, 273905 instances from timing file .timing_file_9079.tif.gz.
#NanoRoute Version v10.12-s010 NR110720-1815/10_10_USR2-UB
#Using multithreading with 8 threads.
# ME1 H Track-Pitch = 0.200 Line-2-Via Pitch = 0.185
# ME2 V Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME3 H Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME4 V Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME5 H Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME6 V Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME7 H Track-Pitch = 0.400 Line-2-Via Pitch = 0.400
# ME8 V Track-Pitch = 4.000 Line-2-Via Pitch = 4.000
#Merging special wires using 8 threads...
#Number of eco nets is 0
#
#Start data preparation...
#Force regenerating Ggrids.
#Auto generating G-grids with size=15 tracks, using layer ME2's pitch = 0.200.
#Using automatically generated G-grids.
#
#Data preparation is done on Thu Sep 29 23:17:29 2011
#
#Analyzing routing resource...
#Routing resource analysis is done on Thu Sep 29 23:17:32 2011
#
# Resource Analysis:
#
# Routing #Avail #Track #Total %Gcell
# Layer Direction Track Blocked Gcell Blocked
# --------------------------------------------------------------
# Metal 1 H 5808 3565 391250 74.22%
# Metal 2 V 5718 3657 391250 43.74%
# Metal 3 H 5885 3489 391250 36.36%
# Metal 4 V 5858 3516 391250 42.89%
# Metal 5 H 7164 2209 391250 22.09%
# Metal 6 V 7101 2273 391250 29.79%
# Metal 7 H 2749 1937 391250 24.29%
# Metal 8 V 239 228 391250 61.74%
# --------------------------------------------------------------
# Total 40525 36.22% 3130000 41.89%
#
# 567 nets (0.20%) with 1 preferred extra spacing.
#
#
#cpu time = 00:00:05, elapsed time = 00:00:05, memory = 4055.00 (Mb)
#
#start global routing iteration 1...
#
#setting timing driven routing constraints ...
#
#cpu time = 00:01:07, elapsed time = 00:00:34, memory = 4128.00 (Mb)
#
#start global routing iteration 2...
#cpu time = 00:01:26, elapsed time = 00:00:17, memory = 4127.00 (Mb)
#
#start global routing iteration 3...
#cpu time = 00:01:24, elapsed time = 00:01:24, memory = 4281.00 (Mb)
#
#start global routing iteration 4...
#cpu time = 00:12:09, elapsed time = 00:02:12, memory = 4221.00 (Mb)
#
#
# Congestion Analysis: (blocked Gcells are excluded)
#
# OverCon OverCon OverCon OverCon
# #Gcell #Gcell #Gcell #Gcell %Gcell
# Layer (1-4) (5-8) (9-12) (13-16) OverCon
# --------------------------------------------------------------------------
# Metal 1 1(0.00%) 0(0.00%) 0(0.00%) 0(0.00%) (0.00%)
# Metal 2 27076(11.0%) 6586(2.67%) 736(0.30%) 39(0.02%) (13.9%)
# Metal 3 1465(0.59%) 3(0.00%) 0(0.00%) 0(0.00%) (0.59%)
# Metal 4 133(0.05%) 1(0.00%) 0(0.00%) 0(0.00%) (0.05%)
# Metal 5 23(0.01%) 0(0.00%) 0(0.00%) 0(0.00%) (0.01%)
# Metal 6 12(0.00%) 0(0.00%) 0(0.00%) 0(0.00%) (0.00%)
# Metal 7 14(0.00%) 0(0.00%) 0(0.00%) 0(0.00%) (0.00%)
# Metal 8 0(0.00%) 0(0.00%) 0(0.00%) 0(0.00%) (0.00%)
# --------------------------------------------------------------------------
# Total 28724(1.47%) 6590(0.34%) 736(0.04%) 39(0.00%) (1.85%)
#
# The worst congested Gcell overcon (routing demand over resource in number of tracks) = 16
#
#Complete Global Routing.
#Total number of nets with non-default rule or having extra spacing = 1576
#Total wire length = 16311316 um.
#Total half perimeter of net bounding box = 14221684 um.
#Total wire length on LAYER ME1 = 23609 um.
#Total wire length on LAYER ME2 = 2491356 um.
#Total wire length on LAYER ME3 = 3557365 um.
#Total wire length on LAYER ME4 = 3056555 um.
#Total wire length on LAYER ME5 = 3624339 um.
#Total wire length on LAYER ME6 = 2759922 um.
#Total wire length on LAYER ME7 = 599967 um.
#Total wire length on LAYER ME8 = 198203 um.
#Total number of vias = 2092663
#Up-Via Summary (total 2092663):
#
#-----------------------
# Metal 1 837760
# Metal 2 731974
# Metal 3 280258
# Metal 4 135659
# Metal 5 71640
# Metal 6 27722
# Metal 7 7650
#-----------------------
# 2092663
#
#Max overcon = 16 tracks.
#Total overcon = 1.85%.
#Worst layer Gcell overcon rate = 0.59%.
#Cpu time = 00:16:24
#Elapsed time = 00:04:44
#Increased memory = 158.00 (Mb)
#Total memory = 4150.00 (Mb)
#Peak memory = 4658.00 (Mb)
#Using multithreading with 8 threads.
#
#Start Detail Routing...
#start initial detail routing ...
# completing 10% with 7196 violations
# elapsed time = 00:01:09, memory = 4444.00 (Mb)
# completing 20% with 9629 violations
# elapsed time = 00:02:10, memory = 4416.00 (Mb)
# completing 30% with 10014 violations
# elapsed time = 00:03:00, memory = 4454.00 (Mb)
# completing 40% with 10432 violations
# elapsed time = 00:04:11, memory = 4439.00 (Mb)
# completing 50% with 10583 violations
# elapsed time = 00:05:20, memory = 4407.00 (Mb)
# completing 60% with 11322 violations
# elapsed time = 00:06:04, memory = 4445.00 (Mb)
# completing 70% with 11736 violations
# elapsed time = 00:07:13, memory = 4456.00 (Mb)
# completing 80% with 12173 violations
# elapsed time = 00:08:24, memory = 4473.00 (Mb)
# completing 90% with 9585 violations
# elapsed time = 00:09:13, memory = 4512.00 (Mb)
# completing 100% with 4600 violations
# elapsed time = 00:10:18, memory = 4283.00 (Mb)
# number of violations = 4600
#cpu time = 01:13:20, elapsed time = 00:10:20, memory = 4233.00 (Mb)
#start 1st optimization iteration ...
# number of violations = 1124
#cpu time = 00:02:41, elapsed time = 00:00:31, memory = 4233.00 (Mb)
#start 2nd optimization iteration ...
# number of violations = 911
#cpu time = 00:00:31, elapsed time = 00:00:06, memory = 4233.00 (Mb)
#start 3rd optimization iteration ...
# number of violations = 750
#cpu time = 00:00:23, elapsed time = 00:00:05, memory = 4233.00 (Mb)
#start 4th optimization iteration ...
# number of violations = 723
#cpu time = 00:00:19, elapsed time = 00:00:05, memory = 4233.00 (Mb)
#start 5th optimization iteration ...
# number of violations = 676
#cpu time = 00:00:18, elapsed time = 00:00:05, memory = 4233.00 (Mb)
#start 6th optimization iteration ...
# number of violations = 658
#cpu time = 00:00:19, elapsed time = 00:00:05, memory = 4233.00 (Mb)
#start 7th optimization iteration ...
# number of violations = 640
#cpu time = 00:00:18, elapsed time = 00:00:05, memory = 4233.00 (Mb)
#start 8th optimization iteration ...
# number of violations = 638
#cpu time = 00:00:17, elapsed time = 00:00:04, memory = 4236.00 (Mb)
#start 9th optimization iteration ...
# number of violations = 631
#cpu time = 00:00:17, elapsed time = 00:00:04, memory = 4236.00 (Mb)
#start 10th optimization iteration ...
# number of violations = 614
#cpu time = 00:00:16, elapsed time = 00:00:04, memory = 4236.00 (Mb)
#start 11th optimization iteration ...
# number of violations = 607
#cpu time = 00:00:30, elapsed time = 00:00:07, memory = 4236.00 (Mb)
#start 12th optimization iteration ...
# number of violations = 603
#cpu time = 00:00:29, elapsed time = 00:00:07, memory = 4236.00 (Mb)
#start 13th optimization iteration ...
# number of violations = 600
#cpu time = 00:00:29, elapsed time = 00:00:07, memory = 4236.00 (Mb)
#start 14th optimization iteration ...
# number of violations = 597
#cpu time = 00:00:28, elapsed time = 00:00:07, memory = 4236.00 (Mb)
#start 15th optimization iteration ...
# number of violations = 529
#cpu time = 00:00:31, elapsed time = 00:00:07, memory = 4236.00 (Mb)
#start 16th optimization iteration ...
# number of violations = 520
#cpu time = 00:00:43, elapsed time = 00:00:09, memory = 4236.00 (Mb)
#start 17th optimization iteration ...
# number of violations = 512
#cpu time = 00:00:40, elapsed time = 00:00:09, memory = 4236.00 (Mb)
#start 18th optimization iteration ...
# number of violations = 514
#cpu time = 00:00:41, elapsed time = 00:00:09, memory = 4236.00 (Mb)
#start 19th optimization iteration ...
# number of violations = 509
#cpu time = 00:00:41, elapsed time = 00:00:09, memory = 4236.00 (Mb)
#start 20th optimization iteration ...
# number of violations = 511
#cpu time = 00:00:42, elapsed time = 00:00:09, memory = 4236.00 (Mb)
#Complete Detail Routing.
#Total number of nets with non-default rule or having extra spacing = 1576
#Total wire length = 16455445 um.
#Total half perimeter of net bounding box = 14221684 um.
#Total wire length on LAYER ME1 = 181853 um.
#Total wire length on LAYER ME2 = 2606678 um.
#Total wire length on LAYER ME3 = 3567002 um.
#Total wire length on LAYER ME4 = 3069397 um.
#Total wire length on LAYER ME5 = 3623574 um.
#Total wire length on LAYER ME6 = 2726403 um.
#Total wire length on LAYER ME7 = 509425 um.
#Total wire length on LAYER ME8 = 171113 um.
#Total number of vias = 2800103
#Total number of multi-cut vias = 27534 ( 1.0%)
#Total number of single cut vias = 2772569 ( 99.0%)
#Up-Via Summary (total 2800103):
# single-cut multi-cut Total
#-----------------------------------------------------------
# Metal 1 996483 (100.0%) 0 ( 0.0%) 996483
# Metal 2 1061047 (100.0%) 0 ( 0.0%) 1061047
# Metal 3 381010 (100.0%) 0 ( 0.0%) 381010
# Metal 4 199980 (100.0%) 44 ( 0.0%) 200024
# Metal 5 125164 (100.0%) 0 ( 0.0%) 125164
# Metal 6 0 ( 0.0%) 27490 (100.0%) 27490
# Metal 7 8885 (100.0%) 0 ( 0.0%) 8885
#-----------------------------------------------------------
# 2772569 ( 99.0%) 27534 ( 1.0%) 2800103
#
#Total number of DRC violations = 511
#Total number of violations on LAYER ME1 = 18
#Total number of violations on LAYER ME2 = 156
#Total number of violations on LAYER ME3 = 98
#Total number of violations on LAYER ME4 = 239
#Total number of violations on LAYER ME5 = 0
#Total number of violations on LAYER ME6 = 0
#Total number of violations on LAYER ME7 = 0
#Total number of violations on LAYER ME8 = 0
#Cpu time = 01:25:05
#Elapsed time = 00:13:08
#Increased memory = 67.00 (Mb)
#Total memory = 4217.00 (Mb)
#Peak memory = 4968.00 (Mb)
#
#Start Post Routing Optimization.
#start 1st post routing optimization iteration ...
# number of DRC violations = 511
#cpu time = 00:05:26, elapsed time = 00:01:45, memory = 4081.00 (Mb)
#start 2nd post routing optimization iteration ...
# number of DRC violations = 511
#cpu time = 00:05:32, elapsed time = 00:02:22, memory = 4136.00 (Mb)
#start 3rd post routing optimization iteration ...
# number of DRC violations = 511
#cpu time = 00:04:29, elapsed time = 00:01:20, memory = 4135.00 (Mb)
#Complete Post Routing Optimization.
#Cpu time = 00:15:29
#Elapsed time = 00:05:30
#Increased memory = -82.00 (Mb)
#Total memory = 4135.00 (Mb)
#Peak memory = 4975.00 (Mb)
#Total number of nets with non-default rule or having extra spacing = 1576
#Total wire length = 16455445 um.
#Total half perimeter of net bounding box = 14221684 um.
#Total wire length on LAYER ME1 = 181853 um.
#Total wire length on LAYER ME2 = 2606678 um.
#Total wire length on LAYER ME3 = 3567002 um.
#Total wire length on LAYER ME4 = 3069397 um.
#Total wire length on LAYER ME5 = 3623574 um.
#Total wire length on LAYER ME6 = 2726403 um.
#Total wire length on LAYER ME7 = 509425 um.
#Total wire length on LAYER ME8 = 171113 um.
#Total number of vias = 2800103
#Total number of multi-cut vias = 27534 ( 1.0%)
#Total number of single cut vias = 2772569 ( 99.0%)
#Up-Via Summary (total 2800103):
# single-cut multi-cut Total
#-----------------------------------------------------------
# Metal 1 996483 (100.0%) 0 ( 0.0%) 996483
# Metal 2 1061047 (100.0%) 0 ( 0.0%) 1061047
# Metal 3 381010 (100.0%) 0 ( 0.0%) 381010
# Metal 4 199980 (100.0%) 44 ( 0.0%) 200024
# Metal 5 125164 (100.0%) 0 ( 0.0%) 125164
# Metal 6 0 ( 0.0%) 27490 (100.0%) 27490
# Metal 7 8885 (100.0%) 0 ( 0.0%) 8885
#-----------------------------------------------------------
# 2772569 ( 99.0%) 27534 ( 1.0%) 2800103
#
#Total number of DRC violations = 511
#Total number of violations on LAYER ME1 = 18
#Total number of violations on LAYER ME2 = 156
#Total number of violations on LAYER ME3 = 98
#Total number of violations on LAYER ME4 = 239
#Total number of violations on LAYER ME5 = 0
#Total number of violations on LAYER ME6 = 0
#Total number of violations on LAYER ME7 = 0
#Total number of violations on LAYER ME8 = 0
#
#start routing for process antenna violation fix ...
#cpu time = 00:00:25, elapsed time = 00:00:16, memory = 4220.00 (Mb)
#
#Total number of nets with non-default rule or having extra spacing = 1576
#Total wire length = 16455456 um.
#Total half perimeter of net bounding box = 14221684 um.
#Total wire length on LAYER ME1 = 181859 um.
#Total wire length on LAYER ME2 = 2606692 um.
#Total wire length on LAYER ME3 = 3567005 um.
#Total wire length on LAYER ME4 = 3069386 um.
#Total wire length on LAYER ME5 = 3623571 um.
#Total wire length on LAYER ME6 = 2726405 um.
#Total wire length on LAYER ME7 = 509425 um.
#Total wire length on LAYER ME8 = 171113 um.
#Total number of vias = 2800212
#Total number of multi-cut vias = 27538 ( 1.0%)
#Total number of single cut vias = 2772674 ( 99.0%)
#Up-Via Summary (total 2800212):
# single-cut multi-cut Total
#-----------------------------------------------------------
# Metal 1 996488 (100.0%) 0 ( 0.0%) 996488
# Metal 2 1061092 (100.0%) 0 ( 0.0%) 1061092
# Metal 3 381049 (100.0%) 0 ( 0.0%) 381049
# Metal 4 199988 (100.0%) 48 ( 0.0%) 200036
# Metal 5 125172 (100.0%) 0 ( 0.0%) 125172
# Metal 6 0 ( 0.0%) 27490 (100.0%) 27490
# Metal 7 8885 (100.0%) 0 ( 0.0%) 8885
#-----------------------------------------------------------
# 2772674 ( 99.0%) 27538 ( 1.0%) 2800212
#
#Total number of DRC violations = 504
#Total number of net violated process antenna rule = 0
#Total number of violations on LAYER ME1 = 31
#Total number of violations on LAYER ME2 = 154
#Total number of violations on LAYER ME3 = 108
#Total number of violations on LAYER ME4 = 211
#Total number of violations on LAYER ME5 = 0
#Total number of violations on LAYER ME6 = 0
#Total number of violations on LAYER ME7 = 0
#Total number of violations on LAYER ME8 = 0
#
#detailRoute Statistics:
#Cpu time = 01:41:06
#Elapsed time = 00:19:01
#Increased memory = 65.00 (Mb)
#Total memory = 4215.00 (Mb)
#Peak memory = 4975.00 (Mb)
#
#globalDetailRoute statistics:
#Cpu time = 02:10:16
#Elapsed time = 00:35:43
#Increased memory = 4.00 (Mb)
#Total memory = 3870.00 (Mb)
#Peak memory = 4975.00 (Mb)
#Number of warnings = 0
#Total number of warnings = 103
#Number of fails = 0
#Total number of fails = 0
#Complete globalDetailRoute on Thu Sep 29 23:41:25 2011
#
saveDesign save/chip_shabziger_routed.enc
Redoing specifyClockTree ...
Checking spec file integrity...
**WARN: (ENCSYT-3036): Design directory save/chip_shabziger_routed.enc.dat exists, rename it to save/chip_shabziger_routed.enc.dat.tmp.
If saveDesign succeeds, it will be deleted.
Writing Netlist "save/chip_shabziger_routed.enc.dat/shabziger_chip.v.gz" ...
Saving clock tree spec file 'save/chip_shabziger_routed.enc.dat/shabziger_chip.ctstch' ...
Saving configuration ...
Saving preference file save/chip_shabziger_routed.enc.dat/enc.pref.tcl ...
Saving floorplan ...
Saving Drc markers ...
... 504 Drc markers are saved ...
Saving placement ...
*** Completed savePlace (cpu=0:00:00.4 real=0:00:01.0 mem=3870.2M) ***
Saving route ...
*** Completed saveRoute (cpu=0:00:04.0 real=0:00:11.0 mem=3870.2M) ***
Writing DEF file 'save/chip_shabziger_routed.enc.dat/shabziger_chip.def.gz', current time is Thu Sep 29 23:43:01 2011 ...
unitPerMicron=1000, dbgMicronPerDBU=0.001000, unitPerDBU=1.000000
DEF file 'save/chip_shabziger_routed.enc.dat/shabziger_chip.def.gz' is written, current time is Thu Sep 29 23:43:02 2011 ...
*** Completed saveYieldMap (cpu=: 0:00:00.0 real=0:00:00.0 mem=: 0.000M) ***
setExtractRCMode -engine postRoute -effortLevel low -coupled false -reduce 0.0
**WARN: (ENCEXT-3493): Extraction mode changed by calling extraction setup command 'setExtractRCMode'. Therefore, parasitic data in the tool generated as per previous mode is deleted. Call of extractRC/spefIn will generate/bring parasitic data in the tool as per current mode.
timeDesign -postroute -hold -outDir timingReports_final
Extraction called for design 'shabziger_chip' of instances=310768 and nets=283683 using extraction engine 'postRoute' at effort level 'low' .
Detail RC Extraction called for design shabziger_chip.
RC Extraction called in multi-corner(2) mode.
Process corner(s) are loaded.
Corner: rc_worst
Corner: rc_best
extractDetailRC Option : -outfile ../tmp/shabziger_chip_wukc1u_9079.rcdb.d -extended
RC Mode: Detail [Extended CapTable, RC Table Resistances]
RC Corner Indexes 0 1
Capacitance Scaling Factor : 1.00000 1.00000
Coupling Cap. Scaling Factor : 1.00000 1.00000
Resistance Scaling Factor : 1.00000 1.00000
Clock Cap. Scaling Factor : 1.00000 1.00000
Clock Res. Scaling Factor : 1.00000 1.00000
Shrink Factor : 1.00000
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Checking LVS Completed (CPU Time= 0:00:01.2 MEM= 3870.2M)
Creating parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' in memory efficient access mode for storing RC.
Extracted 10% (CPU Time= 0:00:06.3 MEM= 4163.3M)
Extracted 20% (CPU Time= 0:00:12.8 MEM= 4174.3M)
Extracted 30% (CPU Time= 0:00:16.5 MEM= 4191.4M)
Extracted 40.0001% (CPU Time= 0:00:22.6 MEM= 4193.4M)
Extracted 50.0001% (CPU Time= 0:00:29.5 MEM= 4225.5M)
Extracted 60.0001% (CPU Time= 0:00:34.0 MEM= 4230.6M)
Extracted 70.0001% (CPU Time= 0:00:42.4 MEM= 4230.6M)
Extracted 80.0001% (CPU Time= 0:00:49.9 MEM= 4230.6M)
Extracted 90.0001% (CPU Time= 0:00:54.7 MEM= 4230.6M)
Extracted 100% (CPU Time= 0:01:06 MEM= 4230.6M)
Nr. Extracted Resistors : 5577754
Nr. Extracted Ground Cap. : 5856523
Nr. Extracted Coupling Cap. : 0
Opening parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' for reading.
Detail RC Extraction DONE (CPU Time: 0:01:08 Real Time: 0:01:11 MEM: 3870.234M)
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
timeDesign Summary
------------------------------------------------------------
+--------------------+---------+---------+---------+---------+---------+---------+
| Hold mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| -5.301 | 0.077 | -1.464 | -4.406 | -5.301 | -0.981 |
| TNS (ns):|-37059.2 | 0.000 |-36980.6 | -76.869 | -10.001 | -7.943 |
| Violating Paths:| 59684 | 0 | 59665 | 19 | 2 | 15 |
| All Paths:| 85005 | 46605 | 63302 | 19 | 2 | 15 |
+--------------------+---------+---------+---------+---------+---------+---------+
Density: 60.175%
------------------------------------------------------------
Reported timing to dir timingReports_final
Total CPU time: 166.38 sec
Total Real time: 155.0 sec
Total Memory Usage: 4112.621094 Mbytes
timeDesign -expandedViews -postroute -outDir timingReports_final -prefix shabziger.postroute.expV
**WARN: (ENCEXT-3493): Extraction mode changed by calling extraction setup command 'setExtractRCMode'. Therefore, parasitic data in the tool generated as per previous mode is deleted. Call of extractRC/spefIn will generate/bring parasitic data in the tool as per current mode.
Extraction called for design 'shabziger_chip' of instances=310768 and nets=283683 using extraction engine 'postRoute' at effort level 'low' .
Detail RC Extraction called for design shabziger_chip.
RC Extraction called in multi-corner(2) mode.
Process corner(s) are loaded.
Corner: rc_worst
Corner: rc_best
extractDetailRC Option : -outfile ../tmp/shabziger_chip_wukc1u_9079.rcdb.d -maxResLength 200 -extended
RC Mode: Detail [Extended CapTable, RC Table Resistances]
RC Corner Indexes 0 1
Capacitance Scaling Factor : 1.00000 1.00000
Coupling Cap. Scaling Factor : 1.00000 1.00000
Resistance Scaling Factor : 1.00000 1.00000
Clock Cap. Scaling Factor : 1.00000 1.00000
Clock Res. Scaling Factor : 1.00000 1.00000
Shrink Factor : 1.00000
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Checking LVS Completed (CPU Time= 0:00:01.2 MEM= 4104.6M)
Closing parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d'. 371402 times net's RC data read were performed.
Creating parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' in memory efficient access mode for storing RC.
Extracted 10% (CPU Time= 0:00:07.1 MEM= 4438.2M)
Extracted 20% (CPU Time= 0:00:13.7 MEM= 4449.2M)
Extracted 30% (CPU Time= 0:00:17.4 MEM= 4467.3M)
Extracted 40.0001% (CPU Time= 0:00:23.5 MEM= 4469.3M)
Extracted 50.0001% (CPU Time= 0:00:30.5 MEM= 4500.4M)
Extracted 60.0001% (CPU Time= 0:00:34.9 MEM= 4505.5M)
Extracted 70.0001% (CPU Time= 0:00:43.4 MEM= 4506.5M)
Extracted 80.0001% (CPU Time= 0:00:50.9 MEM= 4506.5M)
Extracted 90.0001% (CPU Time= 0:00:55.7 MEM= 4506.5M)
Extracted 100% (CPU Time= 0:01:07 MEM= 4506.5M)
Nr. Extracted Resistors : 5577754
Nr. Extracted Ground Cap. : 5856523
Nr. Extracted Coupling Cap. : 0
Opening parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' for reading.
Detail RC Extraction DONE (CPU Time: 0:01:09 Real Time: 0:01:11 MEM: 4081.641M)
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
timeDesign Summary
------------------------------------------------------------
+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| -0.246 | -0.246 | 0.509 | 0.321 | 18.536 | 15.850 |
| TNS (ns):|-180.760 |-180.760 | 0.000 | 0.000 | 0.000 | 0.000 |
| Violating Paths:| 2876 | 2876 | 0 | 0 | 0 | 0 |
| All Paths:| 85005 | 46605 | 63302 | 19 | 2 | 15 |
+--------------------+---------+---------+---------+---------+---------+---------+
|dummy_slow_view | 7.881 | 7.881 | 9.049 | 8.721 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5131 | 2517 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_blake_slow_view| -0.015 | -0.015 | 3.903 | 3.721 | N/A | N/A |
| | -0.051 | -0.051 | 0.000 | 0.000 | N/A | N/A |
| | 4 | 4 | 0 | 0 | N/A | N/A |
| | 8290 | 4385 | 3887 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_groestl_slow_view
| | -0.123 | -0.123 | 2.649 | 2.321 | N/A | N/A |
| | -3.289 | -3.289 | 0.000 | 0.000 | N/A | N/A |
| | 124 | 124 | 0 | 0 | N/A | N/A |
| | 8236 | 4070 | 4148 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_jh_slow_view | -0.147 | -0.147 | 2.049 | 1.721 | N/A | N/A |
| | -0.918 | -0.918 | 0.000 | 0.000 | N/A | N/A |
| | 21 | 21 | 0 | 0 | N/A | N/A |
| | 8801 | 4640 | 4143 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_keccak_slow_view
| | -0.065 | -0.065 | 0.730 | 0.721 | N/A | N/A |
| | -1.249 | -1.249 | 0.000 | 0.000 | N/A | N/A |
| | 63 | 63 | 0 | 0 | N/A | N/A |
| | 8346 | 4125 | 4203 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_sha2_slow_view | 0.105 | 0.105 | 2.500 | 2.221 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 7204 | 3554 | 3632 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_skein_slow_view| -0.114 | -0.114 | 1.603 | 1.521 | N/A | N/A |
| | -4.118 | -4.118 | 0.000 | 0.000 | N/A | N/A |
| | 107 | 107 | 0 | 0 | N/A | N/A |
| | 9002 | 4517 | 4467 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_blake_slow_view | -0.158 | -0.158 | 2.949 | 2.621 | N/A | N/A |
| | -9.175 | -9.175 | 0.000 | 0.000 | N/A | N/A |
| | 132 | 132 | 0 | 0 | N/A | N/A |
| | 9724 | 5498 | 4208 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_groestl_slow_view
| | -0.209 | -0.209 | 1.049 | 0.821 | N/A | N/A |
| | -63.721 | -63.721 | 0.000 | 0.000 | N/A | N/A |
| | 946 | 946 | 0 | 0 | N/A | N/A |
| | 9252 | 5088 | 4146 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_jh_slow_view | -0.195 | -0.195 | 0.649 | 0.321 | N/A | N/A |
| | -3.301 | -3.301 | 0.000 | 0.000 | N/A | N/A |
| | 132 | 132 | 0 | 0 | N/A | N/A |
| | 10269 | 5853 | 4398 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_keccak_slow_view| -0.246 | -0.246 | 0.649 | 0.321 | N/A | N/A |
| | -87.355 | -87.355 | 0.000 | 0.000 | N/A | N/A |
| | 1231 | 1231 | 0 | 0 | N/A | N/A |
| | 9926 | 5702 | 4206 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_sha2_slow_view | -0.060 | -0.060 | 0.509 | 0.521 | N/A | N/A |
| | -0.292 | -0.292 | 0.000 | 0.000 | N/A | N/A |
| | 17 | 17 | 0 | 0 | N/A | N/A |
| | 7986 | 4238 | 3730 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_skein_slow_view | -0.152 | -0.152 | 2.615 | 4.221 | N/A | N/A |
| | -7.490 | -7.490 | 0.000 | 0.000 | N/A | N/A |
| | 117 | 117 | 0 | 0 | N/A | N/A |
| | 10156 | 5551 | 4587 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ram1_slow_view | 5.157 | 5.157 | 9.049 | 8.721 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5237 | 2623 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ram2_slow_view | 4.911 | 4.911 | 9.049 | 8.721 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5237 | 2623 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ram3_slow_view | 3.367 | 3.367 | 9.049 | 8.721 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5240 | 2626 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|test_slow_view | 13.341 | 13.341 | 13.763 | 18.516 | 18.536 | 15.850 |
| | 0.000 | 0.000 | 0.000 | 0.000 | 0.000 | 0.000 |
| | 0 | 0 | 0 | 0 | 0 | 0 |
| | 85005 | 46605 | 63302 | 19 | 2 | 15 |
+--------------------+---------+---------+---------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 43 (43) | -0.023 | 43 (43) |
| max_tran | 40 (218) | -0.360 | 40 (218) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 60.175%
------------------------------------------------------------
Reported timing to dir timingReports_final
Total CPU time: 795.5 sec
Total Real time: 742.0 sec
Total Memory Usage: 4799.328125 Mbytes
setOptMode -setupTargetSlack 0
*info: Setting setup target slack to 0.000
*info: Hold target slack is 0.000
optDesign -postroute -outDir timingReports_final -prefix shabziger.postrouteopt
Disable merging buffers from different footprints for postRoute code for non-MSV designs
**WARN: (ENCOPT-6055): The following cells have a dont_touch property but without being dont_use.
Such configuration can impact the timing closure because they can be inserted in the netlist but never transformed again.
It is recommended that you apply a dont_use attribute on them.
Cell SYKA65_2048X32X1CM8 is dont_touch but not dont_use
Cell SHKA65_2048X32X1CM4 is dont_touch but not dont_use
Cell SHKA65_16384X32X1CM16 is dont_touch but not dont_use
...
Reporting only the 20 first cells found...
COE opt is not supported in non AAE mode. Reverting to non COE postroute flow
**optDesign ... cpu = 0:00:00, real = 0:00:00, mem = 4799.3M **
#Created 3310 library cell signatures
#Created 283683 NETS and 0 SPECIALNETS signatures
#Created 310769 instance signatures
Begin checking placement ... (start mem=4830.5M, init mem=4922.6M)
*info: Placed = 273277
*info: Unplaced = 0
Placement Density:60.17%(1135020/1886211)
Finished checkPlace (cpu: total=0:00:02.3, vio checks=0:00:00.2; mem=4827.4M)
Setting latch borrow mode to budget during optimization.
setExtractRCMode -coupled false
**WARN: (ENCEXT-3493): Extraction mode changed by calling extraction setup command 'setExtractRCMode'. Therefore, parasitic data in the tool generated as per previous mode is deleted. Call of extractRC/spefIn will generate/bring parasitic data in the tool as per current mode.
*** optDesign -postRoute ***
DRC Margin: user margin 0.0; extra margin 0
Setup Target Slack: user slack 0.0
Hold Target Slack: user slack 0.0
*info: Setting setup target slack to 0.000
*info: Hold target slack is 0.000
**INFO : Adding temp dont-use cells (LVT only flow version : 4)
Creating information for LVT Only Flow
Num of Buffers : 123
Num of Inverters : 105
Num of VTs : 3
Executing LVT Only Same Size Flow (setting 4)
*Info* Num dontuse cells 311
*Info* Num dontuse cells 2259
Extraction called for design 'shabziger_chip' of instances=310768 and nets=283683 using extraction engine 'postRoute' at effort level 'low' .
Detail RC Extraction called for design shabziger_chip.
RC Extraction called in multi-corner(2) mode.
Process corner(s) are loaded.
Corner: rc_worst
Corner: rc_best
extractDetailRC Option : -outfile ../tmp/shabziger_chip_wukc1u_9079.rcdb.d -maxResLength 200 -extended
RC Mode: Detail [Extended CapTable, RC Table Resistances]
RC Corner Indexes 0 1
Capacitance Scaling Factor : 1.00000 1.00000
Coupling Cap. Scaling Factor : 1.00000 1.00000
Resistance Scaling Factor : 1.00000 1.00000
Clock Cap. Scaling Factor : 1.00000 1.00000
Clock Res. Scaling Factor : 1.00000 1.00000
Shrink Factor : 1.00000
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Checking LVS Completed (CPU Time= 0:00:01.2 MEM= 4146.3M)
Closing parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d'. 4613552 times net's RC data read were performed.
Creating parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' in memory efficient access mode for storing RC.
Extracted 10% (CPU Time= 0:00:07.1 MEM= 4437.8M)
Extracted 20% (CPU Time= 0:00:13.7 MEM= 4448.9M)
Extracted 30% (CPU Time= 0:00:17.5 MEM= 4466.9M)
Extracted 40.0001% (CPU Time= 0:00:23.7 MEM= 4468.9M)
Extracted 50.0001% (CPU Time= 0:00:30.6 MEM= 4501.1M)
Extracted 60.0001% (CPU Time= 0:00:35.1 MEM= 4505.1M)
Extracted 70.0001% (CPU Time= 0:00:43.5 MEM= 4506.1M)
Extracted 80.0001% (CPU Time= 0:00:51.1 MEM= 4506.1M)
Extracted 90.0001% (CPU Time= 0:00:55.9 MEM= 4506.1M)
Extracted 100% (CPU Time= 0:01:07 MEM= 4506.1M)
Nr. Extracted Resistors : 5577754
Nr. Extracted Ground Cap. : 5856523
Nr. Extracted Coupling Cap. : 0
Opening parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' for reading.
Detail RC Extraction DONE (CPU Time: 0:01:09 Real Time: 0:01:13 MEM: 4136.855M)
Using new Cte TW Api base...#################################################################################
# Design Stage: PostRoute
# Design Mode: 65nm
# Analysis Mode: MMMC non-OCV
# Extraction Mode: detail/spef
# Delay Calculation Options: engine=signalStorm signOff=true SIAware=false(opt)
# Switching Delay Calculation Engine to signalStorm
#################################################################################
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.4, MEM = 4197.0M, InitMEM = 4197.0M)
Start delay calculation using Signal Storm (mem=4196.984M)...
delayCal using detail RC...
Opening parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' for reading.
RC Database In Completed (CPU Time= 0:00:01.2 MEM= 4306.0M)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Delay calculation completed. (cpu=0:00:48.6 real=0:00:48.0 mem=4819.406M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 4819.4M, InitMEM = 4819.4M)
Start delay calculation using Signal Storm (mem=4819.406M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:24.3 real=0:00:25.0 mem=4819.406M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 4819.4M, InitMEM = 4819.4M)
Start delay calculation using Signal Storm (mem=4819.406M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:24.5 real=0:00:24.0 mem=4819.406M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 4819.4M, InitMEM = 4819.4M)
Start delay calculation using Signal Storm (mem=4819.406M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:24.7 real=0:00:25.0 mem=4819.406M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 4819.4M, InitMEM = 4819.4M)
Start delay calculation using Signal Storm (mem=4819.406M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:25.0 real=0:00:25.0 mem=4819.406M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 4819.4M, InitMEM = 4819.4M)
Start delay calculation using Signal Storm (mem=4819.406M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:24.7 real=0:00:25.0 mem=4819.406M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 4819.4M, InitMEM = 4819.4M)
Start delay calculation using Signal Storm (mem=4819.406M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:25.3 real=0:00:25.0 mem=4819.406M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 4819.4M, InitMEM = 4819.4M)
Start delay calculation using Signal Storm (mem=4819.406M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:25.3 real=0:00:25.0 mem=4819.406M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 4819.4M, InitMEM = 4819.4M)
Start delay calculation using Signal Storm (mem=4819.406M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:27.0 real=0:00:27.0 mem=4819.406M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 4819.4M, InitMEM = 4819.4M)
Start delay calculation using Signal Storm (mem=4819.406M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:25.9 real=0:00:26.0 mem=4819.406M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 4819.4M, InitMEM = 4819.4M)
Start delay calculation using Signal Storm (mem=4819.406M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:26.8 real=0:00:27.0 mem=4819.406M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 4819.4M, InitMEM = 4819.4M)
Start delay calculation using Signal Storm (mem=4819.406M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:26.1 real=0:00:26.0 mem=4819.406M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 4819.4M, InitMEM = 4819.4M)
Start delay calculation using Signal Storm (mem=4819.406M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:27.8 real=0:00:28.0 mem=4819.406M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 4819.4M, InitMEM = 4819.4M)
Start delay calculation using Signal Storm (mem=4819.406M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:26.4 real=0:00:27.0 mem=4819.406M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 4819.4M, InitMEM = 4819.4M)
Start delay calculation using Signal Storm (mem=4819.406M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:26.4 real=0:00:26.0 mem=4819.406M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 4819.4M, InitMEM = 4819.4M)
Start delay calculation using Signal Storm (mem=4819.406M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:26.4 real=0:00:27.0 mem=4819.406M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 4819.4M, InitMEM = 4819.4M)
Start delay calculation using Signal Storm (mem=4819.406M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:35.1 real=0:00:35.0 mem=4819.406M 0)
*** CDM Built up (cpu=0:08:52 real=0:08:52 mem= 4819.4M) ***
-holdSdfFile {} # string, default=""
-holdSdfScript {} # string, default="", private
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
Initial Summary
------------------------------------------------------------
+--------------------+---------+
| Setup mode | all |
+--------------------+---------+
| WNS (ns):| -0.246 |
| TNS (ns):|-180.760 |
| Violating Paths:| 2876 |
| All Paths:| 85005 |
+--------------------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 43 (43) | -0.023 | 43 (43) |
| max_tran | 40 (218) | -0.360 | 40 (218) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 60.175%
------------------------------------------------------------
**optDesign ... cpu = 0:11:39, real = 0:11:42, mem = 5150.7M **
*info: Start fixing DRV (Mem = 5187.66M) ...
*info: Options = -postRoute -maxCap -maxTran -noMaxFanout -noSensitivity -backward -maxIter 1
*info: Start fixing DRV iteration 1 ...
*** Starting dpFixDRCViolation (5187.7M)
*info: 40 io nets excluded
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
*info: 567 clock nets excluded
*info: 4 special nets excluded.
*info: 2406 no-driver nets excluded.
*info: 21 multi-driver nets excluded.
*info: There are 60 candidate Buffer cells
*info: There are 52 candidate Inverter cells
Initializing placement sections/sites ...
Density before buffering = 0.601746
Start fixing design rules ... (0:00:04.4 5356.6M)
All-RC-Corners-Per-Net-In-Memory is turned ON...
Closing parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d'. 4613576 times net's RC data read were performed.
Opening parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' for reading.
RC Database In Completed (CPU Time= 0:00:01.4 MEM= 5232.1M)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Topological Sorting (CPU = 0:00:01.0, MEM = 5400.0M, InitMEM = 5400.0M)
Done fixing design rule (0:01:19 5350.1M)
Summary:
57 buffers added on 57 nets (with 39 drivers resized)
Density after buffering = 0.601901
Starting refinePlace ...
move report: placeLevelShifters moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Spread Effort: high, post-route mode.
Finished Phase I. CPU Time = 0:00:17.1, Real Time = 0:00:17.0
move report: preRPlace moves 48 insts, mean move: 0.36 um, max move: 0.80 um
max move on inst (top/i_ethz_jh/U26096): (949.60, 1331.40) --> (950.40, 1331.40)
move report: rPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: overall moves 48 insts, mean move: 0.36 um, max move: 0.80 um
max move on inst (top/i_ethz_jh/U26096): (949.60, 1331.40) --> (950.40, 1331.40)
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 0.80 um
inst (top/i_ethz_jh/U26096) with max move: (949.6, 1331.4) -> (950.4, 1331.4)
mean (X+Y) = 0.36 um
Total instances moved : 48
*** cpu=0:00:18.8 mem=5255.9M mem(used)=16.6M***
*** Completed dpFixDRCViolation (0:01:40 5248.3M)
End of fixDrcViolation iteration 1.
*** Starting dpFixDRCViolation (5248.3M)
*info: 40 io nets excluded
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
*info: 567 clock nets excluded
*info: 4 special nets excluded.
*info: 2406 no-driver nets excluded.
*info: 21 multi-driver nets excluded.
Start fixing design rules ... (0:00:04.2 5360.3M)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Topological Sorting (CPU = 0:00:01.0, MEM = 5388.6M, InitMEM = 5388.6M)
Done fixing design rule (0:00:43.7 5337.2M)
Summary:
1 buffer added on 1 net (with 0 driver resized)
Density after buffering = 0.601915
Starting refinePlace ...
move report: placeLevelShifters moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Spread Effort: high, post-route mode.
Finished Phase I. CPU Time = 0:00:16.8, Real Time = 0:00:17.0
move report: preRPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: rPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: overall moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 0.00 um
mean (X+Y) = 0.00 um
Total instances moved : 0
*** cpu=0:00:18.4 mem=5256.9M mem(used)=6.5M***
*** Completed dpFixDRCViolation (0:01:05 5250.4M)
End of fixDrcViolation iteration 2.
*info:
*info: Completed fixing DRV (CPU Time = 0:03:05, Mem = 5250.36M).
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
Summary (cpu=3.09min real=3.10min mem=5250.4M)
------------------------------------------------------------
+--------------------+---------+
| Setup mode | all |
+--------------------+---------+
| WNS (ns):| -0.246 |
| TNS (ns):|-180.752 |
| Violating Paths:| 2875 |
| All Paths:| 85005 |
+--------------------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 0 (0) | 0.000 | 0 (0) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 60.192%
------------------------------------------------------------
**optDesign ... cpu = 0:15:22, real = 0:15:25, mem = 5250.4M **
*** Timing NOT met, worst failing slack is -0.246
*** Check timing (0:00:00.6)
*** Timing NOT met, worst failing slack is -0.246
*** Check timing (0:00:00.1)
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
Info: 40 io nets excluded
Info: 567 clock nets excluded from IPO operation.
*** Start Post Route Setup Fixing (cpu=0:00:00.0 mem=5104.4M) ***
Time Engine : CTE
SSTA Mode : off
MMMC mode : on (11 dominant view(s), 6 view(s) pruned)
Incr. DC : on
Incr POM Mode : on
On Demand POM Mode : on
CTE SubNetWork Mode : on
Up Size : on
Down Size : on
Resize FFs : on
Add Buffer : off
Del Buffer : off
Pin Swap : off
Add InvPair : off
LegalLoc GS : off
Speedup GS : off
Crit. Range : 20%
density before = 60.192%
total 280768 net, 39 ipo_ignored
total 951821 term, 78 ipo_ignored
total 289612 comb inst, 37273 fixed, 273 dont_touch, 36923 no_footp
total 21214 seq inst, 18 fixed, 3 dont_touch, 3 no_footp
total 240 footprint(s)
10 footprint(s) with 0 cell(s)
36 footprint(s) with 1 cell(s)
16 footprint(s) with 2 cell(s)
3 footprint(s) with 3 cell(s)
119 footprint(s) with 4 cell(s)
13 footprint(s) with 5 cell(s)
13 footprint(s) with 6 cell(s)
13 footprint(s) with 7 cell(s)
7 footprint(s) with 8 cell(s)
1 footprint(s) with 9 cell(s)
9 footprint(s) with 10+ cell(s)
Estimated WNS = -0.246ns, TNS = -180.758ns (cpu=0:00:13.1 mem=5175.2M)
Iter 0 ...
Collected 67765 nets for fixing
Evaluate 753(997) resize, Select 130 cand. (cpu=0:00:25.7 mem=5255.9M)
Commit 47 cand, 40 upSize, 5 downSize, 2 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:00:31.2 mem=5256.9M)
Calc. DC (cpu=0:00:31.8 mem=5256.9M) ***
Estimated WNS = -0.174ns, TNS = -143.888ns (cpu=0:00:38.3 mem=5256.9M)
Iter 1 ...
Collected 67708 nets for fixing
Evaluate 754(1530) resize, Select 481 cand. (cpu=0:00:56.6 mem=5258.3M)
Commit 45 cand, 34 upSize, 8 downSize, 3 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:01:10 mem=5262.5M)
Calc. DC (cpu=0:01:10 mem=5262.5M) ***
Estimated WNS = -0.161ns, TNS = -136.125ns (cpu=0:01:17 mem=5262.5M)
Iter 2 ...
Collected 66831 nets for fixing
Evaluate 750(1573) resize, Select 202 cand. (cpu=0:01:35 mem=5264.6M)
Commit 47 cand, 43 upSize, 2 downSize, 2 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:01:41 mem=5265.6M)
Calc. DC (cpu=0:01:42 mem=5265.6M) ***
Estimated WNS = -0.143ns, TNS = -117.886ns (cpu=0:01:48 mem=5265.6M)
Iter 3 ...
Collected 65464 nets for fixing
Evaluate 750(1697) resize, Select 437 cand. (cpu=0:02:08 mem=5267.4M)
Commit 39 cand, 30 upSize, 8 downSize, 1 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:02:11 mem=5271.0M)
Calc. DC (cpu=0:02:11 mem=5271.0M) ***
Estimated WNS = -0.133ns, TNS = -116.915ns (cpu=0:02:17 mem=5271.0M)
Iter 4 ...
Collected 65307 nets for fixing
Evaluate 758(2086) resize, Select 134 cand. (cpu=0:02:38 mem=5271.6M)
Commit 35 cand, 30 upSize, 4 downSize, 1 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:02:40 mem=5272.1M)
Calc. DC (cpu=0:02:40 mem=5272.1M) ***
Estimated WNS = -0.129ns, TNS = -115.995ns (cpu=0:02:47 mem=5272.1M)
Iter 5 ...
Collected 65255 nets for fixing
Evaluate 750(1697) resize, Select 391 cand. (cpu=0:03:05 mem=5272.6M)
Commit 41 cand, 24 upSize, 15 downSize, 2 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:03:09 mem=5276.3M)
Calc. DC (cpu=0:03:09 mem=5276.3M) ***
Estimated WNS = -0.125ns, TNS = -110.182ns (cpu=0:03:16 mem=5276.3M)
Iter 6 ...
Collected 65175 nets for fixing
Evaluate 753(1993) resize, Select 168 cand. (cpu=0:03:40 mem=5277.2M)
Commit 40 cand, 30 upSize, 9 downSize, 1 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:03:43 mem=5278.7M)
Calc. DC (cpu=0:03:43 mem=5278.7M) ***
Estimated WNS = -0.120ns, TNS = -109.762ns (cpu=0:03:49 mem=5278.7M)
Iter 7 ...
Collected 64495 nets for fixing
Evaluate 752(2219) resize, Select 474 cand. (cpu=0:04:10 mem=5279.2M)
Commit 44 cand, 27 upSize, 16 downSize, 1 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:04:16 mem=5281.7M)
Calc. DC (cpu=0:04:17 mem=5281.7M) ***
Estimated WNS = -0.116ns, TNS = -109.126ns (cpu=0:04:23 mem=5281.7M)
Iter 8 ...
Collected 63976 nets for fixing
Evaluate 750(2325) resize, Select 166 cand. (cpu=0:04:50 mem=5283.6M)
Commit 35 cand, 31 upSize, 2 downSize, 2 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:04:53 mem=5286.2M)
Calc. DC (cpu=0:04:54 mem=5286.2M) ***
Estimated WNS = -0.115ns, TNS = -105.646ns (cpu=0:05:00 mem=5286.2M)
Iter 9 ...
Collected 63447 nets for fixing
Evaluate 750(1671) resize, Select 451 cand. (cpu=0:05:21 mem=5287.8M)
Commit 39 cand, 25 upSize, 12 downSize, 2 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:05:26 mem=5291.5M)
Calc. DC (cpu=0:05:26 mem=5291.5M) ***
Estimated WNS = -0.118ns, TNS = -104.300ns (cpu=0:05:32 mem=5291.5M)
Iter 10 ...
Collected 63525 nets for fixing
Evaluate 751(2403) resize, Select 145 cand. (cpu=0:05:57 mem=5292.0M)
Commit 35 cand, 32 upSize, 3 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:05:59 mem=5293.5M)
Calc. DC (cpu=0:06:00 mem=5293.5M) ***
Estimated WNS = -0.110ns, TNS = -103.705ns (cpu=0:06:06 mem=5293.5M)
Iter 11 ...
Collected 63297 nets for fixing
Evaluate 750(2978) resize, Select 377 cand. (cpu=0:06:36 mem=5295.4M)
Commit 41 cand, 21 upSize, 18 downSize, 2 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:06:47 mem=5300.0M)
Calc. DC (cpu=0:06:48 mem=5300.0M) ***
Estimated WNS = -0.108ns, TNS = -103.409ns (cpu=0:06:54 mem=5300.0M)
Iter 12 ...
Collected 63078 nets for fixing
Evaluate 753(2110) resize, Select 156 cand. (cpu=0:07:13 mem=5300.5M)
Commit 29 cand, 26 upSize, 3 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:07:16 mem=5301.0M)
Calc. DC (cpu=0:07:16 mem=5301.0M) ***
Estimated WNS = -0.107ns, TNS = -99.731ns (cpu=0:07:22 mem=5301.0M)
Iter 13 ...
Collected 62954 nets for fixing
Evaluate 752(1958) resize, Select 398 cand. (cpu=0:07:46 mem=5303.6M)
Commit 37 cand, 27 upSize, 9 downSize, 1 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:07:50 mem=5307.3M)
Calc. DC (cpu=0:07:50 mem=5307.3M) ***
Estimated WNS = -0.104ns, TNS = -98.529ns (cpu=0:07:56 mem=5307.3M)
Iter 14 ...
Collected 62135 nets for fixing
Evaluate 751(2752) resize, Select 151 cand. (cpu=0:08:21 mem=5308.0M)
Commit 31 cand, 25 upSize, 4 downSize, 2 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:08:23 mem=5309.5M)
Calc. DC (cpu=0:08:23 mem=5309.5M) ***
Estimated WNS = -0.104ns, TNS = -98.178ns (cpu=0:08:30 mem=5309.5M)
Calc. DC (cpu=0:08:30 mem=5309.5M) ***
*summary: 585 instances changed cell type
density after = 60.252%
*** Finish Post Route Setup Fixing (cpu=0:08:32 mem=5238.9M) ***
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
Info: 40 io nets excluded
Info: 567 clock nets excluded from IPO operation.
*** Start Post Route Setup Fixing (cpu=0:00:00.0 mem=5238.9M) ***
Time Engine : CTE
SSTA Mode : off
MMMC mode : on (11 dominant view(s), 6 view(s) pruned)
Incr. DC : on
Incr POM Mode : on
On Demand POM Mode : on
CTE SubNetWork Mode : on
Up Size : on
Down Size : on
Resize FFs : on
Add Buffer : on
Del Buffer : on
Pin Swap : off
Add InvPair : off
LegalLoc GS : off
Speedup GS : off
Crit. Range : 20%
density before = 60.252%
total 280768 net, 39 ipo_ignored
total 951821 term, 78 ipo_ignored
total 289612 comb inst, 37273 fixed, 273 dont_touch, 36923 no_footp
total 21214 seq inst, 18 fixed, 3 dont_touch, 3 no_footp
total 240 footprint(s)
10 footprint(s) with 0 cell(s)
36 footprint(s) with 1 cell(s)
16 footprint(s) with 2 cell(s)
3 footprint(s) with 3 cell(s)
119 footprint(s) with 4 cell(s)
13 footprint(s) with 5 cell(s)
13 footprint(s) with 6 cell(s)
13 footprint(s) with 7 cell(s)
7 footprint(s) with 8 cell(s)
1 footprint(s) with 9 cell(s)
9 footprint(s) with 10+ cell(s)
BUFFER FOOTPRINT (BUFM2S) :
CKBUFM1S(s) CKBUFM2S(s) BUFM2S(s) CKBUFM3S(s) BUFM3S(s)
CKBUFM4S(s) BUFM4S(s) BUFM5S(s) CKBUFM6S(s) BUFM6S(s)
CKBUFM8S(s) BUFM8S(s) BUFM10S(s) CKBUFM12S(s) BUFM12S(s)
BUFM14S(s) CKBUFM16S(s) BUFM16S(s) BUFM18S(s) CKBUFM20S(s)
BUFM20S(s) CKBUFM22SA(s) BUFM22SA(s) CKBUFM24S(s) BUFM24S(s)
CKBUFM26SA(s) BUFM26SA(s) CKBUFM32S(s) BUFM32SA(s) CKBUFM40S(s)
BUFM40SA(s) CKBUFM48S(s) BUFM48SA(s) DEL1M1W(s) CKBUFM1W
BUFM2W CKBUFM2W CKBUFM3W(s) BUFM3W(s) CKBUFM4W
BUFM4W DEL1M4W(s) BUFM5W(s) CKBUFM6W BUFM6W
CKBUFM8W BUFM8W BUFM10W CKBUFM12W BUFM12W
BUFM14W CKBUFM16W BUFM16W BUFM18W CKBUFM20W
BUFM20W CKBUFM22WA BUFM22WA CKBUFM24W BUFM24W
CKBUFM26WA BUFM26WA CKBUFM32W BUFM32WA CKBUFM40W
BUFM40WA CKBUFM48W BUFM48WA CKBUFM1R(s) BUFM2R(s)
CKBUFM2R(s) CKBUFM3R(s) BUFM3R(s) CKBUFM4R(s) BUFM4R(s)
DEL1M4R(s) BUFM5R(s) CKBUFM6R(s) BUFM6R(s) CKBUFM8R(s)
BUFM8R(s) BUFM10R(s) CKBUFM12R(s) BUFM12R(s) BUFM14R(s)
CKBUFM16R(s) BUFM16R(s) BUFM18R(s) CKBUFM20R(s) BUFM20R(s)
CKBUFM22RA(s) BUFM22RA(s) CKBUFM24R(s) BUFM24R(s) CKBUFM26RA(s)
BUFM26RA(s) CKBUFM32R(s) BUFM32RA(s) CKBUFM40R(s) BUFM40RA(s)
CKBUFM48R(s) BUFM48RA(s)
DELAY FOOTPRINT (DEL1M1S) :
DEL4M1S DEL3M1S DEL2M1S DEL1M1S DEL4M4S
DEL3M4S DEL2M4S DEL1M4S DEL4M1W DEL3M1W
DEL2M1W DEL4M4W DEL3M4W DEL2M4W DEL4M1R
DEL3M1R DEL2M1R DEL1M1R DEL4M4R DEL3M4R
DEL2M4R
Estimated WNS = -0.104ns, TNS = -98.178ns (cpu=0:00:13.0 mem=5287.4M)
Iter 0 ...
Collected 62040 nets for fixing
Evaluate 752(1515) resize, Select 122 cand. (cpu=0:00:29.6 mem=5294.0M)
Evaluate 21(5742) addBuf, Select 9 cand. (cpu=0:00:52.7 mem=5330.9M)
Evaluate 101(102) delBuf, Select 1 cand. (cpu=0:00:53.5 mem=5331.9M)
Commit 29 cand, 19 upSize, 3 downSize, 0 sameSize, 6 addBuf, 1 delBuf, 0 pinSwap (cpu=0:00:57.1 mem=5332.4M)
Calc. DC (cpu=0:00:58.6 mem=5332.4M) ***
Estimated WNS = -0.253ns, TNS = -160.306ns (cpu=0:01:05 mem=5332.4M)
*summary: 22 instances changed cell type
density after = 60.256%
*** Finish Post Route Setup Fixing (cpu=0:01:06 mem=5279.8M) ***
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
*** Timing NOT met, worst failing slack is -0.253
*** Check timing (0:00:00.3)
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
Info: 40 io nets excluded
Info: 567 clock nets excluded from IPO operation.
*** Start Post Route Setup Fixing (cpu=0:00:00.0 mem=5262.8M) ***
Time Engine : CTE
SSTA Mode : off
MMMC mode : on (11 dominant view(s), 6 view(s) pruned)
Incr. DC : on
Incr POM Mode : on
On Demand POM Mode : on
CTE SubNetWork Mode : on
Up Size : on
Down Size : on
Resize FFs : on
Add Buffer : off
Del Buffer : off
Pin Swap : off
Add InvPair : off
LegalLoc GS : off
Speedup GS : off
Crit. Range : 20%
density before = 60.256%
total 280773 net, 39 ipo_ignored
total 951831 term, 78 ipo_ignored
total 289617 comb inst, 37273 fixed, 273 dont_touch, 36923 no_footp
total 21214 seq inst, 18 fixed, 3 dont_touch, 3 no_footp
total 240 footprint(s)
10 footprint(s) with 0 cell(s)
36 footprint(s) with 1 cell(s)
16 footprint(s) with 2 cell(s)
3 footprint(s) with 3 cell(s)
119 footprint(s) with 4 cell(s)
13 footprint(s) with 5 cell(s)
13 footprint(s) with 6 cell(s)
13 footprint(s) with 7 cell(s)
7 footprint(s) with 8 cell(s)
1 footprint(s) with 9 cell(s)
9 footprint(s) with 10+ cell(s)
Estimated WNS = -0.253ns, TNS = -160.306ns (cpu=0:00:13.0 mem=5325.4M)
Iter 0 ...
Collected 63393 nets for fixing
Evaluate 772(970) resize, Select 141 cand. (cpu=0:00:30.5 mem=5330.9M)
Commit 45 cand, 34 upSize, 6 downSize, 5 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:00:34.5 mem=5333.5M)
Calc. DC (cpu=0:00:35.0 mem=5333.5M) ***
Estimated WNS = -0.102ns, TNS = -83.919ns (cpu=0:00:41.6 mem=5333.5M)
Iter 1 ...
Collected 62003 nets for fixing
Evaluate 761(2048) resize, Select 407 cand. (cpu=0:01:03 mem=5337.3M)
Commit 35 cand, 26 upSize, 8 downSize, 1 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:01:07 mem=5402.8M)
Calc. DC (cpu=0:01:08 mem=5402.8M) ***
Estimated WNS = -0.100ns, TNS = -83.255ns (cpu=0:01:14 mem=5402.8M)
Iter 2 ...
Collected 61503 nets for fixing
Evaluate 750(2760) resize, Select 157 cand. (cpu=0:01:39 mem=5403.3M)
Commit 28 cand, 23 upSize, 4 downSize, 1 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:01:41 mem=5403.8M)
Calc. DC (cpu=0:01:42 mem=5403.8M) ***
Estimated WNS = -0.099ns, TNS = -82.479ns (cpu=0:01:48 mem=5403.8M)
Iter 3 ...
Collected 61414 nets for fixing
Evaluate 755(3068) resize, Select 415 cand. (cpu=0:02:21 mem=5404.3M)
Commit 38 cand, 20 upSize, 16 downSize, 2 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:02:27 mem=5409.0M)
Calc. DC (cpu=0:02:27 mem=5409.0M) ***
Estimated WNS = -0.098ns, TNS = -79.575ns (cpu=0:02:33 mem=5409.0M)
Iter 4 ...
Collected 61124 nets for fixing
Evaluate 751(2542) resize, Select 151 cand. (cpu=0:03:02 mem=5410.5M)
Commit 27 cand, 22 upSize, 4 downSize, 1 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:03:04 mem=5412.0M)
Calc. DC (cpu=0:03:04 mem=5412.0M) ***
Estimated WNS = -0.098ns, TNS = -79.312ns (cpu=0:03:11 mem=5412.0M)
Iter 5 ...
Collected 61072 nets for fixing
Evaluate 754(1616) resize, Select 376 cand. (cpu=0:03:29 mem=5412.5M)
Commit 30 cand, 20 upSize, 10 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:03:31 mem=5413.0M)
Calc. DC (cpu=0:03:31 mem=5413.0M) ***
Estimated WNS = -0.095ns, TNS = -78.952ns (cpu=0:03:37 mem=5413.0M)
Iter 6 ...
Collected 60984 nets for fixing
Evaluate 752(2897) resize, Select 177 cand. (cpu=0:04:02 mem=5413.5M)
Commit 35 cand, 30 upSize, 3 downSize, 2 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:04:05 mem=5417.1M)
Calc. DC (cpu=0:04:05 mem=5417.1M) ***
Estimated WNS = -0.095ns, TNS = -78.333ns (cpu=0:04:12 mem=5417.1M)
Iter 7 ...
Collected 60558 nets for fixing
Evaluate 752(2504) resize, Select 299 cand. (cpu=0:04:37 mem=5417.6M)
Commit 20 cand, 15 upSize, 4 downSize, 1 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:04:38 mem=5418.1M)
Calc. DC (cpu=0:04:38 mem=5418.1M) ***
Estimated WNS = -0.093ns, TNS = -78.121ns (cpu=0:04:45 mem=5418.1M)
Iter 8 ...
Collected 60541 nets for fixing
Evaluate 753(2949) resize, Select 140 cand. (cpu=0:05:12 mem=5418.9M)
Commit 31 cand, 24 upSize, 6 downSize, 1 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:05:14 mem=5420.4M)
Calc. DC (cpu=0:05:14 mem=5420.4M) ***
Estimated WNS = -0.092ns, TNS = -77.931ns (cpu=0:05:20 mem=5420.4M)
Iter 9 ...
Collected 60517 nets for fixing
Evaluate 757(3097) resize, Select 409 cand. (cpu=0:05:47 mem=5420.9M)
Commit 42 cand, 27 upSize, 15 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:05:50 mem=5423.4M)
Calc. DC (cpu=0:05:51 mem=5423.4M) ***
Estimated WNS = -0.091ns, TNS = -77.647ns (cpu=0:05:57 mem=5423.4M)
Iter 10 ...
Collected 60471 nets for fixing
Evaluate 750(2874) resize, Select 148 cand. (cpu=0:06:24 mem=5423.9M)
Commit 24 cand, 17 upSize, 6 downSize, 1 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:06:26 mem=5424.4M)
Calc. DC (cpu=0:06:26 mem=5424.4M) ***
Estimated WNS = -0.091ns, TNS = -77.052ns (cpu=0:06:33 mem=5424.4M)
Iter 11 ...
Collected 60383 nets for fixing
Evaluate 757(2597) resize, Select 285 cand. (cpu=0:06:58 mem=5424.9M)
Commit 21 cand, 16 upSize, 5 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:06:59 mem=5427.5M)
Calc. DC (cpu=0:06:59 mem=5427.5M) ***
Estimated WNS = -0.091ns, TNS = -76.574ns (cpu=0:07:06 mem=5427.5M)
Calc. DC (cpu=0:07:06 mem=5427.5M) ***
*summary: 376 instances changed cell type
density after = 60.289%
*** Finish Post Route Setup Fixing (cpu=0:07:07 mem=5299.9M) ***
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
Info: 40 io nets excluded
Info: 567 clock nets excluded from IPO operation.
*** Start Post Route Setup Fixing (cpu=0:00:00.0 mem=5299.9M) ***
Time Engine : CTE
SSTA Mode : off
MMMC mode : on (11 dominant view(s), 6 view(s) pruned)
Incr. DC : on
Incr POM Mode : on
On Demand POM Mode : on
CTE SubNetWork Mode : on
Up Size : on
Down Size : on
Resize FFs : on
Add Buffer : on
Del Buffer : on
Pin Swap : off
Add InvPair : off
LegalLoc GS : off
Speedup GS : off
Crit. Range : 20%
density before = 60.289%
total 280773 net, 39 ipo_ignored
total 951831 term, 78 ipo_ignored
total 289617 comb inst, 37273 fixed, 273 dont_touch, 36923 no_footp
total 21214 seq inst, 18 fixed, 3 dont_touch, 3 no_footp
total 240 footprint(s)
10 footprint(s) with 0 cell(s)
36 footprint(s) with 1 cell(s)
16 footprint(s) with 2 cell(s)
3 footprint(s) with 3 cell(s)
119 footprint(s) with 4 cell(s)
13 footprint(s) with 5 cell(s)
13 footprint(s) with 6 cell(s)
13 footprint(s) with 7 cell(s)
7 footprint(s) with 8 cell(s)
1 footprint(s) with 9 cell(s)
9 footprint(s) with 10+ cell(s)
BUFFER FOOTPRINT (BUFM2S) :
CKBUFM1S(s) CKBUFM2S(s) BUFM2S(s) CKBUFM3S(s) BUFM3S(s)
CKBUFM4S(s) BUFM4S(s) BUFM5S(s) CKBUFM6S(s) BUFM6S(s)
CKBUFM8S(s) BUFM8S(s) BUFM10S(s) CKBUFM12S(s) BUFM12S(s)
BUFM14S(s) CKBUFM16S(s) BUFM16S(s) BUFM18S(s) CKBUFM20S(s)
BUFM20S(s) CKBUFM22SA(s) BUFM22SA(s) CKBUFM24S(s) BUFM24S(s)
CKBUFM26SA(s) BUFM26SA(s) CKBUFM32S(s) BUFM32SA(s) CKBUFM40S(s)
BUFM40SA(s) CKBUFM48S(s) BUFM48SA(s) DEL1M1W(s) CKBUFM1W
BUFM2W CKBUFM2W CKBUFM3W(s) BUFM3W(s) CKBUFM4W
BUFM4W DEL1M4W(s) BUFM5W(s) CKBUFM6W BUFM6W
CKBUFM8W BUFM8W BUFM10W CKBUFM12W BUFM12W
BUFM14W CKBUFM16W BUFM16W BUFM18W CKBUFM20W
BUFM20W CKBUFM22WA BUFM22WA CKBUFM24W BUFM24W
CKBUFM26WA BUFM26WA CKBUFM32W BUFM32WA CKBUFM40W
BUFM40WA CKBUFM48W BUFM48WA CKBUFM1R(s) BUFM2R(s)
CKBUFM2R(s) CKBUFM3R(s) BUFM3R(s) CKBUFM4R(s) BUFM4R(s)
DEL1M4R(s) BUFM5R(s) CKBUFM6R(s) BUFM6R(s) CKBUFM8R(s)
BUFM8R(s) BUFM10R(s) CKBUFM12R(s) BUFM12R(s) BUFM14R(s)
CKBUFM16R(s) BUFM16R(s) BUFM18R(s) CKBUFM20R(s) BUFM20R(s)
CKBUFM22RA(s) BUFM22RA(s) CKBUFM24R(s) BUFM24R(s) CKBUFM26RA(s)
BUFM26RA(s) CKBUFM32R(s) BUFM32RA(s) CKBUFM40R(s) BUFM40RA(s)
CKBUFM48R(s) BUFM48RA(s)
DELAY FOOTPRINT (DEL1M1S) :
DEL4M1S DEL3M1S DEL2M1S DEL1M1S DEL4M4S
DEL3M4S DEL2M4S DEL1M4S DEL4M1W DEL3M1W
DEL2M1W DEL4M4W DEL3M4W DEL2M4W DEL4M1R
DEL3M1R DEL2M1R DEL1M1R DEL4M4R DEL3M4R
DEL2M4R
Estimated WNS = -0.091ns, TNS = -76.574ns (cpu=0:00:13.0 mem=5356.5M)
Iter 0 ...
Collected 60356 nets for fixing
Evaluate 758(1592) resize, Select 120 cand. (cpu=0:00:30.5 mem=5363.0M)
Evaluate 23(3764) addBuf, Select 8 cand. (cpu=0:00:44.9 mem=5364.0M)
Evaluate 101(101) delBuf, Select 2 cand. (cpu=0:00:45.5 mem=5364.0M)
Commit 21 cand, 13 upSize, 2 downSize, 1 sameSize, 4 addBuf, 1 delBuf, 0 pinSwap (cpu=0:00:49.6 mem=5364.5M)
Calc. DC (cpu=0:00:50.9 mem=5364.5M) ***
Estimated WNS = -0.090ns, TNS = -73.582ns (cpu=0:00:57.3 mem=5364.5M)
Iter 1 ...
Collected 59346 nets for fixing
Evaluate 752(1594) resize, Select 396 cand. (cpu=0:01:18 mem=5367.0M)
Evaluate 23(2526) addBuf, Select 5 cand. (cpu=0:01:31 mem=5367.0M)
Evaluate 101(105) delBuf, Select 5 cand. (cpu=0:01:32 mem=5368.0M)
Commit 38 cand, 28 upSize, 7 downSize, 0 sameSize, 1 addBuf, 2 delBuf, 0 pinSwap (cpu=0:01:36 mem=5433.5M)
Calc. DC (cpu=0:01:38 mem=5433.5M) ***
Estimated WNS = -0.087ns, TNS = -70.612ns (cpu=0:01:44 mem=5433.5M)
Iter 2 ...
Collected 58898 nets for fixing
Evaluate 751(2323) resize, Select 164 cand. (cpu=0:02:16 mem=5434.3M)
Evaluate 21(5370) addBuf, Select 8 cand. (cpu=0:02:49 mem=5434.3M)
Evaluate 101(105) delBuf, Select 3 cand. (cpu=0:02:50 mem=5434.3M)
Commit 32 cand, 24 upSize, 1 downSize, 0 sameSize, 5 addBuf, 2 delBuf, 0 pinSwap (cpu=0:02:56 mem=5438.9M)
Calc. DC (cpu=0:02:58 mem=5438.9M) ***
Estimated WNS = -0.180ns, TNS = -132.645ns (cpu=0:03:04 mem=5438.9M)
*summary: 76 instances changed cell type
density after = 60.299%
*** Finish Post Route Setup Fixing (cpu=0:03:05 mem=5315.3M) ***
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
*** Timing NOT met, worst failing slack is -0.181
*** Check timing (0:00:00.3)
Starting refinePlace ...
Spread Effort: high, post-route mode.
Finished Phase I. CPU Time = 0:00:17.8, Real Time = 0:00:18.0
move report: preRPlace moves 4199 insts, mean move: 0.77 um, max move: 5.20 um
max move on inst (top/i_gmu_groestl/dp_fx2_256_rounds_mc/FE_OCPC22085_n51): (337.00, 415.20) --> (331.80, 415.20)
move report: rPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: overall moves 4199 insts, mean move: 0.77 um, max move: 5.20 um
max move on inst (top/i_gmu_groestl/dp_fx2_256_rounds_mc/FE_OCPC22085_n51): (337.00, 415.20) --> (331.80, 415.20)
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 5.20 um
inst (top/i_gmu_groestl/dp_fx2_256_rounds_mc/FE_OCPC22085_n51) with max move: (337, 415.2) -> (331.8, 415.2)
mean (X+Y) = 0.77 um
Total instances moved : 4199
*** cpu=0:00:19.5 mem=5124.6M mem(used)=0.0M***
Total net length = 1.413e+07 (6.599e+06 7.531e+06) (ext = 0.000e+00)
default core: bins with density > 0.75 = 24.5 % ( 1901 / 7744 )
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
Summary (cpu=21.65min real=21.65min mem=5124.6M)
------------------------------------------------------------
+--------------------+---------+
| Setup mode | all |
+--------------------+---------+
| WNS (ns):| -0.181 |
| TNS (ns):|-132.637 |
| Violating Paths:| 2703 |
| All Paths:| 84861 |
+--------------------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 0 (0) | 0.000 | 0 (0) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 60.299%
------------------------------------------------------------
**optDesign ... cpu = 0:38:27, real = 0:38:31, mem = 5419.5M **
*** Timing NOT met, worst failing slack is -0.181
*** Check timing (0:00:00.1)
setClockDomains -fromType register -toType register
**WARN: (ENCCTE-318): Paths not in the reg2reg domain will be added 1000ns slack adjustment
*** Timing NOT met, worst failing slack is -0.181
*** Check timing (0:01:21)
Active setup views: dummy_slow_view ethz_blake_slow_view ethz_groestl_slow_view ethz_jh_slow_view ethz_keccak_slow_view ethz_sha2_slow_view ethz_skein_slow_view gmu_blake_slow_view gmu_groestl_slow_view gmu_jh_slow_view gmu_keccak_slow_view gmu_sha2_slow_view gmu_skein_slow_view ram1_slow_view ram2_slow_view ram3_slow_view test_slow_view
Active hold views: hold_fast_view
-routeWithEco false # bool, default=false, user setting
-routeWithEco true # bool, default=false, user setting
-routeSelectedNetOnly false # bool, default=false
-routeWithTimingDriven true # bool, default=false, user setting
-routeWithTimingDriven false # bool, default=false, user setting
-routeWithSiDriven false # bool, default=false, user setting
-drouteStartIteration 0 # int, default=0, user setting
-drouteStartIteration 0 # int, default=0
globalDetailRoute
#Start globalDetailRoute on Fri Sep 30 00:40:32 2011
#
Closing parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d'. 391032 times net's RC data read were performed.
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_0 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_1 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_2 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_3 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_4 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_5 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_6 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_7 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_8 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_9 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_10 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_11 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_12 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_13 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_14 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_15 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_16 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_17 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_18 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34 Repeated 20 times. Will be suppressed.) Power/Ground pin VSSIO of instance fillperi_N_19 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRDB-733) PIN AlgSelxSI[0] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN AlgSelxSI[1] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN AlgSelxSI[2] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN AlgSelxSI[3] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN ClkDxCI in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN ClkxCI in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN CoreScanEnxTI in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN CoreScanInxTI in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[0] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[10] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[11] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[12] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[13] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[14] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[15] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[1] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[2] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[3] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[4] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733 Repeated 20 times. Will be suppressed.) PIN DataOutxDO[5] in CELL_VIEW shabziger_chip,init does not have physical port
#NanoRoute Version v10.12-s010 NR110720-1815/10_10_USR2-UB
#Loading the last recorded routing design signature
#Created 74 NETS and 0 SPECIALNETS new signatures
#Summary of the placement changes since last routing:
# Number of instances added (including moved) = 4186
# Number of instances deleted (including moved) = 4118
# Number of instances resized = 602
# Number of instances with same cell size swap = 7
# Number of instances with pin swaps = 24
# Total number of placement changes (moved instances are counted twice) = 8906
#Using multithreading with 8 threads.
# ME1 H Track-Pitch = 0.200 Line-2-Via Pitch = 0.185
# ME2 V Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME3 H Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME4 V Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME5 H Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME6 V Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME7 H Track-Pitch = 0.400 Line-2-Via Pitch = 0.400
# ME8 V Track-Pitch = 4.000 Line-2-Via Pitch = 4.000
#Merging special wires using 8 threads...
#WARNING (NRDB-1005) Can not establish connection to PIN Z at (998.250 1013.675) on ME1 for NET DataOutxD[1]. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN Z at (626.925 950.690) on ME1 for NET FE_OFCN23416_FE_OFN220_DataOutxD_4_. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN Z at (1215.910 902.100) on ME1 for NET FE_OFCN23421_FE_OFN106_OutSelxS_3_. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN A at (1211.580 902.200) on ME1 for NET FE_OFN106_OutSelxS_3_. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN A at (624.535 950.600) on ME1 for NET FE_OFN220_DataOutxD_4_. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (967.150 810.235) on ME1 for NET top/ClkxC__L6_N25. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (974.550 810.235) on ME1 for NET top/ClkxC__L6_N25. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (937.950 833.765) on ME1 for NET top/ClkxC__L6_N26. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (890.350 779.765) on ME1 for NET top/ClkxC__L6_N27. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (879.550 779.765) on ME1 for NET top/ClkxC__L6_N27. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (967.150 795.835) on ME1 for NET top/ClkxC__L6_N30. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (981.305 810.240) on ME1 for NET top/ClkxC__L6_N31. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (986.510 810.240) on ME1 for NET top/ClkxC__L6_N31. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (981.310 792.280) on ME1 for NET top/ClkxC__L6_N31. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (1015.550 770.635) on ME1 for NET top/ClkxC__L6_N32. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (1012.510 747.320) on ME1 for NET top/ClkxC__L6_N32. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (1008.750 770.635) on ME1 for NET top/ClkxC__L6_N32. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (1000.110 747.320) on ME1 for NET top/ClkxC__L6_N33. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (995.105 747.360) on ME1 for NET top/ClkxC__L6_N33. The NET is considered partially routed.
#WARNING (NRDB-1005 Repeated 20 times. Will be suppressed.) Can not establish connection to PIN CK at (1005.750 747.365) on ME1 for NET top/ClkxC__L6_N33. The NET is considered partially routed.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/CoreOutxD_2__17_ are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/FE_OFN3816_CoreOutxD_10__16_ are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_ethz_groestl/i_q/i_subbytes_0/n765 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_ethz_groestl/i_q/i_subbytes_0/n832 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_ethz_groestl/i_q/n699 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_ethz_jh/n32743 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_ethz_keccak/FE_OFN15444_StateTempxD_283_ are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_ethz_keccak/StateTempxD[1035] are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_ethz_keccak/StateTempxD[176] are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_ethz_keccak/StateTempxD[206] are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_ethz_keccak/StateTempxD[523] are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_ethz_keccak/n11548 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_ethz_keccak/n11631 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_ethz_skein/add_x_351_5_n1 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_blake/datapath_gen/DP_OP_74J1_126_7150_n565 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_blake/datapath_gen/DP_OP_77J1_129_7063_n805 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_blake/datapath_gen/r_r[269] are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/FE_OCPN18447_n18849 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/FE_OCPN18962_n3449 are dangling and deleted.
#WARNING (NRDB-874 Repeated 20 times. Will be suppressed.) Some WIRE segments on routed NET top/i_gmu_groestl/FE_OCPN19383_n9906 are dangling and deleted.
#WARNING (EMS-27) Message (NRDB-874) has exceeded the current message display limit of 20.
#To increase the message display limit, refer to the product command reference manual.
#12227 routed nets are extracted.
# 10423 (3.67%) extracted nets are partially routed.
#267787 routed nets are imported.
#3737 routed nets are fixed|skipped|trivial (not extracted).
#Total number of nets = 283751.
#Number of eco nets is 10423
#
#Start data preparation...
#Force regenerating Ggrids.
#Auto generating G-grids with size=15 tracks, using layer ME2's pitch = 0.200.
#Using automatically generated G-grids.
#
#Data preparation is done on Fri Sep 30 00:40:59 2011
#
#Analyzing routing resource...
#Routing resource analysis is done on Fri Sep 30 00:41:03 2011
#
# Resource Analysis:
#
# Routing #Avail #Track #Total %Gcell
# Layer Direction Track Blocked Gcell Blocked
# --------------------------------------------------------------
# Metal 1 H 5808 3565 391250 74.25%
# Metal 2 V 5718 3657 391250 43.74%
# Metal 3 H 5885 3489 391250 36.36%
# Metal 4 V 5858 3516 391250 42.89%
# Metal 5 H 7164 2209 391250 22.09%
# Metal 6 V 7101 2273 391250 29.79%
# Metal 7 H 2749 1937 391250 24.29%
# Metal 8 V 239 228 391250 61.74%
# --------------------------------------------------------------
# Total 40525 36.22% 3130000 41.89%
#
# 1567 nets (0.55%) with 1 preferred extra spacing.
# 9 nets (0.00%) with 2 preferred extra spacing.
#
#
#cpu time = 00:00:05, elapsed time = 00:00:05, memory = 5349.00 (Mb)
#
#start global routing iteration 1...
#cpu time = 00:00:04, elapsed time = 00:00:02, memory = 5353.00 (Mb)
#
#start global routing iteration 2...
#cpu time = 00:00:01, elapsed time = 00:00:01, memory = 5395.00 (Mb)
#
#start global routing iteration 3...
#cpu time = 00:00:09, elapsed time = 00:00:04, memory = 5356.00 (Mb)
#
#
# Congestion Analysis: (blocked Gcells are excluded)
#
# OverCon OverCon OverCon OverCon
# #Gcell #Gcell #Gcell #Gcell %Gcell
# Layer (1-4) (5-8) (9-12) (13-16) OverCon
# --------------------------------------------------------------------------
# Metal 1 1332(0.90%) 0(0.00%) 0(0.00%) 0(0.00%) (0.90%)
# Metal 2 8191(3.32%) 786(0.32%) 113(0.05%) 14(0.01%) (3.69%)
# Metal 3 3283(1.32%) 236(0.09%) 6(0.00%) 0(0.00%) (1.41%)
# Metal 4 1704(0.68%) 12(0.00%) 0(0.00%) 0(0.00%) (0.68%)
# Metal 5 121(0.04%) 0(0.00%) 0(0.00%) 0(0.00%) (0.04%)
# Metal 6 105(0.03%) 0(0.00%) 0(0.00%) 0(0.00%) (0.03%)
# Metal 7 141(0.05%) 0(0.00%) 0(0.00%) 0(0.00%) (0.05%)
# Metal 8 54(0.04%) 0(0.00%) 0(0.00%) 0(0.00%) (0.04%)
# --------------------------------------------------------------------------
# Total 14931(0.77%) 1034(0.05%) 119(0.01%) 14(0.00%) (0.83%)
#
# The worst congested Gcell overcon (routing demand over resource in number of tracks) = 16
#
#Complete Global Routing.
#Total number of nets with non-default rule or having extra spacing = 1576
#Total wire length = 16457230 um.
#Total half perimeter of net bounding box = 14225240 um.
#Total wire length on LAYER ME1 = 181330 um.
#Total wire length on LAYER ME2 = 2607061 um.
#Total wire length on LAYER ME3 = 3568968 um.
#Total wire length on LAYER ME4 = 3069453 um.
#Total wire length on LAYER ME5 = 3623530 um.
#Total wire length on LAYER ME6 = 2726377 um.
#Total wire length on LAYER ME7 = 509431 um.
#Total wire length on LAYER ME8 = 171078 um.
#Total number of vias = 2798387
#Total number of multi-cut vias = 27524 ( 1.0%)
#Total number of single cut vias = 2770863 ( 99.0%)
#Up-Via Summary (total 2798387):
# single-cut multi-cut Total
#-----------------------------------------------------------
# Metal 1 995070 (100.0%) 0 ( 0.0%) 995070
# Metal 2 1060634 (100.0%) 0 ( 0.0%) 1060634
# Metal 3 381055 (100.0%) 0 ( 0.0%) 381055
# Metal 4 200005 (100.0%) 48 ( 0.0%) 200053
# Metal 5 125188 (100.0%) 0 ( 0.0%) 125188
# Metal 6 22 ( 0.1%) 27476 ( 99.9%) 27498
# Metal 7 8889 (100.0%) 0 ( 0.0%) 8889
#-----------------------------------------------------------
# 2770863 ( 99.0%) 27524 ( 1.0%) 2798387
#
#Max overcon = 16 tracks.
#Total overcon = 0.83%.
#Worst layer Gcell overcon rate = 1.41%.
#Cpu time = 00:00:35
#Elapsed time = 00:00:27
#Increased memory = 81.00 (Mb)
#Total memory = 5318.00 (Mb)
#Peak memory = 5448.00 (Mb)
#Using multithreading with 8 threads.
#
#Start Detail Routing...
#start initial detail routing ...
# completing 10% with 595 violations
# elapsed time = 00:00:06, memory = 5660.00 (Mb)
# completing 20% with 743 violations
# elapsed time = 00:00:12, memory = 5703.00 (Mb)
# completing 30% with 893 violations
# elapsed time = 00:00:17, memory = 5666.00 (Mb)
# completing 40% with 1030 violations
# elapsed time = 00:00:24, memory = 5704.00 (Mb)
# completing 50% with 1231 violations
# elapsed time = 00:00:33, memory = 5736.00 (Mb)
# completing 60% with 1345 violations
# elapsed time = 00:00:39, memory = 5698.00 (Mb)
# completing 70% with 1431 violations
# elapsed time = 00:00:46, memory = 5713.00 (Mb)
# completing 80% with 1594 violations
# elapsed time = 00:00:53, memory = 5731.00 (Mb)
# completing 90% with 1709 violations
# elapsed time = 00:00:59, memory = 5674.00 (Mb)
# completing 100% with 1853 violations
# elapsed time = 00:01:12, memory = 5516.00 (Mb)
# ECO: 0.0% of the total area was rechecked for DRC, and 9.1% required routing.
# number of violations = 1853
#4.7% of the total area is being checked for drcs
#4.7% of the total area was checked
# number of violations = 3471
#cpu time = 00:07:08, elapsed time = 00:01:37, memory = 5466.00 (Mb)
#start 1st optimization iteration ...
# number of violations = 770
#cpu time = 00:01:34, elapsed time = 00:00:24, memory = 5458.00 (Mb)
#start 2nd optimization iteration ...
# number of violations = 613
#cpu time = 00:00:15, elapsed time = 00:00:04, memory = 5458.00 (Mb)
#start 3rd optimization iteration ...
# number of violations = 560
#cpu time = 00:00:12, elapsed time = 00:00:04, memory = 5458.00 (Mb)
#start 4th optimization iteration ...
# number of violations = 552
#cpu time = 00:00:13, elapsed time = 00:00:04, memory = 5458.00 (Mb)
#start 5th optimization iteration ...
# number of violations = 551
#cpu time = 00:00:12, elapsed time = 00:00:04, memory = 5458.00 (Mb)
#start 6th optimization iteration ...
# number of violations = 553
#cpu time = 00:00:13, elapsed time = 00:00:04, memory = 5458.00 (Mb)
#start 7th optimization iteration ...
# number of violations = 549
#cpu time = 00:00:13, elapsed time = 00:00:04, memory = 5458.00 (Mb)
#start 8th optimization iteration ...
# number of violations = 550
#cpu time = 00:00:13, elapsed time = 00:00:04, memory = 5458.00 (Mb)
#start 9th optimization iteration ...
# number of violations = 547
#cpu time = 00:00:13, elapsed time = 00:00:04, memory = 5458.00 (Mb)
#start 10th optimization iteration ...
# number of violations = 549
#cpu time = 00:00:13, elapsed time = 00:00:04, memory = 5458.00 (Mb)
#start 11th optimization iteration ...
# number of violations = 542
#cpu time = 00:00:24, elapsed time = 00:00:07, memory = 5459.00 (Mb)
#start 12th optimization iteration ...
# number of violations = 537
#cpu time = 00:00:25, elapsed time = 00:00:07, memory = 5459.00 (Mb)
#start 13th optimization iteration ...
# number of violations = 542
#cpu time = 00:00:24, elapsed time = 00:00:07, memory = 5459.00 (Mb)
#start 14th optimization iteration ...
# number of violations = 538
#cpu time = 00:00:24, elapsed time = 00:00:07, memory = 5459.00 (Mb)
#start 15th optimization iteration ...
# number of violations = 523
#cpu time = 00:00:27, elapsed time = 00:00:07, memory = 5459.00 (Mb)
#start 16th optimization iteration ...
# number of violations = 504
#cpu time = 00:00:38, elapsed time = 00:00:09, memory = 5461.00 (Mb)
#start 17th optimization iteration ...
# number of violations = 499
#cpu time = 00:00:38, elapsed time = 00:00:09, memory = 5467.00 (Mb)
#start 18th optimization iteration ...
# number of violations = 502
#cpu time = 00:00:38, elapsed time = 00:00:09, memory = 5467.00 (Mb)
#start 19th optimization iteration ...
# number of violations = 497
#cpu time = 00:00:38, elapsed time = 00:00:09, memory = 5467.00 (Mb)
#start 20th optimization iteration ...
# number of violations = 496
#cpu time = 00:00:38, elapsed time = 00:00:09, memory = 5467.00 (Mb)
#Complete Detail Routing.
#Total number of nets with non-default rule or having extra spacing = 1576
#Total wire length = 16456668 um.
#Total half perimeter of net bounding box = 14225240 um.
#Total wire length on LAYER ME1 = 181313 um.
#Total wire length on LAYER ME2 = 2603921 um.
#Total wire length on LAYER ME3 = 3566001 um.
#Total wire length on LAYER ME4 = 3072360 um.
#Total wire length on LAYER ME5 = 3626176 um.
#Total wire length on LAYER ME6 = 2726561 um.
#Total wire length on LAYER ME7 = 509358 um.
#Total wire length on LAYER ME8 = 170976 um.
#Total number of vias = 2805538
#Total number of multi-cut vias = 27532 ( 1.0%)
#Total number of single cut vias = 2778006 ( 99.0%)
#Up-Via Summary (total 2805538):
# single-cut multi-cut Total
#-----------------------------------------------------------
# Metal 1 996750 (100.0%) 0 ( 0.0%) 996750
# Metal 2 1062992 (100.0%) 0 ( 0.0%) 1062992
# Metal 3 383115 (100.0%) 0 ( 0.0%) 383115
# Metal 4 200930 (100.0%) 49 ( 0.0%) 200979
# Metal 5 125338 (100.0%) 0 ( 0.0%) 125338
# Metal 6 0 ( 0.0%) 27483 (100.0%) 27483
# Metal 7 8881 (100.0%) 0 ( 0.0%) 8881
#-----------------------------------------------------------
# 2778006 ( 99.0%) 27532 ( 1.0%) 2805538
#
#Total number of DRC violations = 496
#Total number of violations on LAYER ME1 = 18
#Total number of violations on LAYER ME2 = 148
#Total number of violations on LAYER ME3 = 100
#Total number of violations on LAYER ME4 = 230
#Total number of violations on LAYER ME5 = 0
#Total number of violations on LAYER ME6 = 0
#Total number of violations on LAYER ME7 = 0
#Total number of violations on LAYER ME8 = 0
#Cpu time = 00:16:02
#Elapsed time = 00:04:06
#Increased memory = 67.00 (Mb)
#Total memory = 5385.00 (Mb)
#Peak memory = 6198.00 (Mb)
#
#Start Post Routing Optimization.
#start 1st post routing optimization iteration ...
# number of DRC violations = 496
#cpu time = 00:04:41, elapsed time = 00:01:26, memory = 5352.00 (Mb)
#start 2nd post routing optimization iteration ...
# number of DRC violations = 496
#cpu time = 00:04:32, elapsed time = 00:01:23, memory = 5403.00 (Mb)
#start 3rd post routing optimization iteration ...
# number of DRC violations = 496
#cpu time = 00:04:33, elapsed time = 00:01:22, memory = 5427.00 (Mb)
#Complete Post Routing Optimization.
#Cpu time = 00:13:47
#Elapsed time = 00:04:13
#Increased memory = 42.00 (Mb)
#Total memory = 5427.00 (Mb)
#Peak memory = 6201.00 (Mb)
#Total number of nets with non-default rule or having extra spacing = 1576
#Total wire length = 16456668 um.
#Total half perimeter of net bounding box = 14225240 um.
#Total wire length on LAYER ME1 = 181313 um.
#Total wire length on LAYER ME2 = 2603921 um.
#Total wire length on LAYER ME3 = 3566001 um.
#Total wire length on LAYER ME4 = 3072360 um.
#Total wire length on LAYER ME5 = 3626176 um.
#Total wire length on LAYER ME6 = 2726561 um.
#Total wire length on LAYER ME7 = 509358 um.
#Total wire length on LAYER ME8 = 170976 um.
#Total number of vias = 2805538
#Total number of multi-cut vias = 27532 ( 1.0%)
#Total number of single cut vias = 2778006 ( 99.0%)
#Up-Via Summary (total 2805538):
# single-cut multi-cut Total
#-----------------------------------------------------------
# Metal 1 996750 (100.0%) 0 ( 0.0%) 996750
# Metal 2 1062992 (100.0%) 0 ( 0.0%) 1062992
# Metal 3 383115 (100.0%) 0 ( 0.0%) 383115
# Metal 4 200930 (100.0%) 49 ( 0.0%) 200979
# Metal 5 125338 (100.0%) 0 ( 0.0%) 125338
# Metal 6 0 ( 0.0%) 27483 (100.0%) 27483
# Metal 7 8881 (100.0%) 0 ( 0.0%) 8881
#-----------------------------------------------------------
# 2778006 ( 99.0%) 27532 ( 1.0%) 2805538
#
#Total number of DRC violations = 496
#Total number of violations on LAYER ME1 = 18
#Total number of violations on LAYER ME2 = 148
#Total number of violations on LAYER ME3 = 100
#Total number of violations on LAYER ME4 = 230
#Total number of violations on LAYER ME5 = 0
#Total number of violations on LAYER ME6 = 0
#Total number of violations on LAYER ME7 = 0
#Total number of violations on LAYER ME8 = 0
#
#start routing for process antenna violation fix ...
#cpu time = 00:00:25, elapsed time = 00:00:15, memory = 5447.00 (Mb)
#
#Total number of nets with non-default rule or having extra spacing = 1576
#Total wire length = 16456681 um.
#Total half perimeter of net bounding box = 14225240 um.
#Total wire length on LAYER ME1 = 181315 um.
#Total wire length on LAYER ME2 = 2603959 um.
#Total wire length on LAYER ME3 = 3566007 um.
#Total wire length on LAYER ME4 = 3072338 um.
#Total wire length on LAYER ME5 = 3626175 um.
#Total wire length on LAYER ME6 = 2726553 um.
#Total wire length on LAYER ME7 = 509358 um.
#Total wire length on LAYER ME8 = 170976 um.
#Total number of vias = 2805631
#Total number of multi-cut vias = 27532 ( 1.0%)
#Total number of single cut vias = 2778099 ( 99.0%)
#Up-Via Summary (total 2805631):
# single-cut multi-cut Total
#-----------------------------------------------------------
# Metal 1 996751 (100.0%) 0 ( 0.0%) 996751
# Metal 2 1063040 (100.0%) 0 ( 0.0%) 1063040
# Metal 3 383153 (100.0%) 0 ( 0.0%) 383153
# Metal 4 200936 (100.0%) 49 ( 0.0%) 200985
# Metal 5 125338 (100.0%) 0 ( 0.0%) 125338
# Metal 6 0 ( 0.0%) 27483 (100.0%) 27483
# Metal 7 8881 (100.0%) 0 ( 0.0%) 8881
#-----------------------------------------------------------
# 2778099 ( 99.0%) 27532 ( 1.0%) 2805631
#
#Total number of DRC violations = 496
#Total number of net violated process antenna rule = 0
#Total number of violations on LAYER ME1 = 26
#Total number of violations on LAYER ME2 = 162
#Total number of violations on LAYER ME3 = 109
#Total number of violations on LAYER ME4 = 199
#Total number of violations on LAYER ME5 = 0
#Total number of violations on LAYER ME6 = 0
#Total number of violations on LAYER ME7 = 0
#Total number of violations on LAYER ME8 = 0
#
#detailRoute Statistics:
#Cpu time = 00:30:21
#Elapsed time = 00:08:42
#Increased memory = 124.00 (Mb)
#Total memory = 5442.00 (Mb)
#Peak memory = 6201.00 (Mb)
#Updating routing design signature
#Created 3310 library cell signatures
#Created 283751 NETS and 0 SPECIALNETS signatures
#Created 310837 instance signatures
#
#globalDetailRoute statistics:
#Cpu time = 00:31:27
#Elapsed time = 00:09:46
#Increased memory = -875.00 (Mb)
#Total memory = 4532.00 (Mb)
#Peak memory = 6201.00 (Mb)
#Number of warnings = 81
#Total number of warnings = 184
#Number of fails = 0
#Total number of fails = 0
#Complete globalDetailRoute on Fri Sep 30 00:50:18 2011
#
**optDesign ... cpu = 1:13:43, real = 0:52:05, mem = 4532.0M **
-routeWithEco false # bool, default=false, user setting
-routeSelectedNetOnly false # bool, default=false
-routeWithTimingDriven true # bool, default=false, user setting
-routeWithSiDriven false # bool, default=false, user setting
-drouteStartIteration 0 # int, default=0, user setting
Extraction called for design 'shabziger_chip' of instances=310836 and nets=283751 using extraction engine 'postRoute' at effort level 'low' .
Detail RC Extraction called for design shabziger_chip.
RC Extraction called in multi-corner(2) mode.
Process corner(s) are loaded.
Corner: rc_worst
Corner: rc_best
extractDetailRC Option : -outfile ../tmp/shabziger_chip_wukc1u_9079.rcdb.d -maxResLength 200 -extended
RC Mode: Detail [Extended CapTable, RC Table Resistances]
RC Corner Indexes 0 1
Capacitance Scaling Factor : 1.00000 1.00000
Coupling Cap. Scaling Factor : 1.00000 1.00000
Resistance Scaling Factor : 1.00000 1.00000
Clock Cap. Scaling Factor : 1.00000 1.00000
Clock Res. Scaling Factor : 1.00000 1.00000
Shrink Factor : 1.00000
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Checking LVS Completed (CPU Time= 0:00:01.2 MEM= 4532.0M)
Creating parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' in memory efficient access mode for storing RC.
Extracted 10% (CPU Time= 0:00:07.1 MEM= 4750.8M)
Extracted 20.0001% (CPU Time= 0:00:13.7 MEM= 4750.8M)
Extracted 30.0001% (CPU Time= 0:00:17.5 MEM= 4750.8M)
Extracted 40% (CPU Time= 0:00:23.7 MEM= 4750.8M)
Extracted 50.0001% (CPU Time= 0:00:30.8 MEM= 4776.9M)
Extracted 60.0001% (CPU Time= 0:00:35.3 MEM= 4781.9M)
Extracted 70% (CPU Time= 0:00:43.8 MEM= 4781.9M)
Extracted 80.0001% (CPU Time= 0:00:51.5 MEM= 4781.9M)
Extracted 90.0001% (CPU Time= 0:00:56.3 MEM= 4781.9M)
Extracted 100% (CPU Time= 0:01:07 MEM= 4781.9M)
Nr. Extracted Resistors : 5589300
Nr. Extracted Ground Cap. : 5868140
Nr. Extracted Coupling Cap. : 0
Opening parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' for reading.
Detail RC Extraction DONE (CPU Time: 0:01:10 Real Time: 0:01:13 MEM: 4532.047M)
Using new Cte TW Api base...#################################################################################
# Design Stage: PostRoute
# Design Mode: 65nm
# Analysis Mode: MMMC non-OCV
# Extraction Mode: detail/spef
# Delay Calculation Options: engine=signalStorm signOff=true SIAware=false(opt)
# Switching Delay Calculation Engine to signalStorm
#################################################################################
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.4, MEM = 4556.3M, InitMEM = 4556.3M)
Start delay calculation using Signal Storm (mem=4556.258M)...
delayCal using detail RC...
Opening parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' for reading.
RC Database In Completed (CPU Time= 0:00:01.4 MEM= 4624.7M)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Delay calculation completed. (cpu=0:00:48.1 real=0:00:48.0 mem=5091.922M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5091.9M, InitMEM = 5091.9M)
Start delay calculation using Signal Storm (mem=5091.922M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:24.1 real=0:00:24.0 mem=5092.926M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5092.9M, InitMEM = 5092.9M)
Start delay calculation using Signal Storm (mem=5092.926M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:24.4 real=0:00:25.0 mem=5092.926M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5092.9M, InitMEM = 5092.9M)
Start delay calculation using Signal Storm (mem=5092.926M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:24.6 real=0:00:24.0 mem=5092.926M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5092.9M, InitMEM = 5092.9M)
Start delay calculation using Signal Storm (mem=5092.926M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:24.8 real=0:00:25.0 mem=5092.926M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5092.9M, InitMEM = 5092.9M)
Start delay calculation using Signal Storm (mem=5092.926M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:24.6 real=0:00:25.0 mem=5092.926M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5092.9M, InitMEM = 5092.9M)
Start delay calculation using Signal Storm (mem=5092.926M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:25.2 real=0:00:25.0 mem=5092.926M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5092.9M, InitMEM = 5092.9M)
Start delay calculation using Signal Storm (mem=5092.926M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:25.2 real=0:00:25.0 mem=5092.926M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5092.9M, InitMEM = 5092.9M)
Start delay calculation using Signal Storm (mem=5092.926M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:26.8 real=0:00:27.0 mem=5092.926M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5092.9M, InitMEM = 5092.9M)
Start delay calculation using Signal Storm (mem=5092.926M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:25.9 real=0:00:26.0 mem=5092.926M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5092.9M, InitMEM = 5092.9M)
Start delay calculation using Signal Storm (mem=5092.926M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:26.8 real=0:00:27.0 mem=5092.926M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5092.9M, InitMEM = 5092.9M)
Start delay calculation using Signal Storm (mem=5092.926M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:26.1 real=0:00:26.0 mem=5092.926M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5092.9M, InitMEM = 5092.9M)
Start delay calculation using Signal Storm (mem=5092.926M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:27.8 real=0:00:28.0 mem=5092.926M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5092.9M, InitMEM = 5092.9M)
Start delay calculation using Signal Storm (mem=5092.926M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:26.3 real=0:00:26.0 mem=5092.926M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5092.9M, InitMEM = 5092.9M)
Start delay calculation using Signal Storm (mem=5092.926M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:26.5 real=0:00:26.0 mem=5092.926M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5092.9M, InitMEM = 5092.9M)
Start delay calculation using Signal Storm (mem=5092.926M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:26.4 real=0:00:26.0 mem=5092.926M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5092.9M, InitMEM = 5092.9M)
Start delay calculation using Signal Storm (mem=5092.926M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:35.1 real=0:00:35.0 mem=5092.926M 0)
*** CDM Built up (cpu=0:08:50 real=0:08:50 mem= 5092.9M) ***
*** Timing NOT met, worst failing slack is -0.192
*** Check timing (0:09:55)
Clearing footprints for all libraries
Loading footprints for all corners
***** CTE Mode is Operational *****
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
Info: 40 io nets excluded
Info: 567 clock nets excluded from IPO operation.
*** Starting new resizing ***
density before resizing = 60.299%
start postIPO sizing
338 instances have been resized
*summary: 338 instances changed cell type
density after resizing = 60.299%
*** Finish new resizing (cpu=0:00:55.5 mem=5451.8M) ***
*** Starting resizing for timing improvement ***
702 instances have been resized
density change = 0.000%
*summary: 702 instances changed cell type
*** Finish resizing for timing improvement (cpu=0:00:42.2 mem=5457.1M) ***
Instances Resized for DRV : 0
Instances Resized for Timing: 1040
Total Instances Resized : 1040
Current TNS: -144.173 Prev TNS: -146.557
Current WNS: -0.192 Prev WNS: -0.192
Restoring original footprint information
Clearing footprints for all libraries
Loading footprints for all corners
Latch borrow mode reset to max_borrow
Reported timing to dir timingReports_final
**optDesign ... cpu = 1:27:43, real = 1:06:10, mem = 4796.5M **
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
optDesign Final Summary
------------------------------------------------------------
+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| -0.192 | -0.192 | 0.509 | 0.322 | 18.537 | 15.619 |
| TNS (ns):|-144.008 |-144.008 | 0.000 | 0.000 | 0.000 | 0.000 |
| Violating Paths:| 2711 | 2711 | 0 | 0 | 0 | 0 |
| All Paths:| 85005 | 46605 | 63302 | 19 | 2 | 15 |
+--------------------+---------+---------+---------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 0 (0) | 0.000 | 0 (0) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 60.299%
------------------------------------------------------------
**optDesign ... cpu = 1:38:14, real = 1:15:40, mem = 5105.0M **
**INFO : removing temp dont-use cells (LVT only flow version : 4)
Deleting the dont_use list
*** Finished optDesign ***
Opening parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' for reading.
Closing parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d'. 9118777 times net's RC data read were performed.
RC Database In Completed (CPU Time= 0:00:01.2 MEM= 4910.2M)
timeDesign -expandedViews -reportOnly -outDir timingReports_final -prefix shabziger.postrouteopt.expV
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
timeDesign Summary
------------------------------------------------------------
+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| -0.192 | -0.192 | 0.509 | 0.322 | 18.537 | 15.619 |
| TNS (ns):|-144.008 |-144.008 | 0.000 | 0.000 | 0.000 | 0.000 |
| Violating Paths:| 2711 | 2711 | 0 | 0 | 0 | 0 |
| All Paths:| 85005 | 46605 | 63302 | 19 | 2 | 15 |
+--------------------+---------+---------+---------+---------+---------+---------+
|dummy_slow_view | 7.880 | 7.880 | 9.049 | 8.722 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5131 | 2517 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_blake_slow_view| 0.035 | 0.035 | 3.902 | 3.722 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 8290 | 4385 | 3887 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_groestl_slow_view
| | -0.085 | -0.085 | 2.648 | 2.322 | N/A | N/A |
| | -1.848 | -1.848 | 0.000 | 0.000 | N/A | N/A |
| | 81 | 81 | 0 | 0 | N/A | N/A |
| | 8236 | 4070 | 4148 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_jh_slow_view | -0.044 | -0.044 | 2.049 | 1.722 | N/A | N/A |
| | -0.090 | -0.090 | 0.000 | 0.000 | N/A | N/A |
| | 3 | 3 | 0 | 0 | N/A | N/A |
| | 8801 | 4640 | 4143 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_keccak_slow_view
| | -0.060 | -0.060 | 0.730 | 0.722 | N/A | N/A |
| | -0.861 | -0.861 | 0.000 | 0.000 | N/A | N/A |
| | 51 | 51 | 0 | 0 | N/A | N/A |
| | 8346 | 4125 | 4203 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_sha2_slow_view | 0.105 | 0.105 | 2.501 | 2.222 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 7204 | 3554 | 3632 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_skein_slow_view| -0.078 | -0.078 | 1.603 | 1.522 | N/A | N/A |
| | -3.202 | -3.202 | 0.000 | 0.000 | N/A | N/A |
| | 90 | 90 | 0 | 0 | N/A | N/A |
| | 9002 | 4517 | 4467 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_blake_slow_view | -0.084 | -0.084 | 2.948 | 2.622 | N/A | N/A |
| | -4.642 | -4.642 | 0.000 | 0.000 | N/A | N/A |
| | 107 | 107 | 0 | 0 | N/A | N/A |
| | 9724 | 5498 | 4208 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_groestl_slow_view
| | -0.156 | -0.156 | 1.048 | 0.822 | N/A | N/A |
| | -56.937 | -56.937 | 0.000 | 0.000 | N/A | N/A |
| | 1017 | 1017 | 0 | 0 | N/A | N/A |
| | 9252 | 5088 | 4146 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_jh_slow_view | -0.077 | -0.077 | 0.649 | 0.322 | N/A | N/A |
| | -2.004 | -2.004 | 0.000 | 0.000 | N/A | N/A |
| | 96 | 96 | 0 | 0 | N/A | N/A |
| | 10269 | 5853 | 4398 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_keccak_slow_view| -0.192 | -0.192 | 0.648 | 0.322 | N/A | N/A |
| | -71.901 | -71.901 | 0.000 | 0.000 | N/A | N/A |
| | 1210 | 1210 | 0 | 0 | N/A | N/A |
| | 9926 | 5702 | 4206 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_sha2_slow_view | -0.060 | -0.060 | 0.509 | 0.522 | N/A | N/A |
| | -0.298 | -0.298 | 0.000 | 0.000 | N/A | N/A |
| | 15 | 15 | 0 | 0 | N/A | N/A |
| | 7986 | 4238 | 3730 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_skein_slow_view | -0.080 | -0.080 | 2.614 | 4.222 | N/A | N/A |
| | -2.394 | -2.394 | 0.000 | 0.000 | N/A | N/A |
| | 56 | 56 | 0 | 0 | N/A | N/A |
| | 10156 | 5551 | 4587 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ram1_slow_view | 5.156 | 5.156 | 9.049 | 8.722 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5237 | 2623 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ram2_slow_view | 4.908 | 4.908 | 9.049 | 8.722 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5237 | 2623 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ram3_slow_view | 3.366 | 3.366 | 9.049 | 8.722 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5240 | 2626 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|test_slow_view | 13.339 | 13.339 | 13.788 | 18.517 | 18.537 | 15.619 |
| | 0.000 | 0.000 | 0.000 | 0.000 | 0.000 | 0.000 |
| | 0 | 0 | 0 | 0 | 0 | 0 |
| | 85005 | 46605 | 63302 | 19 | 2 | 15 |
+--------------------+---------+---------+---------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 0 (0) | 0.000 | 0 (0) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 60.299%
------------------------------------------------------------
Reported timing to dir timingReports_final
Total CPU time: 197.25 sec
Total Real time: 144.0 sec
Total Memory Usage: 4910.214844 Mbytes
addFiller -cell {FILEP64W FILEP32W FILEP16W FILEP8W FILE6W FILE4W FILE3W FIL2W FILEP64S FILEP32S FILEP16S FILEP8S FILE6S FILE4S FILE3S FIL2S FILEP64R FILEP32R FILEP16R FILEP8R FILE6R FILE4R FILE3R FIL2R} -prefix fillcore
*INFO: Adding fillers to top-module.
*INFO: Added 1161 filler insts (cell FILEP64W / prefix fillcore).
*INFO: Added 5015 filler insts (cell FILEP64S / prefix fillcore).
*INFO: Added 247 filler insts (cell FILEP64R / prefix fillcore).
*INFO: Added 5375 filler insts (cell FILEP32W / prefix fillcore).
*INFO: Added 2342 filler insts (cell FILEP32S / prefix fillcore).
*INFO: Added 594 filler insts (cell FILEP32R / prefix fillcore).
*INFO: Added 18168 filler insts (cell FILEP16W / prefix fillcore).
*INFO: Added 6298 filler insts (cell FILEP16S / prefix fillcore).
*INFO: Added 1919 filler insts (cell FILEP16R / prefix fillcore).
*INFO: Added 36756 filler insts (cell FILEP8W / prefix fillcore).
*INFO: Added 8948 filler insts (cell FILEP8S / prefix fillcore).
*INFO: Added 4033 filler insts (cell FILEP8R / prefix fillcore).
*INFO: Added 22757 filler insts (cell FILE6W / prefix fillcore).
*INFO: Added 4609 filler insts (cell FILE6S / prefix fillcore).
*INFO: Added 2373 filler insts (cell FILE6R / prefix fillcore).
*INFO: Added 31523 filler insts (cell FILE4W / prefix fillcore).
*INFO: Added 5992 filler insts (cell FILE4S / prefix fillcore).
*INFO: Added 3293 filler insts (cell FILE4R / prefix fillcore).
*INFO: Added 22624 filler insts (cell FILE3W / prefix fillcore).
*INFO: Added 5799 filler insts (cell FILE3S / prefix fillcore).
*INFO: Added 2356 filler insts (cell FILE3R / prefix fillcore).
*INFO: Added 29926 filler insts (cell FIL2W / prefix fillcore).
*INFO: Added 4213 filler insts (cell FIL2S / prefix fillcore).
*INFO: Added 3085 filler insts (cell FIL2R / prefix fillcore).
*INFO: Total 229406 filler insts added - prefix fillcore (CPU: 0:00:04.0).
For 229406 new insts, *** Applied 4 GNC rules (cpu = 0:00:00.1)
*INFO: Checking for DRC violations on added fillers.
*INFO: Iteration 0-#1, Found 438425 DRC violations (real: 0:00:43.0).
For 182516 new insts, *** Applied 4 GNC rules (cpu = 0:00:00.1)
*INFO: Iteration 0-#2, Found 290370 DRC violations (real: 0:00:36.0).
For 102233 new insts, *** Applied 4 GNC rules (cpu = 0:00:00.1)
*INFO: Iteration 0-#3, Found 183880 DRC violations (real: 0:00:36.0).
For 58480 new insts, *** Applied 4 GNC rules (cpu = 0:00:00.0)
*INFO: Iteration 0-#4, Found 93508 DRC violations (real: 0:00:35.0).
For 28330 new insts, *** Applied 4 GNC rules (cpu = 0:00:00.0)
*INFO: Iteration 0-#5, Found 38873 DRC violations (real: 0:00:34.0).
For 9035 new insts, *** Applied 4 GNC rules (cpu = 0:00:00.0)
*INFO: Iteration 0-#6, Found 9411 DRC violations (real: 0:00:34.0).
For 1742 new insts, *** Applied 4 GNC rules (cpu = 0:00:00.0)
*INFO: Iteration 0-#7, Found 478 DRC violations (real: 0:00:33.0).
For 356 new insts, *** Applied 4 GNC rules (cpu = 0:00:00.0)
*INFO: Iteration 0-#8, Found 0 DRC violation (real: 0:00:33.0).
*INFO: Adding fillers to top-module.
*INFO: Added 151832 filler insts (cell FIL2R / prefix fillcore).
For 151832 new insts, *** Applied 4 GNC rules (cpu = 0:00:00.1)
*INFO: End DRC Checks. (real: 0:05:33 ).
*INFO: Replaced 291500 fillers which had DRC vio's, with 382692 new fillers.
addFiller -cell {FIL1W FIL1R FIL1S} -prefix fillcore
*INFO: Adding fillers to top-module.
*INFO: Added 63633 filler insts (cell FIL1W / prefix fillcore).
*INFO: Added 7552 filler insts (cell FIL1S / prefix fillcore).
*INFO: Added 26142 filler insts (cell FIL1R / prefix fillcore).
*INFO: Total 97327 filler insts added - prefix fillcore (CPU: 0:00:04.0).
For 97327 new insts, *** Applied 4 GNC rules (cpu = 0:00:00.0)
*INFO: Checking for DRC violations on added fillers.
*INFO: Iteration 0-#1, Found 0 DRC violation (real: 0:00:38.0).
*INFO: Adding fillers to top-module.
*INFO: Added 0 filler inst of any cell-type.
For 0 new insts, *** Applied 0 GNC rules.
*INFO: End DRC Checks. (real: 0:00:38.0 ).
saveDesign save/chip_shabziger_final.enc
Redoing specifyClockTree ...
Checking spec file integrity...
**WARN: (ENCSYT-3036): Design directory save/chip_shabziger_final.enc.dat exists, rename it to save/chip_shabziger_final.enc.dat.tmp.
If saveDesign succeeds, it will be deleted.
Writing Netlist "save/chip_shabziger_final.enc.dat/shabziger_chip.v.gz" ...
Saving clock tree spec file 'save/chip_shabziger_final.enc.dat/shabziger_chip.ctstch' ...
Saving configuration ...
Saving preference file save/chip_shabziger_final.enc.dat/enc.pref.tcl ...
Saving floorplan ...
Saving Drc markers ...
... No Drc file written since there is no markers found.
Saving placement ...
*** Completed savePlace (cpu=0:00:01.1 real=0:00:03.0 mem=5206.5M) ***
Saving route ...
*** Completed saveRoute (cpu=0:00:04.5 real=0:00:11.0 mem=5206.5M) ***
Writing DEF file 'save/chip_shabziger_final.enc.dat/shabziger_chip.def.gz', current time is Fri Sep 30 01:24:33 2011 ...
unitPerMicron=1000, dbgMicronPerDBU=0.001000, unitPerDBU=1.000000
DEF file 'save/chip_shabziger_final.enc.dat/shabziger_chip.def.gz' is written, current time is Fri Sep 30 01:24:34 2011 ...
*** Completed saveYieldMap (cpu=: 0:00:00.0 real=0:00:00.0 mem=: 0.000M) ***
setExtractRCMode -engine detail -coupled false -reduce 0.0
**WARN: (ENCEXT-1082): Option '-engine detail' is obsolete. Use '-engine postRoute [-effortLevel low]' to set extraction engine, which is based on recommended convention '-engine postRoute [-effortLevel ]'. The obsolete option still works in this release, but to avoid this warning and to ensure compatibility with future releases, update your script and configuration file to use recommended convention.
**WARN: (ENCEXT-1090): Option '-effortLevel low' specified in past directly by user or in-directly through 'timeDesign -signoff' or similar command. And option '-engine detail' specified now. User is recommended to use either '-engine postRoute [-effortLevel ]' or '-engine default|detail|cce|signoff' because '-engine default|detail|cce|signoff' has implicit meaning for '-effortLevel'. In this case, most recent engine option specified '-engine detail' will be honored by the tool and '-effortLevel' ignored.
**WARN: (ENCEXT-3493): Extraction mode changed by calling extraction setup command 'setExtractRCMode'. Therefore, parasitic data in the tool generated as per previous mode is deleted. Call of extractRC/spefIn will generate/bring parasitic data in the tool as per current mode.
extractRC
Extraction called for design 'shabziger_chip' of instances=880593 and nets=283751 using extraction engine 'postRoute' at effort level 'low' .
Detail RC Extraction called for design shabziger_chip.
RC Extraction called in multi-corner(2) mode.
Process corner(s) are loaded.
Corner: rc_worst
Corner: rc_best
extractDetailRC Option : -outfile ../tmp/shabziger_chip_wukc1u_9079.rcdb.d -maxResLength 200 -extended
RC Mode: Detail [Extended CapTable, RC Table Resistances]
RC Corner Indexes 0 1
Capacitance Scaling Factor : 1.00000 1.00000
Coupling Cap. Scaling Factor : 1.00000 1.00000
Resistance Scaling Factor : 1.00000 1.00000
Clock Cap. Scaling Factor : 1.00000 1.00000
Clock Res. Scaling Factor : 1.00000 1.00000
Shrink Factor : 1.00000
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Checking LVS Completed (CPU Time= 0:00:01.2 MEM= 5198.5M)
Closing parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d'. 100449 times net's RC data read were performed.
Creating parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' in memory efficient access mode for storing RC.
Extracted 10% (CPU Time= 0:00:07.6 MEM= 5417.2M)
Extracted 20.0001% (CPU Time= 0:00:14.2 MEM= 5417.2M)
Extracted 30.0001% (CPU Time= 0:00:18.1 MEM= 5417.2M)
Extracted 40% (CPU Time= 0:00:24.3 MEM= 5417.2M)
Extracted 50.0001% (CPU Time= 0:00:31.4 MEM= 5417.2M)
Extracted 60.0001% (CPU Time= 0:00:36.1 MEM= 5417.2M)
Extracted 70% (CPU Time= 0:00:44.7 MEM= 5417.2M)
Extracted 80.0001% (CPU Time= 0:00:52.4 MEM= 5417.2M)
Extracted 90.0001% (CPU Time= 0:00:57.4 MEM= 5417.2M)
Extracted 100% (CPU Time= 0:01:09 MEM= 5417.2M)
Nr. Extracted Resistors : 5589300
Nr. Extracted Ground Cap. : 5868140
Nr. Extracted Coupling Cap. : 0
Opening parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' for reading.
Detail RC Extraction DONE (CPU Time: 0:01:11 Real Time: 0:01:15 MEM: 5198.473M)
setAnalysisMode -checkType setup
set_global timing_recompute_sdf_in_setuphold_mode true
write_sdf -precision 4 -min_period_edges posedge -remashold \
-min_view hold_fast_view -typ_view test_slow_view -max_view test_slow_view \
out/${NAME}.sdf.gz
Using new Cte TW Api base...#################################################################################
# Design Stage: PostRoute
# Design Mode: 65nm
# Analysis Mode: MMMC non-OCV
# Extraction Mode: detail/spef
# Delay Calculation Options: engine=signalStorm signOff=true SIAware=false(opt)
# Switching Delay Calculation Engine to signalStorm
#################################################################################
Start translating cell libraries into ECSM model (MEM=4866.0M)
End translating ECSM and Loading done (CPU=0:00:00.1, MEM=4866.0M)
Multi-cpu acceleration using 8 CPU(s).
Topological Sorting (CPU = 0:00:01.7, MEM = 0.1M, InitMEM = 0.1M)
Start delay calculation using Signal Storm (mem=0.051M)...
delayCal using detail RC...
Opening parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' for reading.
RC Database In Completed (CPU Time= 0:00:01.8 MEM= 0.1M)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Delay calculation completed. (cpu=0:00:45.1 real=0:00:42.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.4, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:41.4 real=0:00:38.0 mem=0.000M 0)
Closing parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d'. 651124 times net's RC data read were performed.
Topological Sorting (CPU = 0:00:02.7, MEM = 0.1M, InitMEM = 0.1M)
Start delay calculation using Signal Storm (mem=0.051M)...
delayCal using detail RC...
Opening parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' for reading.
RC Database In Completed (CPU Time= 0:00:01.9 MEM= 0.1M)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Delay calculation completed. (cpu=0:01:19 real=0:00:48.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.6, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:01:14 real=0:00:42.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:26.0 real=0:00:24.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:26.0 real=0:00:23.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:26.5 real=0:00:24.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:26.3 real=0:00:24.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:26.8 real=0:00:24.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:26.7 real=0:00:24.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:27.0 real=0:00:24.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:27.0 real=0:00:24.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:27.1 real=0:00:24.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:26.8 real=0:00:24.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:27.6 real=0:00:25.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:27.3 real=0:00:25.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:27.6 real=0:00:25.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:27.4 real=0:00:25.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:29.2 real=0:00:27.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:29.0 real=0:00:26.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:28.2 real=0:00:25.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:28.0 real=0:00:26.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:29.2 real=0:00:27.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:28.9 real=0:00:26.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:28.3 real=0:00:26.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:28.3 real=0:00:26.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:30.2 real=0:00:27.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:29.9 real=0:00:27.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:28.6 real=0:00:26.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:28.4 real=0:00:26.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:28.7 real=0:00:26.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:28.5 real=0:00:25.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:28.7 real=0:00:26.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:28.5 real=0:00:26.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:37.4 real=0:00:35.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:37.1 real=0:00:34.0 mem=0.000M 0)
Closing parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d'. 9139128 times net's RC data read were performed.
Topological Sorting (CPU = 0:00:01.3, MEM = 4866.0M, InitMEM = 4866.0M)
*** CDM Built up (cpu=0:24:00 real=0:20:42 mem= 5499.1M) ***
**WARN: (SDF-802): The sum of the Setup and Hold sides of the SETUPHOLD check on pin top/i_ethz_groestl/HxDP_reg_431_/SE is negative - which is illegal in SDF V3.1. The negative side of the SETUPHOLD will be postively adjusted so that the resulting sum is zero. This will result in a more conservative analysis of the adjusted check. Negative SETUPHOLD sums maybe an indication of a characterization problem in your timing libraries. You can set the timing global timing_write_sdf_allow_negative_setuphold_sum to 'true' to loosen this restriction.
**WARN: (SDF-802): The sum of the Setup and Hold sides of the SETUPHOLD check on pin top/i_ethz_groestl/HxDP_reg_280_/SE is negative - which is illegal in SDF V3.1. The negative side of the SETUPHOLD will be postively adjusted so that the resulting sum is zero. This will result in a more conservative analysis of the adjusted check. Negative SETUPHOLD sums maybe an indication of a characterization problem in your timing libraries. You can set the timing global timing_write_sdf_allow_negative_setuphold_sum to 'true' to loosen this restriction.
**WARN: (SDF-802): The sum of the Setup and Hold sides of the SETUPHOLD check on pin top/i_ethz_groestl/HxDP_reg_504_/SE is negative - which is illegal in SDF V3.1. The negative side of the SETUPHOLD will be postively adjusted so that the resulting sum is zero. This will result in a more conservative analysis of the adjusted check. Negative SETUPHOLD sums maybe an indication of a characterization problem in your timing libraries. You can set the timing global timing_write_sdf_allow_negative_setuphold_sum to 'true' to loosen this restriction.
**WARN: (SDF-802): The sum of the Setup and Hold sides of the SETUPHOLD check on pin top/i_ethz_groestl/HxDP_reg_496_/SE is negative - which is illegal in SDF V3.1. The negative side of the SETUPHOLD will be postively adjusted so that the resulting sum is zero. This will result in a more conservative analysis of the adjusted check. Negative SETUPHOLD sums maybe an indication of a characterization problem in your timing libraries. You can set the timing global timing_write_sdf_allow_negative_setuphold_sum to 'true' to loosen this restriction.
**WARN: (SDF-802): The sum of the Setup and Hold sides of the SETUPHOLD check on pin top/i_ethz_groestl/CntxDP_reg_6_/SE is negative - which is illegal in SDF V3.1. The negative side of the SETUPHOLD will be postively adjusted so that the resulting sum is zero. This will result in a more conservative analysis of the adjusted check. Negative SETUPHOLD sums maybe an indication of a characterization problem in your timing libraries. You can set the timing global timing_write_sdf_allow_negative_setuphold_sum to 'true' to loosen this restriction.
**WARN: (SDF-802): The sum of the Setup and Hold sides of the SETUPHOLD check on pin top/i_ethz_groestl/HxDP_reg_509_/SE is negative - which is illegal in SDF V3.1. The negative side of the SETUPHOLD will be postively adjusted so that the resulting sum is zero. This will result in a more conservative analysis of the adjusted check. Negative SETUPHOLD sums maybe an indication of a characterization problem in your timing libraries. You can set the timing global timing_write_sdf_allow_negative_setuphold_sum to 'true' to loosen this restriction.
**WARN: (SDF-802): The sum of the Setup and Hold sides of the SETUPHOLD check on pin top/i_ethz_jh/HxDP_reg_51__2_/SE is negative - which is illegal in SDF V3.1. The negative side of the SETUPHOLD will be postively adjusted so that the resulting sum is zero. This will result in a more conservative analysis of the adjusted check. Negative SETUPHOLD sums maybe an indication of a characterization problem in your timing libraries. You can set the timing global timing_write_sdf_allow_negative_setuphold_sum to 'true' to loosen this restriction.
**WARN: (SDF-802): The sum of the Setup and Hold sides of the SETUPHOLD check on pin top/i_ethz_jh/HxDP_reg_71__2_/SE is negative - which is illegal in SDF V3.1. The negative side of the SETUPHOLD will be postively adjusted so that the resulting sum is zero. This will result in a more conservative analysis of the adjusted check. Negative SETUPHOLD sums maybe an indication of a characterization problem in your timing libraries. You can set the timing global timing_write_sdf_allow_negative_setuphold_sum to 'true' to loosen this restriction.
**WARN: (SDF-802): The sum of the Setup and Hold sides of the SETUPHOLD check on pin top/i_ethz_jh/HxDP_reg_26__2_/SE is negative - which is illegal in SDF V3.1. The negative side of the SETUPHOLD will be postively adjusted so that the resulting sum is zero. This will result in a more conservative analysis of the adjusted check. Negative SETUPHOLD sums maybe an indication of a characterization problem in your timing libraries. You can set the timing global timing_write_sdf_allow_negative_setuphold_sum to 'true' to loosen this restriction.
**WARN: (SDF-802): The sum of the Setup and Hold sides of the SETUPHOLD check on pin top/i_ethz_jh/HxDP_reg_19__2_/SE is negative - which is illegal in SDF V3.1. The negative side of the SETUPHOLD will be postively adjusted so that the resulting sum is zero. This will result in a more conservative analysis of the adjusted check. Negative SETUPHOLD sums maybe an indication of a characterization problem in your timing libraries. You can set the timing global timing_write_sdf_allow_negative_setuphold_sum to 'true' to loosen this restriction.
**WARN: (SDF-802): The sum of the Setup and Hold sides of the SETUPHOLD check on pin top/i_ethz_jh/HxDP_reg_80__3_/SE is negative - which is illegal in SDF V3.1. The negative side of the SETUPHOLD will be postively adjusted so that the resulting sum is zero. This will result in a more conservative analysis of the adjusted check. Negative SETUPHOLD sums maybe an indication of a characterization problem in your timing libraries. You can set the timing global timing_write_sdf_allow_negative_setuphold_sum to 'true' to loosen this restriction.
**WARN: (SDF-802): The sum of the Setup and Hold sides of the SETUPHOLD check on pin top/i_ethz_jh/HxDP_reg_112__2_/SE is negative - which is illegal in SDF V3.1. The negative side of the SETUPHOLD will be postively adjusted so that the resulting sum is zero. This will result in a more conservative analysis of the adjusted check. Negative SETUPHOLD sums maybe an indication of a characterization problem in your timing libraries. You can set the timing global timing_write_sdf_allow_negative_setuphold_sum to 'true' to loosen this restriction.
**WARN: (SDF-802): The sum of the Setup and Hold sides of the SETUPHOLD check on pin top/i_ethz_jh/HxDP_reg_52__3_/SE is negative - which is illegal in SDF V3.1. The negative side of the SETUPHOLD will be postively adjusted so that the resulting sum is zero. This will result in a more conservative analysis of the adjusted check. Negative SETUPHOLD sums maybe an indication of a characterization problem in your timing libraries. You can set the timing global timing_write_sdf_allow_negative_setuphold_sum to 'true' to loosen this restriction.
**WARN: (SDF-802): The sum of the Setup and Hold sides of the SETUPHOLD check on pin top/i_ethz_jh/HxDP_reg_10__1_/SE is negative - which is illegal in SDF V3.1. The negative side of the SETUPHOLD will be postively adjusted so that the resulting sum is zero. This will result in a more conservative analysis of the adjusted check. Negative SETUPHOLD sums maybe an indication of a characterization problem in your timing libraries. You can set the timing global timing_write_sdf_allow_negative_setuphold_sum to 'true' to loosen this restriction.
**WARN: (SDF-802): The sum of the Setup and Hold sides of the SETUPHOLD check on pin top/i_ethz_jh/HxDP_reg_218__3_/SE is negative - which is illegal in SDF V3.1. The negative side of the SETUPHOLD will be postively adjusted so that the resulting sum is zero. This will result in a more conservative analysis of the adjusted check. Negative SETUPHOLD sums maybe an indication of a characterization problem in your timing libraries. You can set the timing global timing_write_sdf_allow_negative_setuphold_sum to 'true' to loosen this restriction.
**WARN: (SDF-802): The sum of the Setup and Hold sides of the SETUPHOLD check on pin top/i_ethz_jh/HxDP_reg_218__2_/SE is negative - which is illegal in SDF V3.1. The negative side of the SETUPHOLD will be postively adjusted so that the resulting sum is zero. This will result in a more conservative analysis of the adjusted check. Negative SETUPHOLD sums maybe an indication of a characterization problem in your timing libraries. You can set the timing global timing_write_sdf_allow_negative_setuphold_sum to 'true' to loosen this restriction.
**WARN: (SDF-802): The sum of the Setup and Hold sides of the SETUPHOLD check on pin top/i_ethz_jh/HxDP_reg_56__3_/SE is negative - which is illegal in SDF V3.1. The negative side of the SETUPHOLD will be postively adjusted so that the resulting sum is zero. This will result in a more conservative analysis of the adjusted check. Negative SETUPHOLD sums maybe an indication of a characterization problem in your timing libraries. You can set the timing global timing_write_sdf_allow_negative_setuphold_sum to 'true' to loosen this restriction.
**WARN: (SDF-802): The sum of the Setup and Hold sides of the SETUPHOLD check on pin top/i_ethz_jh/HxDP_reg_253__1_/SE is negative - which is illegal in SDF V3.1. The negative side of the SETUPHOLD will be postively adjusted so that the resulting sum is zero. This will result in a more conservative analysis of the adjusted check. Negative SETUPHOLD sums maybe an indication of a characterization problem in your timing libraries. You can set the timing global timing_write_sdf_allow_negative_setuphold_sum to 'true' to loosen this restriction.
**WARN: (SDF-802): The sum of the Setup and Hold sides of the SETUPHOLD check on pin top/i_ethz_jh/HxDP_reg_149__1_/SE is negative - which is illegal in SDF V3.1. The negative side of the SETUPHOLD will be postively adjusted so that the resulting sum is zero. This will result in a more conservative analysis of the adjusted check. Negative SETUPHOLD sums maybe an indication of a characterization problem in your timing libraries. You can set the timing global timing_write_sdf_allow_negative_setuphold_sum to 'true' to loosen this restriction.
**WARN: (SDF-802): The sum of the Setup and Hold sides of the SETUPHOLD check on pin top/i_ethz_jh/HxDP_reg_223__1_/SE is negative - which is illegal in SDF V3.1. The negative side of the SETUPHOLD will be postively adjusted so that the resulting sum is zero. This will result in a more conservative analysis of the adjusted check. Negative SETUPHOLD sums maybe an indication of a characterization problem in your timing libraries. You can set the timing global timing_write_sdf_allow_negative_setuphold_sum to 'true' to loosen this restriction.
Message has exceeded the message display limit of '20'. setMessageLimit/set_message_limit sets the limit. unsetMessageLimit/unset_message_limit can be used to reset this.
saveNetlist out/shabziger.v -excludeLeafCell -includePhysicalInst
Writing Netlist "out/shabziger.v" ...
Warning (Quiet mode): There are 200 pg terms not connected to global special net.
**WARN: (ENCVL-505): PG terms are not connected to global pg nets.
**WARN: (ENCVL-516): No Power/Ground connections in top module (shabziger_chip).
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_0 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_1 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_2 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_3 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_4 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_5 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_6 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_7 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_8 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_9 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_10 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_11 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_12 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_13 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_14 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_15 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_16 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_17 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_18 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_19 is not connected to a global P/G net.
**WARN: (EMS-62): Message has exceeded the default message display limit of 20.
To avoid this warning, increase the display limit per unique message
by using the set_message_limit command.
The message limit can be removed by using the unset_message_limit command.
Note that setting a very large number using the set_message_limit command
or removing the message limit using the unset_message_limit command can
significantly increase the log file size.
To suppress a message, use suppress_message command.
Pwr name (VDD).
Pwr name (VDDIO).
Gnd name (VSS).
Gnd name (VSSIO).
2 Pwr names and 2 Gnd names.
saveNetlist out/shabziger_lvs.v -excludeLeafCell -includePhysicalInst -phys
Writing Netlist "out/shabziger_lvs.v" ...
Warning (Quiet mode): There are 200 pg terms not connected to global special net.
**WARN: (ENCVL-505): PG terms are not connected to global pg nets.
**WARN: (ENCVL-516): No Power/Ground connections in top module (shabziger_chip).
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_0 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_1 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_2 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_3 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_4 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_5 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_6 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_7 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_8 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_9 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_10 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_11 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_12 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_13 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_14 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_15 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_16 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_17 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_18 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_19 is not connected to a global P/G net.
Pwr name (VDD).
Pwr name (VDDIO).
Gnd name (VSS).
Gnd name (VSSIO).
2 Pwr names and 2 Gnd names.
Creating all pg connections for top cell (shabziger_chip).
setStreamOutMode -SEvianames ON -specifyViaName %t_VIA
streamOut out/shabziger.gds.gz -mapFile tech/streamOut_noObs.map -outputMacros -merge { /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbr/a02/gds/uk65lscllmvbbr.gds /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbl/a02/gds/uk65lscllmvbbl.gds /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbh/a02/gds/uk65lscllmvbbh.gds /usr/pack/umc-65-kgf/umc/ll/u065gioll25mvir/a03/gds/u065gioll25mvir_8m1t0f1u.gds /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_16384X32X1CM16.gds /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_2048X32X1CM4.gds /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SYKA65_2048X32X1CM8.gds }
Finding the highest version number among the merge files
Merge file: /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbr/a02/gds/uk65lscllmvbbr.gds has version number: 5
Merge file: /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbl/a02/gds/uk65lscllmvbbl.gds has version number: 5
Merge file: /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbh/a02/gds/uk65lscllmvbbh.gds has version number: 5
Merge file: /usr/pack/umc-65-kgf/umc/ll/u065gioll25mvir/a03/gds/u065gioll25mvir_8m1t0f1u.gds has version number: 5
Merge file: /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_16384X32X1CM16.gds has version number: 5
Merge file: /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_2048X32X1CM4.gds has version number: 5
Merge file: /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SYKA65_2048X32X1CM8.gds has version number: 5
Parse map file...
Writing GDSII file ...
****** db unit per micron = 1000 ******
****** output gds2 file unit per micron = 1000 ******
****** unit scaling factor = 1 ******
Output for instance
Output for bump
Output for physical terminals
Output for logical terminals
Output for regular nets
Output for special nets and metal fills
Output for via structure generation
Statistics for GDS generated (version 5)
----------------------------------------
Stream Out Layer Mapping Information:
GDS Layer Number GDS Layer Name
----------------------------------------
121 COMP
46 ME1
47 VI1
48 ME2
49 VI2
50 ME3
51 VI3
52 ME4
53 VI4
54 ME5
55 VI5
56 ME6
57 VI6
58 ME7
59 VI7
60 ME8
101 ME1
102 ME2
103 ME3
104 ME4
105 ME5
106 ME6
107 ME7
108 ME8
Stream Out Information Processed for GDS version 5:
Units: 1000 DBU
Object Count
----------------------------------------
Instances 880593
Ports/Pins 0
Nets 2759547
metal layer ME1 167961
metal layer ME2 1099022
metal layer ME3 831013
metal layer ME4 307229
metal layer ME5 204581
metal layer ME6 102717
metal layer ME7 42241
metal layer ME8 4783
Via Instances 2805631
Special Nets 4751
metal layer ME1 4146
metal layer ME2 68
metal layer ME3 57
metal layer ME4 24
metal layer ME5 24
metal layer ME6 24
metal layer ME7 319
metal layer ME8 89
Via Instances 189513
Metal Fills 0
Via Instances 0
Metal FillOPCs 0
Via Instances 0
Text 42
metal layer ME1 2
metal layer ME4 40
Blockages 0
Custom Text 0
Custom Box 0
Merging with GDS libraries
Scanning GDS file /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbr/a02/gds/uk65lscllmvbbr.gds to register cell name ......
Scanning GDS file /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbl/a02/gds/uk65lscllmvbbl.gds to register cell name ......
Scanning GDS file /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbh/a02/gds/uk65lscllmvbbh.gds to register cell name ......
Scanning GDS file /usr/pack/umc-65-kgf/umc/ll/u065gioll25mvir/a03/gds/u065gioll25mvir_8m1t0f1u.gds to register cell name ......
Scanning GDS file /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_16384X32X1CM16.gds to register cell name ......
Scanning GDS file /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_2048X32X1CM4.gds to register cell name ......
Scanning GDS file /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SYKA65_2048X32X1CM8.gds to register cell name ......
Merging GDS file /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbr/a02/gds/uk65lscllmvbbr.gds ......
****** Merge file: /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbr/a02/gds/uk65lscllmvbbr.gds has version number: 5.
****** Merge file: /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbr/a02/gds/uk65lscllmvbbr.gds has units: 1000 per micron.
****** unit scaling factor = 1 ******
Merging GDS file /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbl/a02/gds/uk65lscllmvbbl.gds ......
****** Merge file: /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbl/a02/gds/uk65lscllmvbbl.gds has version number: 5.
****** Merge file: /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbl/a02/gds/uk65lscllmvbbl.gds has units: 1000 per micron.
****** unit scaling factor = 1 ******
Merging GDS file /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbh/a02/gds/uk65lscllmvbbh.gds ......
****** Merge file: /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbh/a02/gds/uk65lscllmvbbh.gds has version number: 5.
****** Merge file: /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbh/a02/gds/uk65lscllmvbbh.gds has units: 1000 per micron.
****** unit scaling factor = 1 ******
Merging GDS file /usr/pack/umc-65-kgf/umc/ll/u065gioll25mvir/a03/gds/u065gioll25mvir_8m1t0f1u.gds ......
****** Merge file: /usr/pack/umc-65-kgf/umc/ll/u065gioll25mvir/a03/gds/u065gioll25mvir_8m1t0f1u.gds has version number: 5.
****** Merge file: /usr/pack/umc-65-kgf/umc/ll/u065gioll25mvir/a03/gds/u065gioll25mvir_8m1t0f1u.gds has units: 1000 per micron.
****** unit scaling factor = 1 ******
Merging GDS file /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_16384X32X1CM16.gds ......
****** Merge file: /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_16384X32X1CM16.gds has version number: 5.
****** Merge file: /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_16384X32X1CM16.gds has units: 1000 per micron.
****** unit scaling factor = 1 ******
Merging GDS file /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_2048X32X1CM4.gds ......
****** Merge file: /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_2048X32X1CM4.gds has version number: 5.
****** Merge file: /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_2048X32X1CM4.gds has units: 1000 per micron.
****** unit scaling factor = 1 ******
WARNING: Ignoring duplicate structure SHKA_DIDO_GAP.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PRED38_GAP.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XDECGAP_BOT_A3.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_BLMUX_AR4.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10028064.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12083272.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12085362.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12105249.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12105528.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12170460.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12285811.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12359965.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14326535.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14330618.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14337440.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14343616.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23646729.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_6232157.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_6317025.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_6395777.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8298672.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CORNER_BOT.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CORNER_TOP.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CORNER_TOP_R.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DELAY_0.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DELAY_1.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DUMBL2.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DUMBL_GAP.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DUMWL4.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DUMX4_BOT.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DUMX4_TOP.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DUMY2.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DUMY2_R.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DUMY_GAP.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DUM_CORNER_BOT.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DUM_CORNER_TOP.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DVSDEBUG_M1.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_GAR_2001977.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_GAR_3531995.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_MTCH_V2.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_419780_SHKA_BTI_0726.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PRED38.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PRED38_GAP_ANTLAYERS.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PREDLS.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PRED_V2.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_RAM4X2.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_RAM_GAP4.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_V1.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_V2.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_V3.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_WEB_M3.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XDEC2_A3.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XDECGAP_BOT.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XDEC_GAP_A3.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XDEC_V2.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_10008858.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3160920.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3170609.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3205977.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3209960.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3221359.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3228325.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3233103.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3321437.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3425269.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3426521.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3426581.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3452029.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3456148.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3463740.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3478292.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3489149.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3749629.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3835106.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3858135.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3889300.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3940578.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3997181.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4498960.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4822324.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4844500.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5226718.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5335262.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5933202.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6518403.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6548882.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_7725639.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_7873963.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_7945450.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_8056179.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_9660467.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_AY0_AR4.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_BLMUX.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_BLMUX_A.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10037589.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10038316.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10134998.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12085174.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12088082.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12088997.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12099175.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12104264.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12105697.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12106424.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12191805.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12197959.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12278541.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12285084.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12288719.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12292394.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12296247.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12296695.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12296974.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12297701.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12302925.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14323697.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14324086.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14324754.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14325914.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14326039.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14327262.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14327713.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14327989.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14328095.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14328150.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14328264.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14328437.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14328598.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14328877.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14329164.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14329387.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14329443.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14329891.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14329993.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14330103.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14331624.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14335986.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14339621.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23890040.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23970077.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24141245.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24174576.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24220647.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24236789.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24260656.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24353232.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24419738.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24496345.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24507306.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24558188.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24677599.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_27874146.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_6239042.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8302216.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8321376.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8495670.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8513101.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DBLRESET_AR8.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DELAY_0_ANTLAYERS.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DELAY_1_ANTLAYERS.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_MATCH_AR8.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_MOSCAPA.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_MOSCAPB.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_MOSCAPC.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_433080.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PRED38_ANTLAYERS.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_WEB_M3_ANTLAYERS.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XDEC_A.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XDEC_GAP_A1.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_10273994.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_11029292.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_11415054.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_11850288.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_12161762.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_16719629.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_20345153.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_2819235.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3213362.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_34797202.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_34873714.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3511167.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3731140.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3905988.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3919509.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3943108.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4012213.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4063591.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4153447.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4197877.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4397290.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4459583.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4476498.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4635864.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4770373.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4829351.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4845450.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4908273.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4922435.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5211455.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5234628.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5409831.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5532826.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5645561.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6051119.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6237011.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6547522.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6567661.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6795078.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6865252.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6905918.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_7498080.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_7536011.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_7549678.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_7689095.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_7705681.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_7922876.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_8555373.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_9307368.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_9411948.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_9515986.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_BLMUX_1.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10017254.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10017533.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10027616.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10027785.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10027895.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10028512.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10029239.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10037868.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10116510.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10117237.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10122860.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10130730.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10131457.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10133112.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10208531.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10218335.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10223111.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10223559.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10938078.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10938526.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10939253.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10939980.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10941174.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10941622.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10950978.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10951426.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10961229.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11039030.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11039478.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11040205.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11040932.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11041659.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11043840.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11046949.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11047675.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11048202.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11049656.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11049857.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11050584.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11056399.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11057126.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11057853.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11133346.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11136254.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11147199.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11152954.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11157730.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12082266.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12084447.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12085920.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12086816.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12087543.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12089724.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12090451.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12092632.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12095445.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12095540.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12096267.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12096620.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12164562.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12169006.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12171914.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12174095.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12183946.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12190968.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12191416.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12192143.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12192870.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12193597.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12193750.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12194324.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12195051.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12195578.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12196505.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12197232.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12198686.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12199413.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12200867.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12201220.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12201594.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12201947.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12202321.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12203048.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12203775.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12204502.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12205229.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12208137.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12208864.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12211772.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12212499.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12247479.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12248654.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12251562.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12277087.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12277814.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12282903.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12286443.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12291219.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12291667.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12301471.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14324145.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14326366.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14326645.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14326983.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14329156.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14332799.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23647287.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23647456.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23647566.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23647735.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23648293.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23648403.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23648462.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23648572.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23648851.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23648910.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23649189.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23649916.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23651370.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23655005.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23657186.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23657913.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23816956.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23816956_FSE0K_A.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23817034.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23863283.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23863361.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23870314.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23889962.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23909610.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23909688.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23936289.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23950351.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23956015.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23982616.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23982694.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24002342.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24028943.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24075270.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24214251.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24233977.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24306667.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24677521.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24697247.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24955483.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_5194519.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_6233053.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_6233660.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_6234108.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_6238594.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_6444266.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_7255157.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_7263802.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8301489.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8301768.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8311572.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8507794.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8512374.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8882870.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8893122.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8978392.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8978840.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_9073867.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_9079091.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_GAR_2089412.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_413100_F.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_413100_SHKA_BTI_0726.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_413640_SHKA_BTI_0726.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_419780_F.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_432540_F.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_463937_F.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_465759_F.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_465999_F.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XDIODE.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_10086253.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_1588363.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_1588781.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_1614729.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_2616968.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_2690537.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_2813413.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3103705.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3193058.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3209137.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3221112.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3231597.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3259615.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3321377.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3410806.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3491211.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3564189.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3599675.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3617789.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3628757.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3694584.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3749060.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3751739.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3798684.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3821577.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3829603.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3846795.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3852026.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3858131.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3924940.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4018282.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4035586.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4129886.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4145097.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4311763.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4339723.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4421332.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4423521.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4428877.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4437005.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4444940.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4466863.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4525653.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4553147.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4553698.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4593509.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4634404.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4642245.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4681731.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4701908.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4709585.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4734365.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4837950.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4845075.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4855525.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4912583.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4952643.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5005409.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5023948.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5052505.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5064787.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5075321.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5095161.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5125877.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5238456.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5352850.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5471841.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5484265.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5499185.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5504434.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5569190.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5607136.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5757317.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5799040.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5934895.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5955236.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6153764.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6199865.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6272006.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6276061.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6726858.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6802803.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6870134.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6956844.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_8555162.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_8647761.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10017981.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10027337.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12082545.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12082993.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12083720.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12085641.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12086089.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12088270.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12095893.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12169733.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12195778.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14325081.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23909610_FSE0K_A.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_25026146.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_6243464.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8312020.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8312747.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_358840.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_413100_FSE0K_A.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_413640_FSE0K_A.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_420640.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_433400.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_438901.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_464477.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_464717.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_467581_SHKA_BTI_0726.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_467821_SHKA_BTI_0726.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_468121.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_468361.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3431959.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3597012.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3722489.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3858075.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4009666.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4258831.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4307140.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4405335.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5574242.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_413100_1_FSE0K_A.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_413640_1_FSE0K_A.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_419780_FSE0K_A.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_432540_SHKA_BTI_0726.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_463937_SHKA_BTI_0726.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_464177.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_465759_SHKA_BTI_0726.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_465999_SHKA_BTI_0726.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_466299_SHKA_BTI_0726.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_466539.
A structure with the same name already exists in one of the merging GDSII files.
There are 529 structures ignored in file /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_2048X32X1CM4.gds
Merging GDS file /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SYKA65_2048X32X1CM8.gds ......
****** Merge file: /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SYKA65_2048X32X1CM8.gds has version number: 5.
****** Merge file: /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SYKA65_2048X32X1CM8.gds has units: 1000 per micron.
****** unit scaling factor = 1 ******
Output for cells
######Streamout is finished!
deleteFiller -cell {FIL16S FIL1S FIL2S FIL32S FIL4S FIL64S FIL8S FILE16S FILE16S FILE32S FILE32S FILE3S FILE3S FILE4S FILE4S FILE64S FILE64S FILE6S FILE6S FILE8S FILE8S FILEP16S FILEP16S FILEP32S FILEP32S FILEP64S FILEP64S FILEP8S FILEP8S FIL16W FIL1W FIL2W FIL32W FIL4W FIL64W FIL8W FILE16W FILE16W FILE32W FILE32W FILE3W FILE3W FILE4W FILE4W FILE64W FILE64W FILE6W FILE6W FILE8W FILE8W FILEP16W FILEP16W FILEP32W FILEP32W FILEP64W FILEP64W FILEP8W FILEP8W FIL16R FIL1R FIL2R FIL32R FIL4R FIL64R FIL8R FILE16R FILE16R FILE32R FILE32R FILE3R FILE3R FILE4R FILE4R FILE64R FILE64R FILE6R FILE6R FILE8R FILE8R FILEP16R FILEP16R FILEP32R FILEP32R FILEP64R FILEP64R FILEP8R FILEP8R}
Deleted 0 physical inst (cell FIL16S / prefix -).
Deleted 7552 physical insts (cell FIL1S / prefix -).
Deleted 4213 physical insts (cell FIL2S / prefix -).
Deleted 0 physical inst (cell FIL32S / prefix -).
Deleted 0 physical inst (cell FIL4S / prefix -).
Deleted 0 physical inst (cell FIL64S / prefix -).
Deleted 0 physical inst (cell FIL8S / prefix -).
Deleted 0 physical inst (cell FILE16S / prefix -).
Deleted 0 physical inst (cell FILE16S / prefix -).
Deleted 0 physical inst (cell FILE32S / prefix -).
Deleted 0 physical inst (cell FILE32S / prefix -).
Deleted 4038 physical insts (cell FILE3S / prefix -).
Deleted 0 physical inst (cell FILE3S / prefix -).
Deleted 3075 physical insts (cell FILE4S / prefix -).
Deleted 0 physical inst (cell FILE4S / prefix -).
Deleted 0 physical inst (cell FILE64S / prefix -).
Deleted 0 physical inst (cell FILE64S / prefix -).
Deleted 2356 physical insts (cell FILE6S / prefix -).
Deleted 0 physical inst (cell FILE6S / prefix -).
Deleted 0 physical inst (cell FILE8S / prefix -).
Deleted 0 physical inst (cell FILE8S / prefix -).
Deleted 4785 physical insts (cell FILEP16S / prefix -).
Deleted 0 physical inst (cell FILEP16S / prefix -).
Deleted 1750 physical insts (cell FILEP32S / prefix -).
Deleted 0 physical inst (cell FILEP32S / prefix -).
Deleted 4685 physical insts (cell FILEP64S / prefix -).
Deleted 0 physical inst (cell FILEP64S / prefix -).
Deleted 5773 physical insts (cell FILEP8S / prefix -).
Deleted 0 physical inst (cell FILEP8S / prefix -).
Deleted 0 physical inst (cell FIL16W / prefix -).
Deleted 63633 physical insts (cell FIL1W / prefix -).
Deleted 199089 physical insts (cell FIL2W / prefix -).
Deleted 0 physical inst (cell FIL32W / prefix -).
Deleted 0 physical inst (cell FIL4W / prefix -).
Deleted 0 physical inst (cell FIL64W / prefix -).
Deleted 0 physical inst (cell FIL8W / prefix -).
Deleted 0 physical inst (cell FILE16W / prefix -).
Deleted 0 physical inst (cell FILE16W / prefix -).
Deleted 0 physical inst (cell FILE32W / prefix -).
Deleted 0 physical inst (cell FILE32W / prefix -).
Deleted 16866 physical insts (cell FILE3W / prefix -).
Deleted 0 physical inst (cell FILE3W / prefix -).
Deleted 15674 physical insts (cell FILE4W / prefix -).
Deleted 0 physical inst (cell FILE4W / prefix -).
Deleted 0 physical inst (cell FILE64W / prefix -).
Deleted 0 physical inst (cell FILE64W / prefix -).
Deleted 10879 physical insts (cell FILE6W / prefix -).
Deleted 0 physical inst (cell FILE6W / prefix -).
Deleted 0 physical inst (cell FILE8W / prefix -).
Deleted 0 physical inst (cell FILE8W / prefix -).
Deleted 11558 physical insts (cell FILEP16W / prefix -).
Deleted 0 physical inst (cell FILEP16W / prefix -).
Deleted 3076 physical insts (cell FILEP32W / prefix -).
Deleted 0 physical inst (cell FILEP32W / prefix -).
Deleted 633 physical insts (cell FILEP64W / prefix -).
Deleted 0 physical inst (cell FILEP64W / prefix -).
Deleted 22303 physical insts (cell FILEP8W / prefix -).
Deleted 0 physical inst (cell FILEP8W / prefix -).
Deleted 0 physical inst (cell FIL16R / prefix -).
Deleted 26142 physical insts (cell FIL1R / prefix -).
Deleted 154917 physical insts (cell FIL2R / prefix -).
Deleted 0 physical inst (cell FIL32R / prefix -).
Deleted 0 physical inst (cell FIL4R / prefix -).
Deleted 0 physical inst (cell FIL64R / prefix -).
Deleted 0 physical inst (cell FIL8R / prefix -).
Deleted 0 physical inst (cell FILE16R / prefix -).
Deleted 0 physical inst (cell FILE16R / prefix -).
Deleted 0 physical inst (cell FILE32R / prefix -).
Deleted 0 physical inst (cell FILE32R / prefix -).
Deleted 946 physical insts (cell FILE3R / prefix -).
Deleted 0 physical inst (cell FILE3R / prefix -).
Deleted 1393 physical insts (cell FILE4R / prefix -).
Deleted 0 physical inst (cell FILE4R / prefix -).
Deleted 0 physical inst (cell FILE64R / prefix -).
Deleted 0 physical inst (cell FILE64R / prefix -).
Deleted 1013 physical insts (cell FILE6R / prefix -).
Deleted 0 physical inst (cell FILE6R / prefix -).
Deleted 0 physical inst (cell FILE8R / prefix -).
Deleted 0 physical inst (cell FILE8R / prefix -).
Deleted 1010 physical insts (cell FILEP16R / prefix -).
Deleted 0 physical inst (cell FILEP16R / prefix -).
Deleted 329 physical insts (cell FILEP32R / prefix -).
Deleted 0 physical inst (cell FILEP32R / prefix -).
Deleted 200 physical insts (cell FILEP64R / prefix -).
Deleted 0 physical inst (cell FILEP64R / prefix -).
Deleted 1869 physical insts (cell FILEP8R / prefix -).
Deleted 0 physical inst (cell FILEP8R / prefix -).
Total physical insts deleted = 569757.
setOptMode -setupTargetSlack 0
*info: Setting setup target slack to 0.000
*info: Hold target slack is 0.000
optDesign -postroute -outDir timingReports_final -prefix shabziger.postrouteopt2
Disable merging buffers from different footprints for postRoute code for non-MSV designs
**WARN: (ENCOPT-6055): The following cells have a dont_touch property but without being dont_use.
Such configuration can impact the timing closure because they can be inserted in the netlist but never transformed again.
It is recommended that you apply a dont_use attribute on them.
Cell SYKA65_2048X32X1CM8 is dont_touch but not dont_use
Cell SHKA65_2048X32X1CM4 is dont_touch but not dont_use
Cell SHKA65_16384X32X1CM16 is dont_touch but not dont_use
...
Reporting only the 20 first cells found...
COE opt is not supported in non AAE mode. Reverting to non COE postroute flow
**optDesign ... cpu = 0:00:00, real = 0:00:00, mem = 4864.0M **
#Created 3310 library cell signatures
#Created 283751 NETS and 0 SPECIALNETS signatures
#Created 310837 instance signatures
Begin checking placement ... (start mem=4864.0M, init mem=4881.1M)
*info: Placed = 273345
*info: Unplaced = 0
Placement Density:60.30%(1137368/1886211)
Finished checkPlace (cpu: total=0:00:02.9, vio checks=0:00:00.3; mem=4864.0M)
Setting latch borrow mode to budget during optimization.
setExtractRCMode -coupled false
**WARN: (ENCEXT-3493): Extraction mode changed by calling extraction setup command 'setExtractRCMode'. Therefore, parasitic data in the tool generated as per previous mode is deleted. Call of extractRC/spefIn will generate/bring parasitic data in the tool as per current mode.
*** optDesign -postRoute ***
DRC Margin: user margin 0.0; extra margin 0
Setup Target Slack: user slack 0.0
Hold Target Slack: user slack 0.0
*info: Setting setup target slack to 0.000
*info: Hold target slack is 0.000
**INFO : Adding temp dont-use cells (LVT only flow version : 4)
Creating information for LVT Only Flow
Num of Buffers : 123
Num of Inverters : 105
Num of VTs : 3
Executing LVT Only Same Size Flow (setting 4)
*Info* Num dontuse cells 311
*Info* Num dontuse cells 2259
Extraction called for design 'shabziger_chip' of instances=310836 and nets=283751 using extraction engine 'postRoute' at effort level 'low' .
Detail RC Extraction called for design shabziger_chip.
RC Extraction called in multi-corner(2) mode.
Process corner(s) are loaded.
Corner: rc_worst
Corner: rc_best
extractDetailRC Option : -outfile ../tmp/shabziger_chip_wukc1u_9079.rcdb.d -maxResLength 200 -extended
RC Mode: Detail [Extended CapTable, RC Table Resistances]
RC Corner Indexes 0 1
Capacitance Scaling Factor : 1.00000 1.00000
Coupling Cap. Scaling Factor : 1.00000 1.00000
Resistance Scaling Factor : 1.00000 1.00000
Clock Cap. Scaling Factor : 1.00000 1.00000
Clock Res. Scaling Factor : 1.00000 1.00000
Shrink Factor : 1.00000
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Checking LVS Completed (CPU Time= 0:00:01.8 MEM= 4795.9M)
Creating parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' in memory efficient access mode for storing RC.
Extracted 10% (CPU Time= 0:00:08.2 MEM= 5056.0M)
Extracted 20.0001% (CPU Time= 0:00:14.8 MEM= 5056.0M)
Extracted 30.0001% (CPU Time= 0:00:18.6 MEM= 5056.0M)
Extracted 40% (CPU Time= 0:00:24.8 MEM= 5056.0M)
Extracted 50.0001% (CPU Time= 0:00:31.9 MEM= 5056.0M)
Extracted 60.0001% (CPU Time= 0:00:36.5 MEM= 5056.0M)
Extracted 70% (CPU Time= 0:00:45.0 MEM= 5056.0M)
Extracted 80.0001% (CPU Time= 0:00:52.8 MEM= 5056.0M)
Extracted 90.0001% (CPU Time= 0:00:57.7 MEM= 5056.0M)
Extracted 100% (CPU Time= 0:01:09 MEM= 5056.0M)
Nr. Extracted Resistors : 5589300
Nr. Extracted Ground Cap. : 5868140
Nr. Extracted Coupling Cap. : 0
Opening parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' for reading.
Detail RC Extraction DONE (CPU Time: 0:01:11 Real Time: 0:01:14 MEM: 4795.867M)
Using new Cte TW Api base...#################################################################################
# Design Stage: PostRoute
# Design Mode: 65nm
# Analysis Mode: MMMC non-OCV
# Extraction Mode: detail/spef
# Delay Calculation Options: engine=signalStorm signOff=true SIAware=false(opt)
# Switching Delay Calculation Engine to signalStorm
#################################################################################
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.4, MEM = 4868.4M, InitMEM = 4867.9M)
Start delay calculation using Signal Storm (mem=4868.391M)...
delayCal using detail RC...
Opening parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' for reading.
RC Database In Completed (CPU Time= 0:00:01.2 MEM= 4916.6M)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Delay calculation completed. (cpu=0:00:48.7 real=0:00:48.0 mem=5383.828M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5383.8M, InitMEM = 5383.8M)
Start delay calculation using Signal Storm (mem=5383.828M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:24.0 real=0:00:24.0 mem=5383.828M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5383.8M, InitMEM = 5383.8M)
Start delay calculation using Signal Storm (mem=5383.828M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:24.2 real=0:00:25.0 mem=5383.828M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5383.8M, InitMEM = 5383.8M)
Start delay calculation using Signal Storm (mem=5383.828M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:24.4 real=0:00:24.0 mem=5383.828M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5383.8M, InitMEM = 5383.8M)
Start delay calculation using Signal Storm (mem=5383.828M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:24.6 real=0:00:25.0 mem=5383.828M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5383.8M, InitMEM = 5383.8M)
Start delay calculation using Signal Storm (mem=5383.828M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:24.3 real=0:00:24.0 mem=5383.828M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5383.8M, InitMEM = 5383.8M)
Start delay calculation using Signal Storm (mem=5383.828M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:24.9 real=0:00:25.0 mem=5383.828M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5383.8M, InitMEM = 5383.8M)
Start delay calculation using Signal Storm (mem=5383.828M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:25.0 real=0:00:25.0 mem=5383.828M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5383.8M, InitMEM = 5383.8M)
Start delay calculation using Signal Storm (mem=5383.828M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:26.5 real=0:00:27.0 mem=5383.828M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5383.8M, InitMEM = 5383.8M)
Start delay calculation using Signal Storm (mem=5383.828M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:25.7 real=0:00:25.0 mem=5383.828M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5383.8M, InitMEM = 5383.8M)
Start delay calculation using Signal Storm (mem=5383.828M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:26.6 real=0:00:27.0 mem=5383.828M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5383.8M, InitMEM = 5383.8M)
Start delay calculation using Signal Storm (mem=5383.828M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:25.9 real=0:00:26.0 mem=5383.828M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5383.8M, InitMEM = 5383.8M)
Start delay calculation using Signal Storm (mem=5383.828M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:27.6 real=0:00:27.0 mem=5383.828M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5383.8M, InitMEM = 5383.8M)
Start delay calculation using Signal Storm (mem=5383.828M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:26.4 real=0:00:27.0 mem=5383.828M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.1, MEM = 5383.8M, InitMEM = 5383.8M)
Start delay calculation using Signal Storm (mem=5383.828M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:26.3 real=0:00:26.0 mem=5383.828M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5383.8M, InitMEM = 5383.8M)
Start delay calculation using Signal Storm (mem=5383.828M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:26.3 real=0:00:27.0 mem=5383.828M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5383.8M, InitMEM = 5383.8M)
Start delay calculation using Signal Storm (mem=5383.828M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:34.8 real=0:00:34.0 mem=5383.828M 0)
*** CDM Built up (cpu=0:08:47 real=0:08:47 mem= 5383.8M) ***
-holdSdfFile {} # string, default=""
-holdSdfScript {} # string, default="", private
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
Initial Summary
------------------------------------------------------------
+--------------------+---------+
| Setup mode | all |
+--------------------+---------+
| WNS (ns):| -0.192 |
| TNS (ns):|-144.008 |
| Violating Paths:| 2711 |
| All Paths:| 85005 |
+--------------------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 0 (0) | 0.000 | 0 (0) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 60.299%
------------------------------------------------------------
**optDesign ... cpu = 0:11:40, real = 0:11:44, mem = 5717.4M **
*** Timing NOT met, worst failing slack is -0.192
*** Check timing (0:00:00.4)
*** Timing NOT met, worst failing slack is -0.192
*** Check timing (0:00:00.1)
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
Info: 40 io nets excluded
Info: 567 clock nets excluded from IPO operation.
All-RC-Corners-Per-Net-In-Memory is turned ON...
Closing parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d'. 4614848 times net's RC data read were performed.
Opening parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' for reading.
RC Database In Completed (CPU Time= 0:00:01.4 MEM= 5452.8M)
*** Start Post Route Setup Fixing (cpu=0:00:00.0 mem=5452.8M) ***
Time Engine : CTE
SSTA Mode : off
MMMC mode : on (10 dominant view(s), 7 view(s) pruned)
Incr. DC : on
Incr POM Mode : on
On Demand POM Mode : on
CTE SubNetWork Mode : on
Up Size : on
Down Size : on
Resize FFs : on
Add Buffer : off
Del Buffer : off
Pin Swap : off
Add InvPair : off
LegalLoc GS : off
Speedup GS : off
Crit. Range : 20%
density before = 60.299%
total 280778 net, 39 ipo_ignored
total 951841 term, 78 ipo_ignored
total 289622 comb inst, 37273 fixed, 273 dont_touch, 36923 no_footp
total 21214 seq inst, 18 fixed, 3 dont_touch, 3 no_footp
total 240 footprint(s)
10 footprint(s) with 0 cell(s)
36 footprint(s) with 1 cell(s)
16 footprint(s) with 2 cell(s)
3 footprint(s) with 3 cell(s)
119 footprint(s) with 4 cell(s)
13 footprint(s) with 5 cell(s)
13 footprint(s) with 6 cell(s)
13 footprint(s) with 7 cell(s)
7 footprint(s) with 8 cell(s)
1 footprint(s) with 9 cell(s)
9 footprint(s) with 10+ cell(s)
Estimated WNS = -0.192ns, TNS = -144.012ns (cpu=0:00:12.5 mem=5557.7M)
Iter 0 ...
Collected 57092 nets for fixing
Evaluate 756(1158) resize, Select 120 cand. (cpu=0:00:23.6 mem=5640.6M)
Commit 16 cand, 15 upSize, 1 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:00:25.9 mem=5641.4M)
Calc. DC (cpu=0:00:26.4 mem=5641.4M) ***
Estimated WNS = -0.101ns, TNS = -67.175ns (cpu=0:00:32.7 mem=5641.4M)
Iter 1 ...
Collected 56997 nets for fixing
Evaluate 753(1305) resize, Select 377 cand. (cpu=0:00:47.9 mem=5645.0M)
Commit 38 cand, 28 upSize, 10 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:00:49.9 mem=5649.4M)
Calc. DC (cpu=0:00:50.3 mem=5649.4M) ***
Estimated WNS = -0.096ns, TNS = -67.420ns (cpu=0:00:56.2 mem=5649.4M)
Iter 2 ...
Collected 57064 nets for fixing
Evaluate 754(1751) resize, Select 132 cand. (cpu=0:01:15 mem=5652.1M)
Commit 21 cand, 20 upSize, 1 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:01:17 mem=5652.8M)
Calc. DC (cpu=0:01:17 mem=5652.8M) ***
Estimated WNS = -0.094ns, TNS = -67.129ns (cpu=0:01:23 mem=5652.8M)
Iter 3 ...
Collected 56999 nets for fixing
Evaluate 757(1524) resize, Select 426 cand. (cpu=0:01:45 mem=5657.7M)
Commit 35 cand, 25 upSize, 10 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:01:48 mem=5661.9M)
Calc. DC (cpu=0:01:49 mem=5661.9M) ***
Estimated WNS = -0.091ns, TNS = -66.361ns (cpu=0:01:55 mem=5661.9M)
Iter 4 ...
Collected 56591 nets for fixing
Evaluate 751(1587) resize, Select 142 cand. (cpu=0:02:13 mem=5664.4M)
Commit 26 cand, 20 upSize, 6 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:02:14 mem=5665.2M)
Calc. DC (cpu=0:02:15 mem=5665.2M) ***
Estimated WNS = -0.089ns, TNS = -65.137ns (cpu=0:02:21 mem=5665.2M)
Iter 5 ...
Collected 56302 nets for fixing
Evaluate 750(1532) resize, Select 403 cand. (cpu=0:02:38 mem=5667.7M)
Commit 27 cand, 22 upSize, 3 downSize, 2 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:02:39 mem=5668.5M)
Calc. DC (cpu=0:02:40 mem=5668.5M) ***
Estimated WNS = -0.089ns, TNS = -64.856ns (cpu=0:02:46 mem=5668.5M)
Iter 6 ...
Collected 56215 nets for fixing
Evaluate 752(1981) resize, Select 121 cand. (cpu=0:03:07 mem=5670.3M)
Commit 13 cand, 12 upSize, 1 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:03:08 mem=5671.9M)
Calc. DC (cpu=0:03:08 mem=5671.9M) ***
Estimated WNS = -0.089ns, TNS = -64.697ns (cpu=0:03:14 mem=5671.9M)
Calc. DC (cpu=0:03:15 mem=5671.9M) ***
*summary: 176 instances changed cell type
density after = 60.322%
*** Finish Post Route Setup Fixing (cpu=0:03:16 mem=5593.0M) ***
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
Info: 40 io nets excluded
Info: 567 clock nets excluded from IPO operation.
*** Start Post Route Setup Fixing (cpu=0:00:00.0 mem=5593.0M) ***
Time Engine : CTE
SSTA Mode : off
MMMC mode : on (10 dominant view(s), 7 view(s) pruned)
Incr. DC : on
Incr POM Mode : on
On Demand POM Mode : on
CTE SubNetWork Mode : on
Up Size : on
Down Size : on
Resize FFs : on
Add Buffer : on
Del Buffer : on
Pin Swap : off
Add InvPair : off
LegalLoc GS : off
Speedup GS : off
Crit. Range : 20%
density before = 60.322%
total 280778 net, 39 ipo_ignored
total 951841 term, 78 ipo_ignored
total 289622 comb inst, 37273 fixed, 273 dont_touch, 36923 no_footp
total 21214 seq inst, 18 fixed, 3 dont_touch, 3 no_footp
total 240 footprint(s)
10 footprint(s) with 0 cell(s)
36 footprint(s) with 1 cell(s)
16 footprint(s) with 2 cell(s)
3 footprint(s) with 3 cell(s)
119 footprint(s) with 4 cell(s)
13 footprint(s) with 5 cell(s)
13 footprint(s) with 6 cell(s)
13 footprint(s) with 7 cell(s)
7 footprint(s) with 8 cell(s)
1 footprint(s) with 9 cell(s)
9 footprint(s) with 10+ cell(s)
BUFFER FOOTPRINT (BUFM2S) :
CKBUFM1S(s) CKBUFM2S(s) BUFM2S(s) CKBUFM3S(s) BUFM3S(s)
CKBUFM4S(s) BUFM4S(s) BUFM5S(s) CKBUFM6S(s) BUFM6S(s)
CKBUFM8S(s) BUFM8S(s) BUFM10S(s) CKBUFM12S(s) BUFM12S(s)
BUFM14S(s) CKBUFM16S(s) BUFM16S(s) BUFM18S(s) CKBUFM20S(s)
BUFM20S(s) CKBUFM22SA(s) BUFM22SA(s) CKBUFM24S(s) BUFM24S(s)
CKBUFM26SA(s) BUFM26SA(s) CKBUFM32S(s) BUFM32SA(s) CKBUFM40S(s)
BUFM40SA(s) CKBUFM48S(s) BUFM48SA(s) CKBUFM1R(s) BUFM2R(s)
CKBUFM2R(s) CKBUFM3R(s) BUFM3R(s) CKBUFM4R(s) BUFM4R(s)
DEL1M4R(s) BUFM5R(s) CKBUFM6R(s) BUFM6R(s) CKBUFM8R(s)
BUFM8R(s) BUFM10R(s) CKBUFM12R(s) BUFM12R(s) BUFM14R(s)
CKBUFM16R(s) BUFM16R(s) BUFM18R(s) CKBUFM20R(s) BUFM20R(s)
CKBUFM22RA(s) BUFM22RA(s) CKBUFM24R(s) BUFM24R(s) BUFM26RA(s)
CKBUFM26RA(s) CKBUFM32R(s) BUFM32RA(s) CKBUFM40R(s) BUFM40RA(s)
CKBUFM48R(s) BUFM48RA(s) DEL1M1W(s) CKBUFM1W BUFM2W
CKBUFM2W CKBUFM3W(s) BUFM3W(s) CKBUFM4W BUFM4W
DEL1M4W(s) BUFM5W(s) CKBUFM6W BUFM6W CKBUFM8W
BUFM8W BUFM10W CKBUFM12W BUFM12W BUFM14W
CKBUFM16W BUFM16W BUFM18W CKBUFM20W BUFM20W
CKBUFM22WA BUFM22WA CKBUFM24W BUFM24W BUFM26WA
CKBUFM26WA CKBUFM32W BUFM32WA BUFM40WA CKBUFM40W
BUFM48WA CKBUFM48W
DELAY FOOTPRINT (DEL1M1S) :
DEL4M1S DEL3M1S DEL2M1S DEL1M1S DEL4M4S
DEL3M4S DEL2M4S DEL1M4S DEL4M1R DEL3M1R
DEL2M1R DEL1M1R DEL4M4R DEL3M4R DEL2M4R
DEL4M1W DEL3M1W DEL2M1W DEL4M4W DEL3M4W
DEL2M4W
Estimated WNS = -0.089ns, TNS = -64.697ns (cpu=0:00:13.2 mem=5676.5M)
Iter 0 ...
Collected 56187 nets for fixing
Evaluate 751(1492) resize, Select 122 cand. (cpu=0:00:30.6 mem=5683.0M)
Evaluate 21(2334) addBuf, Select 5 cand. (cpu=0:00:37.1 mem=5720.0M)
Evaluate 102(103) delBuf, Select 6 cand. (cpu=0:00:37.9 mem=5721.0M)
Commit 19 cand, 7 upSize, 4 downSize, 0 sameSize, 3 addBuf, 5 delBuf, 0 pinSwap (cpu=0:00:38.9 mem=5721.6M)
Calc. DC (cpu=0:00:40.4 mem=5721.6M) ***
Estimated WNS = -0.084ns, TNS = -64.315ns (cpu=0:00:46.7 mem=5721.6M)
Iter 1 ...
Collected 56018 nets for fixing
Evaluate 760(1924) resize, Select 354 cand. (cpu=0:01:05 mem=5722.1M)
Evaluate 25(2456) addBuf, Select 5 cand. (cpu=0:01:11 mem=5722.1M)
Evaluate 101(102) delBuf, Select 3 cand. (cpu=0:01:12 mem=5722.1M)
Commit 19 cand, 10 upSize, 8 downSize, 0 sameSize, 1 addBuf, 0 delBuf, 0 pinSwap (cpu=0:01:13 mem=5722.9M)
Calc. DC (cpu=0:01:14 mem=5722.9M) ***
Estimated WNS = -0.082ns, TNS = -64.197ns (cpu=0:01:20 mem=5722.9M)
Iter 2 ...
Collected 55964 nets for fixing
Evaluate 752(2118) resize, Select 135 cand. (cpu=0:01:39 mem=5723.5M)
Evaluate 22(2889) addBuf, Select 8 cand. (cpu=0:01:46 mem=5723.5M)
Evaluate 101(101) delBuf, Select 2 cand. (cpu=0:01:47 mem=5724.5M)
Commit 23 cand, 17 upSize, 0 downSize, 0 sameSize, 5 addBuf, 1 delBuf, 0 pinSwap (cpu=0:01:48 mem=5725.2M)
Calc. DC (cpu=0:01:50 mem=5725.2M) ***
Estimated WNS = -0.080ns, TNS = -63.365ns (cpu=0:01:55 mem=5725.2M)
Iter 3 ...
Collected 55645 nets for fixing
Evaluate 754(2763) resize, Select 360 cand. (cpu=0:02:23 mem=5726.8M)
Evaluate 22(2367) addBuf, Select 7 cand. (cpu=0:02:30 mem=5726.8M)
Evaluate 101(104) delBuf, Select 4 cand. (cpu=0:02:30 mem=5726.8M)
Commit 29 cand, 19 upSize, 7 downSize, 0 sameSize, 2 addBuf, 1 delBuf, 0 pinSwap (cpu=0:02:33 mem=5730.8M)
Calc. DC (cpu=0:02:34 mem=5730.8M) ***
Estimated WNS = -0.079ns, TNS = -63.080ns (cpu=0:02:40 mem=5730.8M)
Iter 4 ...
Collected 55459 nets for fixing
Evaluate 750(2980) resize, Select 150 cand. (cpu=0:03:05 mem=5731.4M)
Evaluate 58(6818) addBuf, Select 22 cand. (cpu=0:03:31 mem=5731.4M)
Evaluate 101(101) delBuf, Select 2 cand. (cpu=0:03:32 mem=5731.4M)
Commit 38 cand, 17 upSize, 7 downSize, 2 sameSize, 10 addBuf, 2 delBuf, 0 pinSwap (cpu=0:03:34 mem=5734.3M)
Calc. DC (cpu=0:03:36 mem=5734.3M) ***
Estimated WNS = -0.078ns, TNS = -62.566ns (cpu=0:03:42 mem=5734.3M)
Iter 5 ...
Collected 55306 nets for fixing
Evaluate 756(3061) resize, Select 419 cand. (cpu=0:04:11 mem=5736.1M)
Evaluate 50(5461) addBuf, Select 16 cand. (cpu=0:04:33 mem=5736.1M)
Evaluate 101(101) delBuf, Select 3 cand. (cpu=0:04:34 mem=5736.1M)
Commit 40 cand, 19 upSize, 14 downSize, 0 sameSize, 6 addBuf, 1 delBuf, 0 pinSwap (cpu=0:04:39 mem=5738.9M)
Calc. DC (cpu=0:04:40 mem=5738.9M) ***
Estimated WNS = -0.080ns, TNS = -61.283ns (cpu=0:04:46 mem=5738.9M)
Iter 6 ...
Collected 54927 nets for fixing
Evaluate 754(3159) resize, Select 134 cand. (cpu=0:05:20 mem=5739.4M)
Evaluate 40(4773) addBuf, Select 13 cand. (cpu=0:05:44 mem=5739.4M)
Evaluate 101(101) delBuf, Select 3 cand. (cpu=0:05:45 mem=5739.4M)
Commit 31 cand, 20 upSize, 7 downSize, 0 sameSize, 3 addBuf, 1 delBuf, 0 pinSwap (cpu=0:05:48 mem=5743.3M)
Calc. DC (cpu=0:05:49 mem=5743.3M) ***
Estimated WNS = -0.078ns, TNS = -61.256ns (cpu=0:05:55 mem=5743.3M)
Iter 7 ...
Collected 54918 nets for fixing
Evaluate 751(1803) resize, Select 352 cand. (cpu=0:06:24 mem=5753.9M)
Evaluate 26(2805) addBuf, Select 8 cand. (cpu=0:06:38 mem=5753.9M)
Evaluate 102(103) delBuf, Select 2 cand. (cpu=0:06:39 mem=5753.9M)
Commit 31 cand, 20 upSize, 7 downSize, 1 sameSize, 2 addBuf, 1 delBuf, 0 pinSwap (cpu=0:06:42 mem=5755.8M)
Calc. DC (cpu=0:06:44 mem=5755.8M) ***
Estimated WNS = -0.077ns, TNS = -60.758ns (cpu=0:06:49 mem=5755.8M)
Iter 8 ...
Collected 54602 nets for fixing
Evaluate 756(3105) resize, Select 151 cand. (cpu=0:07:15 mem=5756.3M)
Evaluate 101(10191) addBuf, Select 34 cand. (cpu=0:07:51 mem=5757.3M)
Evaluate 102(102) delBuf, Select 4 cand. (cpu=0:07:52 mem=5757.3M)
Commit 41 cand, 17 upSize, 3 downSize, 0 sameSize, 19 addBuf, 2 delBuf, 0 pinSwap (cpu=0:07:55 mem=5760.2M)
Calc. DC (cpu=0:07:56 mem=5760.2M) ***
Estimated WNS = -0.076ns, TNS = -60.510ns (cpu=0:08:02 mem=5760.2M)
Iter 9 ...
Collected 54513 nets for fixing
Evaluate 750(3118) resize, Select 400 cand. (cpu=0:08:37 mem=5760.8M)
Evaluate 26(2942) addBuf, Select 4 cand. (cpu=0:08:45 mem=5760.8M)
Evaluate 101(101) delBuf, Select 2 cand. (cpu=0:08:46 mem=5760.8M)
Commit 38 cand, 19 upSize, 14 downSize, 1 sameSize, 2 addBuf, 2 delBuf, 0 pinSwap (cpu=0:08:49 mem=5765.6M)
Calc. DC (cpu=0:08:51 mem=5765.6M) ***
Estimated WNS = -0.076ns, TNS = -60.029ns (cpu=0:08:57 mem=5765.6M)
Iter 10 ...
Collected 54369 nets for fixing
Evaluate 752(2957) resize, Select 163 cand. (cpu=0:09:25 mem=5766.2M)
Evaluate 30(3764) addBuf, Select 14 cand. (cpu=0:09:42 mem=5766.2M)
Evaluate 101(101) delBuf, Select 2 cand. (cpu=0:09:43 mem=5766.2M)
Commit 32 cand, 19 upSize, 5 downSize, 0 sameSize, 7 addBuf, 1 delBuf, 0 pinSwap (cpu=0:09:45 mem=5767.8M)
Calc. DC (cpu=0:09:46 mem=5767.8M) ***
Estimated WNS = -0.074ns, TNS = -59.846ns (cpu=0:09:52 mem=5767.8M)
Iter 11 ...
Collected 54333 nets for fixing
Evaluate 758(2911) resize, Select 346 cand. (cpu=0:10:20 mem=5769.4M)
Evaluate 21(2464) addBuf, Select 8 cand. (cpu=0:10:30 mem=5769.4M)
Evaluate 101(101) delBuf, Select 1 cand. (cpu=0:10:30 mem=5769.4M)
Commit 34 cand, 18 upSize, 11 downSize, 1 sameSize, 3 addBuf, 1 delBuf, 0 pinSwap (cpu=0:10:34 mem=5771.0M)
Calc. DC (cpu=0:10:35 mem=5771.0M) ***
Estimated WNS = -0.074ns, TNS = -59.464ns (cpu=0:10:41 mem=5771.0M)
Iter 12 ...
Collected 54170 nets for fixing
Evaluate 750(3063) resize, Select 172 cand. (cpu=0:11:18 mem=5771.6M)
Evaluate 24(3152) addBuf, Select 7 cand. (cpu=0:11:30 mem=5772.6M)
Evaluate 103(104) delBuf, Select 2 cand. (cpu=0:11:31 mem=5772.6M)
Commit 38 cand, 31 upSize, 4 downSize, 0 sameSize, 3 addBuf, 0 delBuf, 0 pinSwap (cpu=0:11:34 mem=5776.5M)
Calc. DC (cpu=0:11:35 mem=5776.5M) ***
Estimated WNS = -0.073ns, TNS = -59.152ns (cpu=0:11:41 mem=5776.5M)
Iter 13 ...
Collected 54145 nets for fixing
Evaluate 751(3104) resize, Select 388 cand. (cpu=0:12:13 mem=5777.0M)
Evaluate 46(4929) addBuf, Select 17 cand. (cpu=0:12:33 mem=5777.0M)
Evaluate 102(102) delBuf, Select 2 cand. (cpu=0:12:34 mem=5777.0M)
Commit 40 cand, 19 upSize, 14 downSize, 2 sameSize, 4 addBuf, 1 delBuf, 0 pinSwap (cpu=0:12:38 mem=5779.8M)
Calc. DC (cpu=0:12:39 mem=5779.8M) ***
Estimated WNS = -0.073ns, TNS = -59.063ns (cpu=0:12:45 mem=5779.8M)
Iter 14 ...
Collected 54135 nets for fixing
Evaluate 752(2800) resize, Select 155 cand. (cpu=0:13:15 mem=5781.3M)
Evaluate 60(6563) addBuf, Select 18 cand. (cpu=0:13:51 mem=5781.3M)
Evaluate 103(103) delBuf, Select 1 cand. (cpu=0:13:52 mem=5781.3M)
Commit 28 cand, 18 upSize, 5 downSize, 0 sameSize, 5 addBuf, 0 delBuf, 0 pinSwap (cpu=0:13:54 mem=5782.8M)
Calc. DC (cpu=0:13:55 mem=5782.8M) ***
Estimated WNS = -0.072ns, TNS = -58.978ns (cpu=0:14:01 mem=5782.8M)
*summary: 387 instances changed cell type
density after = 60.355%
*** Finish Post Route Setup Fixing (cpu=0:14:02 mem=5694.2M) ***
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
*** Timing NOT met, worst failing slack is -0.072
*** Check timing (0:00:00.3)
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
Info: 40 io nets excluded
Info: 567 clock nets excluded from IPO operation.
*** Start Post Route Setup Fixing (cpu=0:00:00.0 mem=5681.2M) ***
Time Engine : CTE
SSTA Mode : off
MMMC mode : on (10 dominant view(s), 7 view(s) pruned)
Incr. DC : on
Incr POM Mode : on
On Demand POM Mode : on
CTE SubNetWork Mode : on
Up Size : on
Down Size : on
Resize FFs : on
Add Buffer : off
Del Buffer : off
Pin Swap : off
Add InvPair : off
LegalLoc GS : off
Speedup GS : off
Crit. Range : 20%
density before = 60.355%
total 280834 net, 39 ipo_ignored
total 951953 term, 78 ipo_ignored
total 289678 comb inst, 37273 fixed, 273 dont_touch, 36923 no_footp
total 21214 seq inst, 18 fixed, 3 dont_touch, 3 no_footp
total 240 footprint(s)
10 footprint(s) with 0 cell(s)
36 footprint(s) with 1 cell(s)
16 footprint(s) with 2 cell(s)
3 footprint(s) with 3 cell(s)
119 footprint(s) with 4 cell(s)
13 footprint(s) with 5 cell(s)
13 footprint(s) with 6 cell(s)
13 footprint(s) with 7 cell(s)
7 footprint(s) with 8 cell(s)
1 footprint(s) with 9 cell(s)
9 footprint(s) with 10+ cell(s)
Estimated WNS = -0.072ns, TNS = -58.978ns (cpu=0:00:13.1 mem=5758.5M)
Iter 0 ...
Collected 54087 nets for fixing
Evaluate 751(2908) resize, Select 156 cand. (cpu=0:00:42.1 mem=5764.1M)
Commit 24 cand, 19 upSize, 5 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:00:43.6 mem=5768.1M)
Calc. DC (cpu=0:00:44.0 mem=5768.1M) ***
Estimated WNS = -0.072ns, TNS = -58.793ns (cpu=0:00:49.9 mem=5768.1M)
Iter 1 ...
Collected 54038 nets for fixing
Evaluate 761(2906) resize, Select 334 cand. (cpu=0:01:20 mem=5768.7M)
Commit 25 cand, 14 upSize, 9 downSize, 2 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:01:23 mem=5770.7M)
Calc. DC (cpu=0:01:23 mem=5770.7M) ***
Estimated WNS = -0.071ns, TNS = -58.572ns (cpu=0:01:29 mem=5770.7M)
Iter 2 ...
Collected 53949 nets for fixing
Evaluate 753(3024) resize, Select 159 cand. (cpu=0:01:59 mem=5771.3M)
Commit 22 cand, 18 upSize, 4 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:02:00 mem=5773.0M)
Calc. DC (cpu=0:02:01 mem=5773.0M) ***
Estimated WNS = -0.071ns, TNS = -58.420ns (cpu=0:02:07 mem=5773.0M)
Iter 3 ...
Collected 53886 nets for fixing
Evaluate 751(2638) resize, Select 338 cand. (cpu=0:02:32 mem=5774.8M)
Commit 32 cand, 19 upSize, 10 downSize, 3 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:02:35 mem=5776.7M)
Calc. DC (cpu=0:02:35 mem=5776.7M) ***
Estimated WNS = -0.070ns, TNS = -57.836ns (cpu=0:02:41 mem=5776.7M)
Iter 4 ...
Collected 53443 nets for fixing
Evaluate 751(2907) resize, Select 147 cand. (cpu=0:03:11 mem=5777.3M)
Commit 19 cand, 17 upSize, 2 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:03:13 mem=5777.9M)
Calc. DC (cpu=0:03:13 mem=5777.9M) ***
Estimated WNS = -0.070ns, TNS = -57.742ns (cpu=0:03:19 mem=5777.9M)
Iter 5 ...
Collected 53438 nets for fixing
Evaluate 751(2955) resize, Select 385 cand. (cpu=0:03:57 mem=5779.5M)
Commit 34 cand, 20 upSize, 13 downSize, 1 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:04:02 mem=5783.4M)
Calc. DC (cpu=0:04:02 mem=5783.4M) ***
Estimated WNS = -0.070ns, TNS = -56.255ns (cpu=0:04:08 mem=5783.4M)
Iter 6 ...
Collected 53217 nets for fixing
Evaluate 751(3032) resize, Select 168 cand. (cpu=0:04:36 mem=5783.9M)
Commit 33 cand, 29 upSize, 4 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:04:38 mem=5785.8M)
Calc. DC (cpu=0:04:39 mem=5785.8M) ***
Estimated WNS = -0.070ns, TNS = -56.024ns (cpu=0:04:45 mem=5785.8M)
Iter 7 ...
Collected 52769 nets for fixing
Evaluate 753(2719) resize, Select 365 cand. (cpu=0:05:11 mem=5786.4M)
Commit 31 cand, 20 upSize, 11 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:05:13 mem=5788.0M)
Calc. DC (cpu=0:05:14 mem=5788.0M) ***
Estimated WNS = -0.070ns, TNS = -55.845ns (cpu=0:05:20 mem=5788.0M)
Iter 8 ...
Collected 52702 nets for fixing
Evaluate 751(6228) resize, Select 142 cand. (cpu=0:06:23 mem=5789.6M)
Commit 21 cand, 20 upSize, 1 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:06:24 mem=5792.2M)
Calc. DC (cpu=0:06:24 mem=5792.2M) ***
Estimated WNS = -0.070ns, TNS = -55.785ns (cpu=0:06:30 mem=5792.2M)
Calc. DC (cpu=0:06:31 mem=5792.2M) ***
*summary: 241 instances changed cell type
density after = 60.374%
*** Finish Post Route Setup Fixing (cpu=0:06:31 mem=5712.9M) ***
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
Info: 40 io nets excluded
Info: 567 clock nets excluded from IPO operation.
*** Start Post Route Setup Fixing (cpu=0:00:00.0 mem=5712.9M) ***
Time Engine : CTE
SSTA Mode : off
MMMC mode : on (10 dominant view(s), 7 view(s) pruned)
Incr. DC : on
Incr POM Mode : on
On Demand POM Mode : on
CTE SubNetWork Mode : on
Up Size : on
Down Size : on
Resize FFs : on
Add Buffer : on
Del Buffer : on
Pin Swap : off
Add InvPair : off
LegalLoc GS : off
Speedup GS : off
Crit. Range : 20%
density before = 60.374%
total 280834 net, 39 ipo_ignored
total 951953 term, 78 ipo_ignored
total 289678 comb inst, 37273 fixed, 273 dont_touch, 36923 no_footp
total 21214 seq inst, 18 fixed, 3 dont_touch, 3 no_footp
total 240 footprint(s)
10 footprint(s) with 0 cell(s)
36 footprint(s) with 1 cell(s)
16 footprint(s) with 2 cell(s)
3 footprint(s) with 3 cell(s)
119 footprint(s) with 4 cell(s)
13 footprint(s) with 5 cell(s)
13 footprint(s) with 6 cell(s)
13 footprint(s) with 7 cell(s)
7 footprint(s) with 8 cell(s)
1 footprint(s) with 9 cell(s)
9 footprint(s) with 10+ cell(s)
BUFFER FOOTPRINT (BUFM2S) :
CKBUFM1S(s) CKBUFM2S(s) BUFM2S(s) CKBUFM3S(s) BUFM3S(s)
CKBUFM4S(s) BUFM4S(s) BUFM5S(s) CKBUFM6S(s) BUFM6S(s)
CKBUFM8S(s) BUFM8S(s) BUFM10S(s) CKBUFM12S(s) BUFM12S(s)
BUFM14S(s) CKBUFM16S(s) BUFM16S(s) BUFM18S(s) CKBUFM20S(s)
BUFM20S(s) CKBUFM22SA(s) BUFM22SA(s) CKBUFM24S(s) BUFM24S(s)
CKBUFM26SA(s) BUFM26SA(s) CKBUFM32S(s) BUFM32SA(s) CKBUFM40S(s)
BUFM40SA(s) CKBUFM48S(s) BUFM48SA(s) CKBUFM1R(s) BUFM2R(s)
CKBUFM2R(s) CKBUFM3R(s) BUFM3R(s) CKBUFM4R(s) BUFM4R(s)
DEL1M4R(s) BUFM5R(s) CKBUFM6R(s) BUFM6R(s) CKBUFM8R(s)
BUFM8R(s) BUFM10R(s) CKBUFM12R(s) BUFM12R(s) BUFM14R(s)
CKBUFM16R(s) BUFM16R(s) BUFM18R(s) CKBUFM20R(s) BUFM20R(s)
CKBUFM22RA(s) BUFM22RA(s) CKBUFM24R(s) BUFM24R(s) BUFM26RA(s)
CKBUFM26RA(s) CKBUFM32R(s) BUFM32RA(s) CKBUFM40R(s) BUFM40RA(s)
CKBUFM48R(s) BUFM48RA(s) DEL1M1W(s) CKBUFM1W BUFM2W
CKBUFM2W CKBUFM3W(s) BUFM3W(s) CKBUFM4W BUFM4W
DEL1M4W(s) BUFM5W(s) CKBUFM6W BUFM6W CKBUFM8W
BUFM8W BUFM10W CKBUFM12W BUFM12W BUFM14W
CKBUFM16W BUFM16W BUFM18W CKBUFM20W BUFM20W
CKBUFM22WA BUFM22WA CKBUFM24W BUFM24W BUFM26WA
CKBUFM26WA CKBUFM32W BUFM32WA BUFM40WA CKBUFM40W
BUFM48WA CKBUFM48W
DELAY FOOTPRINT (DEL1M1S) :
DEL4M1S DEL3M1S DEL2M1S DEL1M1S DEL4M4S
DEL3M4S DEL2M4S DEL1M4S DEL4M1R DEL3M1R
DEL2M1R DEL1M1R DEL4M4R DEL3M4R DEL2M4R
DEL4M1W DEL3M1W DEL2M1W DEL4M4W DEL3M4W
DEL2M4W
Estimated WNS = -0.070ns, TNS = -55.785ns (cpu=0:00:13.0 mem=5783.2M)
Iter 0 ...
Collected 52666 nets for fixing
Evaluate 750(1569) resize, Select 149 cand. (cpu=0:00:30.2 mem=5789.8M)
Evaluate 24(2818) addBuf, Select 5 cand. (cpu=0:00:37.7 mem=5789.8M)
Evaluate 104(104) delBuf, Select 5 cand. (cpu=0:00:38.5 mem=5789.8M)
Commit 27 cand, 19 upSize, 4 downSize, 1 sameSize, 1 addBuf, 2 delBuf, 0 pinSwap (cpu=0:00:39.5 mem=5790.7M)
Calc. DC (cpu=0:00:40.9 mem=5790.7M) ***
Estimated WNS = -0.069ns, TNS = -55.536ns (cpu=0:00:47.0 mem=5790.7M)
Iter 1 ...
Collected 52546 nets for fixing
Evaluate 755(1522) resize, Select 309 cand. (cpu=0:01:05 mem=5791.3M)
Evaluate 24(2465) addBuf, Select 5 cand. (cpu=0:01:12 mem=5791.3M)
Evaluate 101(101) delBuf, Select 2 cand. (cpu=0:01:12 mem=5791.3M)
Commit 16 cand, 9 upSize, 5 downSize, 0 sameSize, 0 addBuf, 2 delBuf, 0 pinSwap (cpu=0:01:13 mem=5792.1M)
Calc. DC (cpu=0:01:15 mem=5792.1M) ***
Estimated WNS = -0.069ns, TNS = -55.469ns (cpu=0:01:21 mem=5792.1M)
*summary: 38 instances changed cell type
density after = 60.377%
*** Finish Post Route Setup Fixing (cpu=0:01:21 mem=5719.9M) ***
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
*** Timing NOT met, worst failing slack is -0.069
*** Check timing (0:00:00.3)
Starting refinePlace ...
Spread Effort: high, post-route mode.
Finished Phase I. CPU Time = 0:00:20.7, Real Time = 0:00:21.0
move report: preRPlace moves 3655 insts, mean move: 0.81 um, max move: 7.20 um
max move on inst (top/i_gmu_groestl/U7264): (579.80, 440.40) --> (579.80, 433.20)
move report: rPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: overall moves 3655 insts, mean move: 0.81 um, max move: 7.20 um
max move on inst (top/i_gmu_groestl/U7264): (579.80, 440.40) --> (579.80, 433.20)
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 7.20 um
inst (top/i_gmu_groestl/U7264) with max move: (579.8, 440.4) -> (579.8, 433.2)
mean (X+Y) = 0.81 um
Total instances moved : 3655
*** cpu=0:00:22.5 mem=5526.7M mem(used)=16.0M***
Total net length = 1.413e+07 (6.600e+06 7.531e+06) (ext = 0.000e+00)
default core: bins with density > 0.75 = 24.6 % ( 1905 / 7744 )
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
Summary (cpu=27.05min real=27.07min mem=5510.7M)
------------------------------------------------------------
+--------------------+---------+
| Setup mode | all |
+--------------------+---------+
| WNS (ns):| -0.069 |
| TNS (ns):| -55.465 |
| Violating Paths:| 1628 |
| All Paths:| 84923 |
+--------------------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 0 (0) | 0.000 | 0 (0) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 60.377%
------------------------------------------------------------
**optDesign ... cpu = 0:40:28, real = 0:40:32, mem = 5781.4M **
*** Timing NOT met, worst failing slack is -0.069
*** Check timing (0:00:00.1)
setClockDomains -fromType register -toType register
**WARN: (ENCCTE-318): Paths not in the reg2reg domain will be added 1000ns slack adjustment
*** Timing NOT met, worst failing slack is -0.069
*** Check timing (0:01:24)
Active setup views: dummy_slow_view ethz_blake_slow_view ethz_groestl_slow_view ethz_jh_slow_view ethz_keccak_slow_view ethz_sha2_slow_view ethz_skein_slow_view gmu_blake_slow_view gmu_groestl_slow_view gmu_jh_slow_view gmu_keccak_slow_view gmu_sha2_slow_view gmu_skein_slow_view ram1_slow_view ram2_slow_view ram3_slow_view test_slow_view
Active hold views: hold_fast_view
-routeWithEco false # bool, default=false, user setting
-routeWithEco true # bool, default=false, user setting
-routeSelectedNetOnly false # bool, default=false
-routeWithTimingDriven true # bool, default=false, user setting
-routeWithTimingDriven false # bool, default=false, user setting
-routeWithSiDriven false # bool, default=false, user setting
-drouteStartIteration 0 # int, default=0, user setting
-drouteStartIteration 0 # int, default=0
globalDetailRoute
#Start globalDetailRoute on Fri Sep 30 09:16:33 2011
#
Closing parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d'. 133780 times net's RC data read were performed.
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_0 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_1 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_2 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_3 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_4 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_5 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_6 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_7 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_8 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_9 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_10 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_11 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_12 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_13 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_14 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_15 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_16 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_17 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_18 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34 Repeated 20 times. Will be suppressed.) Power/Ground pin VSSIO of instance fillperi_N_19 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRDB-733) PIN AlgSelxSI[0] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN AlgSelxSI[1] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN AlgSelxSI[2] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN AlgSelxSI[3] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN ClkDxCI in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN ClkxCI in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN CoreScanEnxTI in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN CoreScanInxTI in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[0] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[10] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[11] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[12] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[13] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[14] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[15] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[1] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[2] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[3] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[4] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733 Repeated 20 times. Will be suppressed.) PIN DataOutxDO[5] in CELL_VIEW shabziger_chip,init does not have physical port
#NanoRoute Version v10.12-s010 NR110720-1815/10_10_USR2-UB
#Loading the last recorded routing design signature
#Created 76 NETS and 0 SPECIALNETS new signatures
#Summary of the placement changes since last routing:
# Number of instances added (including moved) = 3630
# Number of instances deleted (including moved) = 3577
# Number of instances resized = 489
# Number of instances with same cell size swap = 1
# Number of instances with pin swaps = 56
# Total number of placement changes (moved instances are counted twice) = 7696
#Using multithreading with 8 threads.
# ME1 H Track-Pitch = 0.200 Line-2-Via Pitch = 0.185
# ME2 V Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME3 H Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME4 V Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME5 H Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME6 V Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME7 H Track-Pitch = 0.400 Line-2-Via Pitch = 0.400
# ME8 V Track-Pitch = 4.000 Line-2-Via Pitch = 4.000
#Merging special wires using 8 threads...
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (967.150 803.035) on ME1 for NET top/ClkxC__L6_N25. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (920.750 698.635) on ME1 for NET top/ClkxC__L6_N28. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (982.905 756.240) on ME1 for NET top/ClkxC__L6_N33. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (994.710 756.240) on ME1 for NET top/ClkxC__L6_N33. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (987.950 756.235) on ME1 for NET top/ClkxC__L6_N33. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (991.310 714.920) on ME1 for NET top/ClkxC__L6_N35. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (996.950 714.965) on ME1 for NET top/ClkxC__L6_N35. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (1033.690 898.710) on ME1 for NET top/ClkxC__L6_N49. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (946.550 887.765) on ME1 for NET top/ClkxC__L6_N50. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (970.950 887.765) on ME1 for NET top/ClkxC__L6_N50. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (972.105 862.560) on ME1 for NET top/ClkxC__L6_N51. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (976.550 862.565) on ME1 for NET top/ClkxC__L6_N51. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (959.705 862.560) on ME1 for NET top/ClkxC__L6_N51. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (965.350 862.565) on ME1 for NET top/ClkxC__L6_N51. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (1013.550 875.035) on ME1 for NET top/ClkxC__L6_N52. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN B at (532.400 367.400) on ME1 for NET top/Core10InxD[180]. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN A2 at (579.740 417.875) on ME1 for NET top/Core10InxD[216]. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN A2 at (514.515 427.090) on ME1 for NET top/Core10InxD[243]. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN B at (481.800 427.000) on ME1 for NET top/Core10InxD[272]. The NET is considered partially routed.
#WARNING (NRDB-1005 Repeated 20 times. Will be suppressed.) Can not establish connection to PIN A at (509.000 583.400) on ME1 for NET top/Core10InxD[328]. The NET is considered partially routed.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/FE_OFN2782_InxD_204_ are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_blake/datapath_gen/DP_OP_75J1_127_7150_n305 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_blake/datapath_gen/DP_OP_75J1_127_7150_n354 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_blake/datapath_gen/DP_OP_75J1_127_7150_n890 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_blake/datapath_gen/n1829 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/FE_OCPN20625_n1598 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/FE_OCPN22413_n22261 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/FE_OCPN22799_n906 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/FE_OCPN23147_n25575 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/FE_OFN13593_n32580 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/FE_OFN14891_n35730 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/dp_fx2_256_from_register_172_ are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/dp_fx2_256_from_register_510_ are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/dp_fx2_256_rounds_after_shiftrow[327] are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/dp_fx2_256_rounds_after_subbyte[181] are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/dp_fx2_256_rounds_after_subbyte[462] are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/dp_fx2_256_rounds_mc/n864 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/dp_fx2_256_rounds_n651 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/dp_fx2_256_to_register_409_ are dangling and deleted.
#WARNING (NRDB-874 Repeated 20 times. Will be suppressed.) Some WIRE segments on routed NET top/i_gmu_groestl/dp_fx2_256_to_register_442_ are dangling and deleted.
#10605 routed nets are extracted.
# 8998 (3.17%) extracted nets are partially routed.
#269461 routed nets are imported.
#1 (0.00%) nets are without wires.
#3737 routed nets are fixed|skipped|trivial (not extracted).
#Total number of nets = 283804.
#Number of eco nets is 8998
#
#Start data preparation...
#Force regenerating Ggrids.
#Auto generating G-grids with size=15 tracks, using layer ME2's pitch = 0.200.
#Using automatically generated G-grids.
#
#Data preparation is done on Fri Sep 30 09:17:15 2011
#
#Analyzing routing resource...
#Routing resource analysis is done on Fri Sep 30 09:17:22 2011
#
# Resource Analysis:
#
# Routing #Avail #Track #Total %Gcell
# Layer Direction Track Blocked Gcell Blocked
# --------------------------------------------------------------
# Metal 1 H 5808 3565 391250 74.26%
# Metal 2 V 5718 3657 391250 43.74%
# Metal 3 H 5885 3489 391250 36.36%
# Metal 4 V 5858 3516 391250 42.89%
# Metal 5 H 7164 2209 391250 22.09%
# Metal 6 V 7101 2273 391250 29.79%
# Metal 7 H 2749 1937 391250 24.29%
# Metal 8 V 239 228 391250 61.74%
# --------------------------------------------------------------
# Total 40525 36.22% 3130000 41.89%
#
# 1567 nets (0.55%) with 1 preferred extra spacing.
# 9 nets (0.00%) with 2 preferred extra spacing.
#
#
#cpu time = 00:00:08, elapsed time = 00:00:08, memory = 5825.00 (Mb)
#
#start global routing iteration 1...
#cpu time = 00:00:13, elapsed time = 00:00:06, memory = 5827.00 (Mb)
#
#start global routing iteration 2...
#cpu time = 00:00:04, elapsed time = 00:00:04, memory = 5840.00 (Mb)
#
#start global routing iteration 3...
#cpu time = 00:00:11, elapsed time = 00:00:06, memory = 5834.00 (Mb)
#
#
# Congestion Analysis: (blocked Gcells are excluded)
#
# OverCon OverCon OverCon OverCon
# #Gcell #Gcell #Gcell #Gcell %Gcell
# Layer (1-3) (4-7) (8-11) (12-15) OverCon
# --------------------------------------------------------------------------
# Metal 1 822(0.56%) 3(0.00%) 0(0.00%) 0(0.00%) (0.56%)
# Metal 2 6456(2.61%) 1137(0.46%) 139(0.06%) 15(0.01%) (3.14%)
# Metal 3 3071(1.23%) 338(0.14%) 25(0.01%) 2(0.00%) (1.38%)
# Metal 4 1542(0.61%) 44(0.02%) 0(0.00%) 0(0.00%) (0.63%)
# Metal 5 119(0.04%) 1(0.00%) 0(0.00%) 0(0.00%) (0.04%)
# Metal 6 78(0.03%) 1(0.00%) 0(0.00%) 0(0.00%) (0.03%)
# Metal 7 93(0.03%) 0(0.00%) 0(0.00%) 0(0.00%) (0.03%)
# Metal 8 35(0.02%) 0(0.00%) 0(0.00%) 0(0.00%) (0.02%)
# --------------------------------------------------------------------------
# Total 12216(0.63%) 1524(0.08%) 164(0.01%) 17(0.00%) (0.71%)
#
# The worst congested Gcell overcon (routing demand over resource in number of tracks) = 15
#
#Complete Global Routing.
#Total number of nets with non-default rule or having extra spacing = 1576
#Total wire length = 16458481 um.
#Total half perimeter of net bounding box = 14227415 um.
#Total wire length on LAYER ME1 = 180906 um.
#Total wire length on LAYER ME2 = 2604318 um.
#Total wire length on LAYER ME3 = 3567914 um.
#Total wire length on LAYER ME4 = 3072349 um.
#Total wire length on LAYER ME5 = 3626112 um.
#Total wire length on LAYER ME6 = 2726548 um.
#Total wire length on LAYER ME7 = 509358 um.
#Total wire length on LAYER ME8 = 170975 um.
#Total number of vias = 2803964
#Total number of multi-cut vias = 27532 ( 1.0%)
#Total number of single cut vias = 2776432 ( 99.0%)
#Up-Via Summary (total 2803964):
# single-cut multi-cut Total
#-----------------------------------------------------------
# Metal 1 995533 (100.0%) 0 ( 0.0%) 995533
# Metal 2 1062653 (100.0%) 0 ( 0.0%) 1062653
# Metal 3 383111 (100.0%) 0 ( 0.0%) 383111
# Metal 4 200918 (100.0%) 49 ( 0.0%) 200967
# Metal 5 125333 (100.0%) 0 ( 0.0%) 125333
# Metal 6 3 ( 0.0%) 27483 (100.0%) 27486
# Metal 7 8881 (100.0%) 0 ( 0.0%) 8881
#-----------------------------------------------------------
# 2776432 ( 99.0%) 27532 ( 1.0%) 2803964
#
#Max overcon = 15 tracks.
#Total overcon = 0.71%.
#Worst layer Gcell overcon rate = 1.38%.
#Cpu time = 00:01:01
#Elapsed time = 00:00:49
#Increased memory = 89.00 (Mb)
#Total memory = 5791.00 (Mb)
#Peak memory = 6201.00 (Mb)
#Using multithreading with 8 threads.
#
#Start Detail Routing...
#start initial detail routing ...
# completing 10% with 59 violations
# elapsed time = 00:00:03, memory = 6074.00 (Mb)
# completing 20% with 122 violations
# elapsed time = 00:00:06, memory = 6106.00 (Mb)
# completing 30% with 234 violations
# elapsed time = 00:00:10, memory = 6151.00 (Mb)
# completing 40% with 329 violations
# elapsed time = 00:00:13, memory = 6112.00 (Mb)
# completing 50% with 473 violations
# elapsed time = 00:00:19, memory = 6110.00 (Mb)
# completing 60% with 610 violations
# elapsed time = 00:00:24, memory = 6088.00 (Mb)
# completing 70% with 718 violations
# elapsed time = 00:00:29, memory = 6086.00 (Mb)
# completing 80% with 763 violations
# elapsed time = 00:00:32, memory = 6125.00 (Mb)
# completing 90% with 854 violations
# elapsed time = 00:00:36, memory = 6141.00 (Mb)
# completing 100% with 1022 violations
# elapsed time = 00:00:51, memory = 5994.00 (Mb)
# ECO: 0.0% of the total area was rechecked for DRC, and 7.0% required routing.
# number of violations = 1022
#3.8% of the total area is being checked for drcs
#3.8% of the total area was checked
# number of violations = 2331
#cpu time = 00:05:26, elapsed time = 00:01:14, memory = 5944.00 (Mb)
#start 1st optimization iteration ...
# number of violations = 155
#cpu time = 00:01:09, elapsed time = 00:00:18, memory = 5933.00 (Mb)
#start 2nd optimization iteration ...
# number of violations = 38
#cpu time = 00:00:04, elapsed time = 00:00:02, memory = 5933.00 (Mb)
#start 3rd optimization iteration ...
# number of violations = 2
#cpu time = 00:00:02, elapsed time = 00:00:01, memory = 5933.00 (Mb)
#start 4th optimization iteration ...
# number of violations = 0
#cpu time = 00:00:01, elapsed time = 00:00:01, memory = 5933.00 (Mb)
#Complete Detail Routing.
#Total number of nets with non-default rule or having extra spacing = 1576
#Total wire length = 16458310 um.
#Total half perimeter of net bounding box = 14227415 um.
#Total wire length on LAYER ME1 = 180875 um.
#Total wire length on LAYER ME2 = 2602002 um.
#Total wire length on LAYER ME3 = 3565650 um.
#Total wire length on LAYER ME4 = 3074252 um.
#Total wire length on LAYER ME5 = 3628043 um.
#Total wire length on LAYER ME6 = 2727184 um.
#Total wire length on LAYER ME7 = 509332 um.
#Total wire length on LAYER ME8 = 170971 um.
#Total number of vias = 2809487
#Total number of multi-cut vias = 27521 ( 1.0%)
#Total number of single cut vias = 2781966 ( 99.0%)
#Up-Via Summary (total 2809487):
# single-cut multi-cut Total
#-----------------------------------------------------------
# Metal 1 996852 (100.0%) 0 ( 0.0%) 996852
# Metal 2 1064442 (100.0%) 0 ( 0.0%) 1064442
# Metal 3 384626 (100.0%) 0 ( 0.0%) 384626
# Metal 4 201694 (100.0%) 49 ( 0.0%) 201743
# Metal 5 125469 (100.0%) 0 ( 0.0%) 125469
# Metal 6 0 ( 0.0%) 27472 (100.0%) 27472
# Metal 7 8883 (100.0%) 0 ( 0.0%) 8883
#-----------------------------------------------------------
# 2781966 ( 99.0%) 27521 ( 1.0%) 2809487
#
#Total number of DRC violations = 0
#Total number of violations on LAYER ME1 = 0
#Total number of violations on LAYER ME2 = 0
#Total number of violations on LAYER ME3 = 0
#Total number of violations on LAYER ME4 = 0
#Total number of violations on LAYER ME5 = 0
#Total number of violations on LAYER ME6 = 0
#Total number of violations on LAYER ME7 = 0
#Total number of violations on LAYER ME8 = 0
#
#start routing for process antenna violation fix ...
#cpu time = 00:00:17, elapsed time = 00:00:17, memory = 5907.00 (Mb)
#
#Total number of nets with non-default rule or having extra spacing = 1576
#Total wire length = 16458310 um.
#Total half perimeter of net bounding box = 14227415 um.
#Total wire length on LAYER ME1 = 180875 um.
#Total wire length on LAYER ME2 = 2602002 um.
#Total wire length on LAYER ME3 = 3565650 um.
#Total wire length on LAYER ME4 = 3074252 um.
#Total wire length on LAYER ME5 = 3628043 um.
#Total wire length on LAYER ME6 = 2727184 um.
#Total wire length on LAYER ME7 = 509332 um.
#Total wire length on LAYER ME8 = 170971 um.
#Total number of vias = 2809487
#Total number of multi-cut vias = 27521 ( 1.0%)
#Total number of single cut vias = 2781966 ( 99.0%)
#Up-Via Summary (total 2809487):
# single-cut multi-cut Total
#-----------------------------------------------------------
# Metal 1 996852 (100.0%) 0 ( 0.0%) 996852
# Metal 2 1064442 (100.0%) 0 ( 0.0%) 1064442
# Metal 3 384626 (100.0%) 0 ( 0.0%) 384626
# Metal 4 201694 (100.0%) 49 ( 0.0%) 201743
# Metal 5 125469 (100.0%) 0 ( 0.0%) 125469
# Metal 6 0 ( 0.0%) 27472 (100.0%) 27472
# Metal 7 8883 (100.0%) 0 ( 0.0%) 8883
#-----------------------------------------------------------
# 2781966 ( 99.0%) 27521 ( 1.0%) 2809487
#
#Total number of DRC violations = 0
#Total number of net violated process antenna rule = 0
#Total number of violations on LAYER ME1 = 0
#Total number of violations on LAYER ME2 = 0
#Total number of violations on LAYER ME3 = 0
#Total number of violations on LAYER ME4 = 0
#Total number of violations on LAYER ME5 = 0
#Total number of violations on LAYER ME6 = 0
#Total number of violations on LAYER ME7 = 0
#Total number of violations on LAYER ME8 = 0
#
#detailRoute Statistics:
#Cpu time = 00:07:21
#Elapsed time = 00:02:15
#Increased memory = 111.00 (Mb)
#Total memory = 5902.00 (Mb)
#Peak memory = 6220.00 (Mb)
#Updating routing design signature
#Created 3310 library cell signatures
#Created 283804 NETS and 0 SPECIALNETS signatures
#Created 310890 instance signatures
#
#globalDetailRoute statistics:
#Cpu time = 00:08:55
#Elapsed time = 00:03:36
#Increased memory = -653.00 (Mb)
#Total memory = 5116.00 (Mb)
#Peak memory = 6220.00 (Mb)
#Number of warnings = 80
#Total number of warnings = 264
#Number of fails = 0
#Total number of fails = 0
#Complete globalDetailRoute on Fri Sep 30 09:20:09 2011
#
**optDesign ... cpu = 0:53:21, real = 0:48:06, mem = 5116.2M **
-routeWithEco false # bool, default=false, user setting
-routeSelectedNetOnly false # bool, default=false
-routeWithTimingDriven true # bool, default=false, user setting
-routeWithSiDriven false # bool, default=false, user setting
-drouteStartIteration 0 # int, default=0, user setting
Extraction called for design 'shabziger_chip' of instances=310889 and nets=283804 using extraction engine 'postRoute' at effort level 'low' .
Detail RC Extraction called for design shabziger_chip.
RC Extraction called in multi-corner(2) mode.
Process corner(s) are loaded.
Corner: rc_worst
Corner: rc_best
extractDetailRC Option : -outfile ../tmp/shabziger_chip_wukc1u_9079.rcdb.d -maxResLength 200 -extended
RC Mode: Detail [Extended CapTable, RC Table Resistances]
RC Corner Indexes 0 1
Capacitance Scaling Factor : 1.00000 1.00000
Coupling Cap. Scaling Factor : 1.00000 1.00000
Resistance Scaling Factor : 1.00000 1.00000
Clock Cap. Scaling Factor : 1.00000 1.00000
Clock Res. Scaling Factor : 1.00000 1.00000
Shrink Factor : 1.00000
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Checking LVS Completed (CPU Time= 0:00:01.3 MEM= 5116.8M)
Creating parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' in memory efficient access mode for storing RC.
Extracted 10% (CPU Time= 0:00:08.8 MEM= 5376.9M)
Extracted 20% (CPU Time= 0:00:16.3 MEM= 5376.9M)
Extracted 30% (CPU Time= 0:00:20.6 MEM= 5376.9M)
Extracted 40.0001% (CPU Time= 0:00:28.0 MEM= 5376.9M)
Extracted 50.0001% (CPU Time= 0:00:36.3 MEM= 5376.9M)
Extracted 60.0001% (CPU Time= 0:00:42.1 MEM= 5376.9M)
Extracted 70.0001% (CPU Time= 0:00:52.0 MEM= 5376.9M)
Extracted 80.0001% (CPU Time= 0:01:01 MEM= 5376.9M)
Extracted 90.0001% (CPU Time= 0:01:07 MEM= 5376.9M)
Extracted 100% (CPU Time= 0:01:21 MEM= 5376.9M)
Nr. Extracted Resistors : 5597909
Nr. Extracted Ground Cap. : 5876804
Nr. Extracted Coupling Cap. : 0
Opening parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' for reading.
Detail RC Extraction DONE (CPU Time: 0:01:24 Real Time: 0:01:29 MEM: 5116.195M)
Using new Cte TW Api base...#################################################################################
# Design Stage: PostRoute
# Design Mode: 65nm
# Analysis Mode: MMMC non-OCV
# Extraction Mode: detail/spef
# Delay Calculation Options: engine=signalStorm signOff=true SIAware=false(opt)
# Switching Delay Calculation Engine to signalStorm
#################################################################################
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.5, MEM = 5144.0M, InitMEM = 5144.0M)
Start delay calculation using Signal Storm (mem=5144.020M)...
delayCal using detail RC...
Opening parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' for reading.
RC Database In Completed (CPU Time= 0:00:01.5 MEM= 5218.3M)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Delay calculation completed. (cpu=0:01:16 real=0:01:16 mem=5620.305M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.6, MEM = 5620.3M, InitMEM = 5620.3M)
Start delay calculation using Signal Storm (mem=5620.305M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:41.2 real=0:00:41.0 mem=5620.305M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.6, MEM = 5620.3M, InitMEM = 5620.3M)
Start delay calculation using Signal Storm (mem=5620.305M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:41.6 real=0:00:42.0 mem=5620.305M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.6, MEM = 5620.3M, InitMEM = 5620.3M)
Start delay calculation using Signal Storm (mem=5620.305M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:41.9 real=0:00:42.0 mem=5620.305M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.6, MEM = 5620.3M, InitMEM = 5620.3M)
Start delay calculation using Signal Storm (mem=5620.305M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:41.8 real=0:00:42.0 mem=5620.305M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.7, MEM = 5620.3M, InitMEM = 5620.3M)
Start delay calculation using Signal Storm (mem=5620.305M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:41.8 real=0:00:42.0 mem=5620.305M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.8, MEM = 5620.3M, InitMEM = 5620.3M)
Start delay calculation using Signal Storm (mem=5620.305M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:42.3 real=0:00:42.0 mem=5620.305M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.6, MEM = 5620.3M, InitMEM = 5620.3M)
Start delay calculation using Signal Storm (mem=5620.305M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:43.1 real=0:00:43.0 mem=5620.305M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.6, MEM = 5620.3M, InitMEM = 5620.3M)
Start delay calculation using Signal Storm (mem=5620.305M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:45.4 real=0:00:45.0 mem=5620.305M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.6, MEM = 5620.3M, InitMEM = 5620.3M)
Start delay calculation using Signal Storm (mem=5620.305M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:44.4 real=0:00:44.0 mem=5620.305M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.7, MEM = 5620.3M, InitMEM = 5620.3M)
Start delay calculation using Signal Storm (mem=5620.305M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:45.6 real=0:00:46.0 mem=5620.305M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.6, MEM = 5620.3M, InitMEM = 5620.3M)
Start delay calculation using Signal Storm (mem=5620.305M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:44.0 real=0:00:45.0 mem=5620.305M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.5, MEM = 5620.3M, InitMEM = 5620.3M)
Start delay calculation using Signal Storm (mem=5620.305M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:47.0 real=0:00:47.0 mem=5621.309M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.6, MEM = 5621.3M, InitMEM = 5621.3M)
Start delay calculation using Signal Storm (mem=5621.309M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:44.9 real=0:00:45.0 mem=5621.309M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.6, MEM = 5621.3M, InitMEM = 5621.3M)
Start delay calculation using Signal Storm (mem=5621.309M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:44.9 real=0:00:45.0 mem=5621.309M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.7, MEM = 5621.3M, InitMEM = 5621.3M)
Start delay calculation using Signal Storm (mem=5621.309M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:44.6 real=0:00:45.0 mem=5621.309M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.7, MEM = 5621.3M, InitMEM = 5621.3M)
Start delay calculation using Signal Storm (mem=5621.309M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:57.6 real=0:00:57.0 mem=5621.309M 0)
*** CDM Built up (cpu=0:14:23 real=0:14:22 mem= 5621.3M) ***
*** Timing NOT met, worst failing slack is -0.105
*** Check timing (0:16:32)
Clearing footprints for all libraries
Loading footprints for all corners
***** CTE Mode is Operational *****
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
Info: 40 io nets excluded
Info: 567 clock nets excluded from IPO operation.
*** Starting new resizing ***
density before resizing = 60.377%
start postIPO sizing
7 instances have been resized
*summary: 7 instances changed cell type
density after resizing = 60.377%
*** Finish new resizing (cpu=0:00:45.5 mem=5979.9M) ***
*** Starting resizing for timing improvement ***
32 instances have been resized
density change = 0.000%
*summary: 32 instances changed cell type
*** Finish resizing for timing improvement (cpu=0:00:19.1 mem=5986.0M) ***
*** Starting sequential cell resizing ***
density before resizing = 60.377%
*summary: 116 instances changed cell type
density after resizing = 60.377%
*** Finish sequential cell resizing (cpu=0:00:35.7 mem=5983.0M) ***
Instances Resized for DRV : 0
Instances Resized for Timing: 155
Total Instances Resized : 155
Current TNS: -55.376 Prev TNS: -56.333
Current WNS: -0.105 Prev WNS: -0.105
Restoring original footprint information
Clearing footprints for all libraries
Loading footprints for all corners
Latch borrow mode reset to max_borrow
Reported timing to dir timingReports_final
**optDesign ... cpu = 1:15:18, real = 1:10:09, mem = 5316.1M **
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
optDesign Final Summary
------------------------------------------------------------
+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| -0.105 | -0.105 | 0.502 | 0.322 | 18.541 | 15.615 |
| TNS (ns):| -55.351 | -55.351 | 0.000 | 0.000 | 0.000 | 0.000 |
| Violating Paths:| 1602 | 1602 | 0 | 0 | 0 | 0 |
| All Paths:| 85005 | 46605 | 63302 | 19 | 2 | 15 |
+--------------------+---------+---------+---------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 1 (5) | -0.001 | 1 (5) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 60.377%
------------------------------------------------------------
**optDesign ... cpu = 1:32:15, real = 1:26:03, mem = 5625.6M **
**INFO : removing temp dont-use cells (LVT only flow version : 4)
Deleting the dont_use list
*** Finished optDesign ***
Opening parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' for reading.
Closing parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d'. 9123161 times net's RC data read were performed.
RC Database In Completed (CPU Time= 0:00:01.8 MEM= 5518.1M)
timeDesign -expandedViews -reportOnly -outDir timingReports_final -prefix shabziger.postrouteopt2.expV
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
timeDesign Summary
------------------------------------------------------------
+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| -0.105 | -0.105 | 0.502 | 0.322 | 18.541 | 15.615 |
| TNS (ns):| -55.351 | -55.351 | 0.000 | 0.000 | 0.000 | 0.000 |
| Violating Paths:| 1602 | 1602 | 0 | 0 | 0 | 0 |
| All Paths:| 85005 | 46605 | 63302 | 19 | 2 | 15 |
+--------------------+---------+---------+---------+---------+---------+---------+
|dummy_slow_view | 7.872 | 7.872 | 9.048 | 8.722 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5131 | 2517 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_blake_slow_view| 0.035 | 0.035 | 3.897 | 3.722 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 8290 | 4385 | 3887 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_groestl_slow_view
| | -0.061 | -0.061 | 2.648 | 2.322 | N/A | N/A |
| | -1.494 | -1.494 | 0.000 | 0.000 | N/A | N/A |
| | 70 | 70 | 0 | 0 | N/A | N/A |
| | 8236 | 4070 | 4148 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_jh_slow_view | -0.024 | -0.024 | 2.048 | 1.722 | N/A | N/A |
| | -0.028 | -0.028 | 0.000 | 0.000 | N/A | N/A |
| | 2 | 2 | 0 | 0 | N/A | N/A |
| | 8801 | 4640 | 4143 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_keccak_slow_view
| | -0.060 | -0.060 | 0.726 | 0.722 | N/A | N/A |
| | -0.935 | -0.935 | 0.000 | 0.000 | N/A | N/A |
| | 56 | 56 | 0 | 0 | N/A | N/A |
| | 8346 | 4125 | 4203 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_sha2_slow_view | 0.105 | 0.105 | 2.497 | 2.222 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 7204 | 3554 | 3632 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_skein_slow_view| -0.068 | -0.068 | 1.598 | 1.522 | N/A | N/A |
| | -2.152 | -2.152 | 0.000 | 0.000 | N/A | N/A |
| | 75 | 75 | 0 | 0 | N/A | N/A |
| | 9002 | 4517 | 4467 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_blake_slow_view | -0.068 | -0.068 | 2.948 | 2.622 | N/A | N/A |
| | -3.999 | -3.999 | 0.000 | 0.000 | N/A | N/A |
| | 103 | 103 | 0 | 0 | N/A | N/A |
| | 9724 | 5498 | 4208 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_groestl_slow_view
| | -0.091 | -0.091 | 1.041 | 0.822 | N/A | N/A |
| | -36.484 | -36.484 | 0.000 | 0.000 | N/A | N/A |
| | 843 | 843 | 0 | 0 | N/A | N/A |
| | 9252 | 5088 | 4146 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_jh_slow_view | -0.059 | -0.059 | 0.648 | 0.322 | N/A | N/A |
| | -1.817 | -1.817 | 0.000 | 0.000 | N/A | N/A |
| | 106 | 106 | 0 | 0 | N/A | N/A |
| | 10269 | 5853 | 4398 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_keccak_slow_view| -0.105 | -0.105 | 0.648 | 0.322 | N/A | N/A |
| | -6.848 | -6.848 | 0.000 | 0.000 | N/A | N/A |
| | 302 | 302 | 0 | 0 | N/A | N/A |
| | 9926 | 5702 | 4206 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_sha2_slow_view | -0.060 | -0.060 | 0.502 | 0.522 | N/A | N/A |
| | -0.360 | -0.360 | 0.000 | 0.000 | N/A | N/A |
| | 18 | 18 | 0 | 0 | N/A | N/A |
| | 7986 | 4238 | 3730 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_skein_slow_view | -0.066 | -0.066 | 2.614 | 4.222 | N/A | N/A |
| | -1.351 | -1.351 | 0.000 | 0.000 | N/A | N/A |
| | 41 | 41 | 0 | 0 | N/A | N/A |
| | 10156 | 5551 | 4587 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ram1_slow_view | 5.156 | 5.156 | 9.048 | 8.722 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5237 | 2623 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ram2_slow_view | 4.908 | 4.908 | 9.048 | 8.722 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5237 | 2623 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ram3_slow_view | 3.366 | 3.366 | 9.048 | 8.722 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5240 | 2626 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|test_slow_view | 13.339 | 13.339 | 13.779 | 18.521 | 18.541 | 15.615 |
| | 0.000 | 0.000 | 0.000 | 0.000 | 0.000 | 0.000 |
| | 0 | 0 | 0 | 0 | 0 | 0 |
| | 85005 | 46605 | 63302 | 19 | 2 | 15 |
+--------------------+---------+---------+---------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 1 (5) | -0.001 | 1 (5) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 60.377%
------------------------------------------------------------
Reported timing to dir timingReports_final
Total CPU time: 286.6 sec
Total Real time: 230.0 sec
Total Memory Usage: 5518.136719 Mbytes
saveDesign save/chip_shabziger_final2.enc
Redoing specifyClockTree ...
Checking spec file integrity...
Writing Netlist "save/chip_shabziger_final2.enc.dat/shabziger_chip.v.gz" ...
Saving clock tree spec file 'save/chip_shabziger_final2.enc.dat/shabziger_chip.ctstch' ...
Saving configuration ...
Saving preference file save/chip_shabziger_final2.enc.dat/enc.pref.tcl ...
Saving floorplan ...
Saving Drc markers ...
... No Drc file written since there is no markers found.
Saving placement ...
*** Completed savePlace (cpu=0:00:00.4 real=0:00:01.0 mem=5489.9M) ***
Saving route ...
*** Completed saveRoute (cpu=0:00:05.5 real=0:00:14.0 mem=5489.9M) ***
Writing DEF file 'save/chip_shabziger_final2.enc.dat/shabziger_chip.def.gz', current time is Fri Sep 30 10:05:40 2011 ...
unitPerMicron=1000, dbgMicronPerDBU=0.001000, unitPerDBU=1.000000
DEF file 'save/chip_shabziger_final2.enc.dat/shabziger_chip.def.gz' is written, current time is Fri Sep 30 10:05:41 2011 ...
*** Completed saveYieldMap (cpu=: 0:00:00.0 real=0:00:00.0 mem=: 0.000M) ***
setOptMode -setupTargetSlack 0.05
*info: Setting setup target slack to 0.050
*info: Hold target slack is 0.000
optDesign -postroute -outDir timingReports_final -prefix shabziger.postrouteopt3
Disable merging buffers from different footprints for postRoute code for non-MSV designs
**WARN: (ENCOPT-6055): The following cells have a dont_touch property but without being dont_use.
Such configuration can impact the timing closure because they can be inserted in the netlist but never transformed again.
It is recommended that you apply a dont_use attribute on them.
Cell SYKA65_2048X32X1CM8 is dont_touch but not dont_use
Cell SHKA65_2048X32X1CM4 is dont_touch but not dont_use
Cell SHKA65_16384X32X1CM16 is dont_touch but not dont_use
...
Reporting only the 20 first cells found...
COE opt is not supported in non AAE mode. Reverting to non COE postroute flow
**optDesign ... cpu = 0:00:00, real = 0:00:00, mem = 5489.9M **
#Created 3310 library cell signatures
#Created 283804 NETS and 0 SPECIALNETS signatures
#Created 310890 instance signatures
Begin checking placement ... (start mem=5489.9M, init mem=5496.4M)
*info: Placed = 273398
*info: Unplaced = 0
Placement Density:60.38%(1138831/1886211)
Finished checkPlace (cpu: total=0:00:03.3, vio checks=0:00:00.3; mem=5489.9M)
Setting latch borrow mode to budget during optimization.
setExtractRCMode -coupled false
**WARN: (ENCEXT-3493): Extraction mode changed by calling extraction setup command 'setExtractRCMode'. Therefore, parasitic data in the tool generated as per previous mode is deleted. Call of extractRC/spefIn will generate/bring parasitic data in the tool as per current mode.
*** optDesign -postRoute ***
DRC Margin: user margin 0.0; extra margin 0
Setup Target Slack: user slack 0.05
Hold Target Slack: user slack 0.0
*info: Setting setup target slack to 0.050
*info: Hold target slack is 0.000
**INFO : Adding temp dont-use cells (LVT only flow version : 4)
Creating information for LVT Only Flow
Num of Buffers : 123
Num of Inverters : 105
Num of VTs : 3
Executing LVT Only Same Size Flow (setting 4)
*Info* Num dontuse cells 311
*Info* Num dontuse cells 2259
Extraction called for design 'shabziger_chip' of instances=310889 and nets=283804 using extraction engine 'postRoute' at effort level 'low' .
Detail RC Extraction called for design shabziger_chip.
RC Extraction called in multi-corner(2) mode.
Process corner(s) are loaded.
Corner: rc_worst
Corner: rc_best
extractDetailRC Option : -outfile ../tmp/shabziger_chip_wukc1u_9079.rcdb.d -maxResLength 200 -extended
RC Mode: Detail [Extended CapTable, RC Table Resistances]
RC Corner Indexes 0 1
Capacitance Scaling Factor : 1.00000 1.00000
Coupling Cap. Scaling Factor : 1.00000 1.00000
Resistance Scaling Factor : 1.00000 1.00000
Clock Cap. Scaling Factor : 1.00000 1.00000
Clock Res. Scaling Factor : 1.00000 1.00000
Shrink Factor : 1.00000
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Checking LVS Completed (CPU Time= 0:00:01.6 MEM= 5114.5M)
Closing parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d'. 101559 times net's RC data read were performed.
Creating parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' in memory efficient access mode for storing RC.
Extracted 10% (CPU Time= 0:00:12.1 MEM= 5342.2M)
Extracted 20% (CPU Time= 0:00:22.8 MEM= 5342.2M)
Extracted 30% (CPU Time= 0:00:29.8 MEM= 5342.2M)
Extracted 40.0001% (CPU Time= 0:00:40.2 MEM= 5342.2M)
Extracted 50.0001% (CPU Time= 0:00:52.0 MEM= 5342.2M)
Extracted 60.0001% (CPU Time= 0:01:01 MEM= 5342.2M)
Extracted 70.0001% (CPU Time= 0:01:15 MEM= 5342.2M)
Extracted 80.0001% (CPU Time= 0:01:27 MEM= 5342.2M)
Extracted 90.0001% (CPU Time= 0:01:36 MEM= 5342.2M)
Extracted 100% (CPU Time= 0:01:54 MEM= 5342.2M)
Nr. Extracted Resistors : 5597909
Nr. Extracted Ground Cap. : 5876804
Nr. Extracted Coupling Cap. : 0
Opening parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' for reading.
Detail RC Extraction DONE (CPU Time: 0:01:58 Real Time: 0:02:02 MEM: 5094.578M)
Using new Cte TW Api base...#################################################################################
# Design Stage: PostRoute
# Design Mode: 65nm
# Analysis Mode: MMMC non-OCV
# Extraction Mode: detail/spef
# Delay Calculation Options: engine=signalStorm signOff=true SIAware=false(opt)
# Switching Delay Calculation Engine to signalStorm
#################################################################################
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:02.1, MEM = 5138.1M, InitMEM = 5138.6M)
Start delay calculation using Signal Storm (mem=5138.148M)...
delayCal using detail RC...
Opening parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' for reading.
RC Database In Completed (CPU Time= 0:00:01.8 MEM= 5180.1M)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Delay calculation completed. (cpu=0:01:20 real=0:01:21 mem=5618.168M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.6, MEM = 5618.2M, InitMEM = 5618.2M)
Start delay calculation using Signal Storm (mem=5618.168M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:39.5 real=0:00:39.0 mem=5618.168M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.5, MEM = 5618.2M, InitMEM = 5618.2M)
Start delay calculation using Signal Storm (mem=5618.168M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:39.8 real=0:00:40.0 mem=5618.168M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.7, MEM = 5618.2M, InitMEM = 5618.2M)
Start delay calculation using Signal Storm (mem=5618.168M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:40.5 real=0:00:41.0 mem=5618.168M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.6, MEM = 5618.2M, InitMEM = 5618.2M)
Start delay calculation using Signal Storm (mem=5618.168M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:40.2 real=0:00:40.0 mem=5618.168M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.5, MEM = 5618.2M, InitMEM = 5618.2M)
Start delay calculation using Signal Storm (mem=5618.168M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:39.8 real=0:00:40.0 mem=5618.168M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.5, MEM = 5618.2M, InitMEM = 5618.2M)
Start delay calculation using Signal Storm (mem=5618.168M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:40.7 real=0:00:41.0 mem=5618.168M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.5, MEM = 5618.2M, InitMEM = 5618.2M)
Start delay calculation using Signal Storm (mem=5618.168M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:41.1 real=0:00:41.0 mem=5618.168M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.6, MEM = 5618.2M, InitMEM = 5618.2M)
Start delay calculation using Signal Storm (mem=5618.168M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:42.9 real=0:00:43.0 mem=5618.168M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.6, MEM = 5618.2M, InitMEM = 5618.2M)
Start delay calculation using Signal Storm (mem=5618.168M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:41.8 real=0:00:41.0 mem=5618.168M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.6, MEM = 5618.2M, InitMEM = 5618.2M)
Start delay calculation using Signal Storm (mem=5618.168M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:43.2 real=0:00:43.0 mem=5618.168M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.6, MEM = 5618.2M, InitMEM = 5618.2M)
Start delay calculation using Signal Storm (mem=5618.168M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:42.6 real=0:00:43.0 mem=5618.168M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.6, MEM = 5618.2M, InitMEM = 5618.2M)
Start delay calculation using Signal Storm (mem=5618.168M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:45.1 real=0:00:46.0 mem=5618.168M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.5, MEM = 5618.2M, InitMEM = 5618.2M)
Start delay calculation using Signal Storm (mem=5618.168M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:42.4 real=0:00:43.0 mem=5618.168M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.7, MEM = 5618.2M, InitMEM = 5618.2M)
Start delay calculation using Signal Storm (mem=5618.168M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:42.3 real=0:00:43.0 mem=5618.168M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.6, MEM = 5618.2M, InitMEM = 5618.2M)
Start delay calculation using Signal Storm (mem=5618.168M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:42.6 real=0:00:43.0 mem=5618.168M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.6, MEM = 5618.2M, InitMEM = 5618.2M)
Start delay calculation using Signal Storm (mem=5618.168M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:55.0 real=0:00:55.0 mem=5618.168M 0)
*** CDM Built up (cpu=0:14:16 real=0:14:18 mem= 5618.2M) ***
-holdSdfFile {} # string, default=""
-holdSdfScript {} # string, default="", private
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
Initial Summary
------------------------------------------------------------
+--------------------+---------+
| Setup mode | all |
+--------------------+---------+
| WNS (ns):| -0.105 |
| TNS (ns):| -55.351 |
| Violating Paths:| 1602 |
| All Paths:| 85005 |
+--------------------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 1 (5) | -0.001 | 1 (5) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 60.377%
------------------------------------------------------------
**optDesign ... cpu = 0:18:54, real = 0:18:59, mem = 5950.8M **
*info: Start fixing DRV (Mem = 5987.68M) ...
*info: Options = -postRoute -maxCap -maxTran -noMaxFanout -noSensitivity -backward -maxIter 1
*info: Start fixing DRV iteration 1 ...
*** Starting dpFixDRCViolation (5987.7M)
*info: 40 io nets excluded
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
*info: 567 clock nets excluded
*info: 4 special nets excluded.
*info: 2406 no-driver nets excluded.
*info: 21 multi-driver nets excluded.
*info: There are 60 candidate Buffer cells
*info: There are 52 candidate Inverter cells
Initializing placement sections/sites ...
Density before buffering = 0.603766
Start fixing design rules ... (0:00:06.0 6119.3M)
All-RC-Corners-Per-Net-In-Memory is turned ON...
Closing parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d'. 4616152 times net's RC data read were performed.
Opening parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' for reading.
RC Database In Completed (CPU Time= 0:00:02.0 MEM= 6027.9M)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Topological Sorting (CPU = 0:00:01.6, MEM = 6045.1M, InitMEM = 6045.1M)
Done fixing design rule (0:01:14 5970.2M)
Summary:
1 buffer added on 1 net (with 0 driver resized)
Density after buffering = 0.603768
Starting refinePlace ...
move report: placeLevelShifters moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Spread Effort: high, post-route mode.
Finished Phase I. CPU Time = 0:00:25.1, Real Time = 0:00:25.0
move report: preRPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: rPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: overall moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 0.00 um
mean (X+Y) = 0.00 um
Total instances moved : 0
*** cpu=0:00:27.8 mem=5892.5M mem(used)=33.1M***
*** Completed dpFixDRCViolation (0:01:46 5859.4M)
End of fixDrcViolation iteration 1.
*** Starting dpFixDRCViolation (5859.4M)
*info: 40 io nets excluded
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
*info: 567 clock nets excluded
*info: 4 special nets excluded.
*info: 2406 no-driver nets excluded.
*info: 21 multi-driver nets excluded.
Start fixing design rules ... (0:00:06.0 5996.9M)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Done fixing design rule (0:01:08 5971.3M)
Summary:
0 buffer added on 0 net (with 0 driver resized)
Density after buffering = 0.603768
*** Completed dpFixDRCViolation (0:01:09 5860.5M)
*info:
*info: Completed fixing DRV (CPU Time = 0:03:23, Mem = 5860.53M).
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
Summary (cpu=3.39min real=3.40min mem=5860.5M)
------------------------------------------------------------
+--------------------+---------+
| Setup mode | all |
+--------------------+---------+
| WNS (ns):| -0.105 |
| TNS (ns):| -55.346 |
| Violating Paths:| 1602 |
| All Paths:| 85005 |
+--------------------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 0 (0) | 0.000 | 0 (0) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 60.377%
------------------------------------------------------------
**optDesign ... cpu = 0:23:16, real = 0:23:21, mem = 5860.5M **
*** Timing NOT met, worst failing slack is -0.105
*** Check timing (0:00:00.9)
*** Timing NOT met, worst failing slack is -0.105
*** Check timing (0:00:00.1)
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
Info: 40 io nets excluded
Info: 567 clock nets excluded from IPO operation.
*** Start Post Route Setup Fixing (cpu=0:00:00.0 mem=5740.7M) ***
Time Engine : CTE
SSTA Mode : off
MMMC mode : on (11 dominant view(s), 6 view(s) pruned)
Incr. DC : on
Incr POM Mode : on
On Demand POM Mode : on
CTE SubNetWork Mode : on
Up Size : on
Down Size : on
Resize FFs : on
Add Buffer : off
Del Buffer : off
Pin Swap : off
Add InvPair : off
LegalLoc GS : off
Speedup GS : off
Crit. Range : 20%
density before = 60.377%
total 280832 net, 39 ipo_ignored
total 951949 term, 78 ipo_ignored
total 289676 comb inst, 37273 fixed, 273 dont_touch, 36923 no_footp
total 21214 seq inst, 18 fixed, 3 dont_touch, 3 no_footp
total 240 footprint(s)
10 footprint(s) with 0 cell(s)
36 footprint(s) with 1 cell(s)
16 footprint(s) with 2 cell(s)
3 footprint(s) with 3 cell(s)
119 footprint(s) with 4 cell(s)
13 footprint(s) with 5 cell(s)
13 footprint(s) with 6 cell(s)
13 footprint(s) with 7 cell(s)
7 footprint(s) with 8 cell(s)
1 footprint(s) with 9 cell(s)
9 footprint(s) with 10+ cell(s)
Estimated WNS = -0.155ns, TNS = -197.120ns (targetSlack +0.050ns) (cpu=0:00:21.6 mem=5808.2M)
Iter 0 ...
Collected 89450 nets for fixing
Evaluate 750(1008) resize, Select 128 cand. (cpu=0:00:49.8 mem=5818.5M)
Commit 20 cand, 19 upSize, 1 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:00:53.0 mem=5821.1M)
Calc. DC (cpu=0:00:53.4 mem=5821.1M) ***
Estimated WNS = -0.127ns, TNS = -194.299ns (targetSlack +0.050ns) (cpu=0:01:05 mem=5821.1M)
Iter 1 ...
Collected 89298 nets for fixing
Evaluate 750(1879) resize, Select 350 cand. (cpu=0:01:40 mem=5823.2M)
Commit 20 cand, 15 upSize, 5 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:01:45 mem=5823.8M)
Calc. DC (cpu=0:01:45 mem=5823.8M) ***
Estimated WNS = -0.123ns, TNS = -194.007ns (targetSlack +0.050ns) (cpu=0:01:56 mem=5823.8M)
Iter 2 ...
Collected 89287 nets for fixing
Evaluate 754(1932) resize, Select 115 cand. (cpu=0:02:31 mem=5826.0M)
Commit 17 cand, 16 upSize, 1 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:02:33 mem=5826.3M)
Calc. DC (cpu=0:02:33 mem=5826.3M) ***
Estimated WNS = -0.122ns, TNS = -193.813ns (targetSlack +0.050ns) (cpu=0:02:44 mem=5826.3M)
Iter 3 ...
Collected 89276 nets for fixing
Evaluate 751(1556) resize, Select 305 cand. (cpu=0:03:12 mem=5827.4M)
Commit 18 cand, 12 upSize, 6 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:03:14 mem=5827.6M)
Calc. DC (cpu=0:03:14 mem=5827.6M) ***
Estimated WNS = -0.121ns, TNS = -193.639ns (targetSlack +0.050ns) (cpu=0:03:25 mem=5827.6M)
Iter 4 ...
Collected 89271 nets for fixing
Evaluate 763(1993) resize, Select 107 cand. (cpu=0:04:00 mem=5829.7M)
Commit 11 cand, 8 upSize, 3 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:04:00 mem=5831.1M)
Calc. DC (cpu=0:04:01 mem=5831.1M) ***
Estimated WNS = -0.120ns, TNS = -193.545ns (targetSlack +0.050ns) (cpu=0:04:12 mem=5831.1M)
Iter 5 ...
Collected 89269 nets for fixing
Evaluate 755(2485) resize, Select 339 cand. (cpu=0:04:51 mem=5833.1M)
Commit 23 cand, 16 upSize, 5 downSize, 2 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:04:54 mem=5833.3M)
Calc. DC (cpu=0:04:54 mem=5833.3M) ***
Estimated WNS = -0.119ns, TNS = -193.483ns (targetSlack +0.050ns) (cpu=0:05:06 mem=5833.3M)
Iter 6 ...
Collected 89265 nets for fixing
Evaluate 765(2884) resize, Select 149 cand. (cpu=0:05:55 mem=5838.6M)
Commit 31 cand, 25 upSize, 6 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:05:58 mem=5839.9M)
Calc. DC (cpu=0:05:59 mem=5839.9M) ***
Estimated WNS = -0.118ns, TNS = -193.145ns (targetSlack +0.050ns) (cpu=0:06:10 mem=5839.9M)
Iter 7 ...
Collected 89218 nets for fixing
Evaluate 753(2845) resize, Select 399 cand. (cpu=0:06:54 mem=5842.0M)
Commit 30 cand, 20 upSize, 9 downSize, 1 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:06:58 mem=5846.4M)
Calc. DC (cpu=0:06:58 mem=5846.4M) ***
Estimated WNS = -0.118ns, TNS = -192.879ns (targetSlack +0.050ns) (cpu=0:07:05 mem=5846.4M)
Iter 8 ...
Collected 89197 nets for fixing
Evaluate 751(2753) resize, Select 134 cand. (cpu=0:07:34 mem=5847.5M)
Commit 18 cand, 14 upSize, 4 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:07:35 mem=5847.6M)
Calc. DC (cpu=0:07:36 mem=5847.6M) ***
Estimated WNS = -0.118ns, TNS = -192.747ns (targetSlack +0.050ns) (cpu=0:07:43 mem=5847.6M)
Iter 9 ...
Collected 89191 nets for fixing
Evaluate 757(2970) resize, Select 379 cand. (cpu=0:08:11 mem=5850.0M)
Commit 27 cand, 14 upSize, 11 downSize, 2 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:08:15 mem=5851.2M)
Calc. DC (cpu=0:08:15 mem=5851.2M) ***
Estimated WNS = -0.118ns, TNS = -192.259ns (targetSlack +0.050ns) (cpu=0:08:22 mem=5851.2M)
Iter 10 ...
Collected 88971 nets for fixing
Evaluate 751(5988) resize, Select 148 cand. (cpu=0:09:26 mem=5853.3M)
Commit 22 cand, 22 upSize, 0 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:09:27 mem=5855.5M)
Calc. DC (cpu=0:09:28 mem=5855.5M) ***
Estimated WNS = -0.117ns, TNS = -192.106ns (targetSlack +0.050ns) (cpu=0:09:34 mem=5855.5M)
Iter 11 ...
Collected 88967 nets for fixing
Evaluate 752(2937) resize, Select 363 cand. (cpu=0:10:02 mem=5857.6M)
Commit 24 cand, 12 upSize, 11 downSize, 1 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:10:05 mem=5858.6M)
Calc. DC (cpu=0:10:06 mem=5858.6M) ***
Estimated WNS = -0.116ns, TNS = -191.876ns (targetSlack +0.050ns) (cpu=0:10:13 mem=5858.6M)
Iter 12 ...
Collected 88929 nets for fixing
Evaluate 750(2748) resize, Select 148 cand. (cpu=0:10:39 mem=5859.7M)
Commit 28 cand, 22 upSize, 4 downSize, 2 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:10:42 mem=5862.9M)
Calc. DC (cpu=0:10:42 mem=5862.9M) ***
Estimated WNS = -0.116ns, TNS = -190.958ns (targetSlack +0.050ns) (cpu=0:10:49 mem=5862.9M)
Iter 13 ...
Collected 88749 nets for fixing
Evaluate 750(2985) resize, Select 374 cand. (cpu=0:11:19 mem=5863.9M)
Commit 30 cand, 19 upSize, 11 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:11:22 mem=5866.2M)
Calc. DC (cpu=0:11:22 mem=5866.2M) ***
Estimated WNS = -0.116ns, TNS = -190.715ns (targetSlack +0.050ns) (cpu=0:11:29 mem=5866.2M)
Iter 14 ...
Collected 88732 nets for fixing
Evaluate 750(6092) resize, Select 140 cand. (cpu=0:12:29 mem=5867.5M)
Commit 20 cand, 19 upSize, 1 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:12:31 mem=5867.6M)
Calc. DC (cpu=0:12:31 mem=5867.6M) ***
Estimated WNS = -0.116ns, TNS = -190.588ns (targetSlack +0.050ns) (cpu=0:12:38 mem=5867.6M)
Calc. DC (cpu=0:12:38 mem=5867.6M) ***
*summary: 339 instances changed cell type
density after = 60.406%
*** Finish Post Route Setup Fixing (cpu=0:12:40 mem=5826.8M) ***
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
Info: 40 io nets excluded
Info: 567 clock nets excluded from IPO operation.
*** Start Post Route Setup Fixing (cpu=0:00:00.0 mem=5826.8M) ***
Time Engine : CTE
SSTA Mode : off
MMMC mode : on (11 dominant view(s), 6 view(s) pruned)
Incr. DC : on
Incr POM Mode : on
On Demand POM Mode : on
CTE SubNetWork Mode : on
Up Size : on
Down Size : on
Resize FFs : on
Add Buffer : on
Del Buffer : on
Pin Swap : off
Add InvPair : off
LegalLoc GS : off
Speedup GS : off
Crit. Range : 20%
density before = 60.406%
total 280832 net, 39 ipo_ignored
total 951949 term, 78 ipo_ignored
total 289676 comb inst, 37273 fixed, 273 dont_touch, 36923 no_footp
total 21214 seq inst, 18 fixed, 3 dont_touch, 3 no_footp
total 240 footprint(s)
10 footprint(s) with 0 cell(s)
36 footprint(s) with 1 cell(s)
16 footprint(s) with 2 cell(s)
3 footprint(s) with 3 cell(s)
119 footprint(s) with 4 cell(s)
13 footprint(s) with 5 cell(s)
13 footprint(s) with 6 cell(s)
13 footprint(s) with 7 cell(s)
7 footprint(s) with 8 cell(s)
1 footprint(s) with 9 cell(s)
9 footprint(s) with 10+ cell(s)
BUFFER FOOTPRINT (BUFM2S) :
CKBUFM1S(s) CKBUFM2S(s) BUFM2S(s) CKBUFM3S(s) BUFM3S(s)
CKBUFM4S(s) BUFM4S(s) BUFM5S(s) CKBUFM6S(s) BUFM6S(s)
CKBUFM8S(s) BUFM8S(s) BUFM10S(s) CKBUFM12S(s) BUFM12S(s)
BUFM14S(s) CKBUFM16S(s) BUFM16S(s) BUFM18S(s) CKBUFM20S(s)
BUFM20S(s) CKBUFM22SA(s) BUFM22SA(s) CKBUFM24S(s) BUFM24S(s)
CKBUFM26SA(s) BUFM26SA(s) CKBUFM32S(s) BUFM32SA(s) CKBUFM40S(s)
BUFM40SA(s) CKBUFM48S(s) BUFM48SA(s) DEL1M1W(s) CKBUFM1W
BUFM2W CKBUFM2W CKBUFM3W(s) BUFM3W(s) CKBUFM4W
BUFM4W DEL1M4W(s) BUFM5W(s) CKBUFM6W BUFM6W
CKBUFM8W BUFM8W BUFM10W CKBUFM12W BUFM12W
BUFM14W CKBUFM16W BUFM16W BUFM18W CKBUFM20W
BUFM20W CKBUFM22WA BUFM22WA CKBUFM24W BUFM24W
CKBUFM26WA BUFM26WA CKBUFM32W BUFM32WA CKBUFM40W
BUFM40WA CKBUFM48W BUFM48WA CKBUFM1R(s) BUFM2R(s)
CKBUFM2R(s) CKBUFM3R(s) BUFM3R(s) CKBUFM4R(s) BUFM4R(s)
DEL1M4R(s) BUFM5R(s) CKBUFM6R(s) BUFM6R(s) CKBUFM8R(s)
BUFM8R(s) BUFM10R(s) CKBUFM12R(s) BUFM12R(s) BUFM14R(s)
CKBUFM16R(s) BUFM16R(s) BUFM18R(s) CKBUFM20R(s) BUFM20R(s)
CKBUFM22RA(s) BUFM22RA(s) CKBUFM24R(s) BUFM24R(s) CKBUFM26RA(s)
BUFM26RA(s) CKBUFM32R(s) BUFM32RA(s) CKBUFM40R(s) BUFM40RA(s)
CKBUFM48R(s) BUFM48RA(s)
DELAY FOOTPRINT (DEL1M1S) :
DEL4M1S DEL3M1S DEL2M1S DEL1M1S DEL4M4S
DEL3M4S DEL2M4S DEL1M4S DEL4M1W DEL3M1W
DEL2M1W DEL4M4W DEL3M4W DEL2M4W DEL4M1R
DEL3M1R DEL2M1R DEL1M1R DEL4M4R DEL3M4R
DEL2M4R
Estimated WNS = -0.116ns, TNS = -190.588ns (targetSlack +0.050ns) (cpu=0:00:14.1 mem=5876.5M)
Iter 0 ...
Collected 88712 nets for fixing
Evaluate 755(1733) resize, Select 145 cand. (cpu=0:00:34.0 mem=5879.5M)
Evaluate 23(2850) addBuf, Select 3 cand. (cpu=0:00:41.8 mem=5916.4M)
Evaluate 101(101) delBuf, Select 4 cand. (cpu=0:00:42.7 mem=5916.4M)
Commit 26 cand, 20 upSize, 1 downSize, 1 sameSize, 2 addBuf, 2 delBuf, 0 pinSwap (cpu=0:00:43.7 mem=5990.5M)
Calc. DC (cpu=0:00:45.2 mem=5990.5M) ***
Estimated WNS = -0.115ns, TNS = -190.471ns (targetSlack +0.050ns) (cpu=0:00:52.1 mem=5990.5M)
Iter 1 ...
Collected 88689 nets for fixing
Evaluate 765(2766) resize, Select 338 cand. (cpu=0:01:20 mem=5992.7M)
Evaluate 40(3744) addBuf, Select 8 cand. (cpu=0:01:32 mem=5992.7M)
Evaluate 101(101) delBuf, Select 0 cand. (cpu=0:01:33 mem=5992.7M)
Commit 36 cand, 22 upSize, 9 downSize, 1 sameSize, 4 addBuf, 0 delBuf, 0 pinSwap (cpu=0:01:35 mem=5996.3M)
Calc. DC (cpu=0:01:36 mem=5996.3M) ***
Estimated WNS = -0.115ns, TNS = -190.179ns (targetSlack +0.050ns) (cpu=0:01:43 mem=5996.3M)
*summary: 54 instances changed cell type
density after = 60.412%
*** Finish Post Route Setup Fixing (cpu=0:01:44 mem=5945.7M) ***
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
*** Timing NOT met, worst failing slack is -0.065
*** Check timing (0:00:00.3)
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
Info: 40 io nets excluded
Info: 567 clock nets excluded from IPO operation.
*** Start Post Route Setup Fixing (cpu=0:00:00.0 mem=5930.5M) ***
Time Engine : CTE
SSTA Mode : off
MMMC mode : on (11 dominant view(s), 6 view(s) pruned)
Incr. DC : on
Incr POM Mode : on
On Demand POM Mode : on
CTE SubNetWork Mode : on
Up Size : on
Down Size : on
Resize FFs : on
Add Buffer : off
Del Buffer : off
Pin Swap : off
Add InvPair : off
LegalLoc GS : off
Speedup GS : off
Crit. Range : 20%
density before = 60.412%
total 280836 net, 39 ipo_ignored
total 951957 term, 78 ipo_ignored
total 289680 comb inst, 37273 fixed, 273 dont_touch, 36923 no_footp
total 21214 seq inst, 18 fixed, 3 dont_touch, 3 no_footp
total 240 footprint(s)
10 footprint(s) with 0 cell(s)
36 footprint(s) with 1 cell(s)
16 footprint(s) with 2 cell(s)
3 footprint(s) with 3 cell(s)
119 footprint(s) with 4 cell(s)
13 footprint(s) with 5 cell(s)
13 footprint(s) with 6 cell(s)
13 footprint(s) with 7 cell(s)
7 footprint(s) with 8 cell(s)
1 footprint(s) with 9 cell(s)
9 footprint(s) with 10+ cell(s)
Estimated WNS = -0.115ns, TNS = -190.179ns (targetSlack +0.050ns) (cpu=0:00:14.2 mem=5995.3M)
Iter 0 ...
Collected 88669 nets for fixing
Evaluate 762(2490) resize, Select 137 cand. (cpu=0:00:38.7 mem=5996.4M)
Commit 22 cand, 20 upSize, 2 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:00:39.7 mem=5996.8M)
Calc. DC (cpu=0:00:40.1 mem=5996.8M) ***
Estimated WNS = -0.115ns, TNS = -190.077ns (targetSlack +0.050ns) (cpu=0:00:47.0 mem=5996.8M)
Iter 1 ...
Collected 88661 nets for fixing
Evaluate 754(2916) resize, Select 310 cand. (cpu=0:01:14 mem=5997.9M)
Commit 25 cand, 16 upSize, 8 downSize, 1 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:01:17 mem=5999.3M)
Calc. DC (cpu=0:01:17 mem=5999.3M) ***
Estimated WNS = -0.115ns, TNS = -189.944ns (targetSlack +0.050ns) (cpu=0:01:24 mem=5999.3M)
Iter 2 ...
Collected 88653 nets for fixing
Evaluate 750(2365) resize, Select 103 cand. (cpu=0:01:52 mem=6000.4M)
Commit 13 cand, 11 upSize, 2 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:01:53 mem=5999.5M)
Calc. DC (cpu=0:01:53 mem=5999.5M) ***
Estimated WNS = -0.115ns, TNS = -189.890ns (targetSlack +0.050ns) (cpu=0:02:00 mem=5999.5M)
Calc. DC (cpu=0:02:00 mem=5999.5M) ***
*summary: 60 instances changed cell type
density after = 60.417%
*** Finish Post Route Setup Fixing (cpu=0:02:01 mem=5933.5M) ***
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
Info: 40 io nets excluded
Info: 567 clock nets excluded from IPO operation.
*** Start Post Route Setup Fixing (cpu=0:00:00.0 mem=5933.5M) ***
Time Engine : CTE
SSTA Mode : off
MMMC mode : on (11 dominant view(s), 6 view(s) pruned)
Incr. DC : on
Incr POM Mode : on
On Demand POM Mode : on
CTE SubNetWork Mode : on
Up Size : on
Down Size : on
Resize FFs : on
Add Buffer : on
Del Buffer : on
Pin Swap : off
Add InvPair : off
LegalLoc GS : off
Speedup GS : off
Crit. Range : 20%
density before = 60.417%
total 280836 net, 39 ipo_ignored
total 951957 term, 78 ipo_ignored
total 289680 comb inst, 37273 fixed, 273 dont_touch, 36923 no_footp
total 21214 seq inst, 18 fixed, 3 dont_touch, 3 no_footp
total 240 footprint(s)
10 footprint(s) with 0 cell(s)
36 footprint(s) with 1 cell(s)
16 footprint(s) with 2 cell(s)
3 footprint(s) with 3 cell(s)
119 footprint(s) with 4 cell(s)
13 footprint(s) with 5 cell(s)
13 footprint(s) with 6 cell(s)
13 footprint(s) with 7 cell(s)
7 footprint(s) with 8 cell(s)
1 footprint(s) with 9 cell(s)
9 footprint(s) with 10+ cell(s)
BUFFER FOOTPRINT (BUFM2S) :
CKBUFM1S(s) CKBUFM2S(s) BUFM2S(s) CKBUFM3S(s) BUFM3S(s)
CKBUFM4S(s) BUFM4S(s) BUFM5S(s) CKBUFM6S(s) BUFM6S(s)
CKBUFM8S(s) BUFM8S(s) BUFM10S(s) CKBUFM12S(s) BUFM12S(s)
BUFM14S(s) CKBUFM16S(s) BUFM16S(s) BUFM18S(s) CKBUFM20S(s)
BUFM20S(s) CKBUFM22SA(s) BUFM22SA(s) CKBUFM24S(s) BUFM24S(s)
CKBUFM26SA(s) BUFM26SA(s) CKBUFM32S(s) BUFM32SA(s) CKBUFM40S(s)
BUFM40SA(s) CKBUFM48S(s) BUFM48SA(s) DEL1M1W(s) CKBUFM1W
BUFM2W CKBUFM2W CKBUFM3W(s) BUFM3W(s) CKBUFM4W
BUFM4W DEL1M4W(s) BUFM5W(s) CKBUFM6W BUFM6W
CKBUFM8W BUFM8W BUFM10W CKBUFM12W BUFM12W
BUFM14W CKBUFM16W BUFM16W BUFM18W CKBUFM20W
BUFM20W CKBUFM22WA BUFM22WA CKBUFM24W BUFM24W
CKBUFM26WA BUFM26WA CKBUFM32W BUFM32WA CKBUFM40W
BUFM40WA CKBUFM48W BUFM48WA CKBUFM1R(s) BUFM2R(s)
CKBUFM2R(s) CKBUFM3R(s) BUFM3R(s) CKBUFM4R(s) BUFM4R(s)
DEL1M4R(s) BUFM5R(s) CKBUFM6R(s) BUFM6R(s) CKBUFM8R(s)
BUFM8R(s) BUFM10R(s) CKBUFM12R(s) BUFM12R(s) BUFM14R(s)
CKBUFM16R(s) BUFM16R(s) BUFM18R(s) CKBUFM20R(s) BUFM20R(s)
CKBUFM22RA(s) BUFM22RA(s) CKBUFM24R(s) BUFM24R(s) CKBUFM26RA(s)
BUFM26RA(s) CKBUFM32R(s) BUFM32RA(s) CKBUFM40R(s) BUFM40RA(s)
CKBUFM48R(s) BUFM48RA(s)
DELAY FOOTPRINT (DEL1M1S) :
DEL4M1S DEL3M1S DEL2M1S DEL1M1S DEL4M4S
DEL3M4S DEL2M4S DEL1M4S DEL4M1W DEL3M1W
DEL2M1W DEL4M4W DEL3M4W DEL2M4W DEL4M1R
DEL3M1R DEL2M1R DEL1M1R DEL4M4R DEL3M4R
DEL2M4R
Estimated WNS = -0.115ns, TNS = -189.890ns (targetSlack +0.050ns) (cpu=0:00:14.1 mem=5998.3M)
Iter 0 ...
Collected 88652 nets for fixing
Evaluate 751(1615) resize, Select 142 cand. (cpu=0:00:32.4 mem=5999.4M)
Evaluate 24(2909) addBuf, Select 3 cand. (cpu=0:00:40.2 mem=6000.4M)
Evaluate 101(101) delBuf, Select 1 cand. (cpu=0:00:41.0 mem=6000.4M)
Commit 15 cand, 13 upSize, 1 downSize, 0 sameSize, 0 addBuf, 1 delBuf, 0 pinSwap (cpu=0:00:41.7 mem=6001.7M)
Calc. DC (cpu=0:00:43.2 mem=6001.7M) ***
Estimated WNS = -0.115ns, TNS = -189.801ns (targetSlack +0.050ns) (cpu=0:00:49.8 mem=6001.7M)
*summary: 14 instances changed cell type
density after = 60.420%
*** Finish Post Route Setup Fixing (cpu=0:00:50.7 mem=5936.6M) ***
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
*** Timing NOT met, worst failing slack is -0.065
*** Check timing (0:00:00.3)
Starting refinePlace ...
Spread Effort: high, post-route mode.
Finished Phase I. CPU Time = 0:00:21.0, Real Time = 0:00:21.0
move report: preRPlace moves 2467 insts, mean move: 0.83 um, max move: 4.80 um
max move on inst (top/i_gmu_groestl/U10741): (229.60, 256.80) --> (230.80, 260.40)
move report: rPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: overall moves 2467 insts, mean move: 0.83 um, max move: 4.80 um
max move on inst (top/i_gmu_groestl/U10741): (229.60, 256.80) --> (230.80, 260.40)
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 4.80 um
inst (top/i_gmu_groestl/U10741) with max move: (229.6, 256.8) -> (230.8, 260.4)
mean (X+Y) = 0.83 um
Total instances moved : 2467
*** cpu=0:00:22.8 mem=5731.3M mem(used)=13.1M***
Total net length = 1.413e+07 (6.600e+06 7.531e+06) (ext = 0.000e+00)
default core: bins with density > 0.75 = 24.6 % ( 1908 / 7744 )
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
Summary (cpu=19.78min real=19.78min mem=5718.2M)
------------------------------------------------------------
+--------------------+---------+
| Setup mode | all |
+--------------------+---------+
| WNS (ns):| -0.065 |
| TNS (ns):| -50.643 |
| Violating Paths:| 1566 |
| All Paths:| 84974 |
+--------------------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 0 (0) | 0.000 | 0 (0) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 60.420%
------------------------------------------------------------
**optDesign ... cpu = 0:44:36, real = 0:44:40, mem = 5984.7M **
*** Timing NOT met, worst failing slack is -0.065
*** Check timing (0:00:00.1)
setClockDomains -fromType register -toType register
**WARN: (ENCCTE-318): Paths not in the reg2reg domain will be added 1000ns slack adjustment
*** Timing NOT met, worst failing slack is -0.065
*** Check timing (0:01:26)
Active setup views: dummy_slow_view ethz_blake_slow_view ethz_groestl_slow_view ethz_jh_slow_view ethz_keccak_slow_view ethz_sha2_slow_view ethz_skein_slow_view gmu_blake_slow_view gmu_groestl_slow_view gmu_jh_slow_view gmu_keccak_slow_view gmu_sha2_slow_view gmu_skein_slow_view ram1_slow_view ram2_slow_view ram3_slow_view test_slow_view
Active hold views: hold_fast_view
-routeWithEco false # bool, default=false, user setting
-routeWithEco true # bool, default=false, user setting
-routeSelectedNetOnly false # bool, default=false
-routeWithTimingDriven true # bool, default=false, user setting
-routeWithTimingDriven false # bool, default=false, user setting
-routeWithSiDriven false # bool, default=false, user setting
-drouteStartIteration 0 # int, default=0, user setting
-drouteStartIteration 0 # int, default=0
globalDetailRoute
#Start globalDetailRoute on Fri Sep 30 10:54:42 2011
#
Closing parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d'. 124280 times net's RC data read were performed.
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_0 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_1 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_2 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_3 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_4 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_5 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_6 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_7 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_8 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_9 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_10 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_11 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_12 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_13 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_14 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_15 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_16 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_17 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_18 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34 Repeated 20 times. Will be suppressed.) Power/Ground pin VSSIO of instance fillperi_N_19 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRDB-733) PIN AlgSelxSI[0] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN AlgSelxSI[1] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN AlgSelxSI[2] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN AlgSelxSI[3] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN ClkDxCI in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN ClkxCI in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN CoreScanEnxTI in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN CoreScanInxTI in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[0] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[10] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[11] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[12] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[13] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[14] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[15] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[1] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[2] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[3] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[4] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733 Repeated 20 times. Will be suppressed.) PIN DataOutxDO[5] in CELL_VIEW shabziger_chip,init does not have physical port
#NanoRoute Version v10.12-s010 NR110720-1815/10_10_USR2-UB
#Loading the last recorded routing design signature
#Created 7 NETS and 0 SPECIALNETS new signatures
#Summary of the placement changes since last routing:
# Number of instances added (including moved) = 2374
# Number of instances deleted (including moved) = 2370
# Number of instances resized = 302
# Number of instances with same cell size swap = 1
# Number of instances with pin swaps = 7
# Total number of placement changes (moved instances are counted twice) = 5046
#Using multithreading with 8 threads.
# ME1 H Track-Pitch = 0.200 Line-2-Via Pitch = 0.185
# ME2 V Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME3 H Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME4 V Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME5 H Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME6 V Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME7 H Track-Pitch = 0.400 Line-2-Via Pitch = 0.400
# ME8 V Track-Pitch = 4.000 Line-2-Via Pitch = 4.000
#Merging special wires using 8 threads...
#WARNING (NRDB-1005) Can not establish connection to PIN A2 at (512.540 547.475) on ME1 for NET top/Core10InxD[59]. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN A2 at (572.940 428.675) on ME1 for NET top/Core10InxD[87]. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN Z at (1272.650 1314.295) on ME1 for NET top/Core13InxD[180]. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN Z at (1203.130 1191.890) on ME1 for NET top/Core13InxD[188]. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN NA at (1193.955 1192.420) on ME1 for NET top/Core13InxD[357]. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (332.295 250.710) on ME1 for NET top/CoreClkxC_10___L4_N1. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (219.910 639.510) on ME1 for NET top/CoreClkxC_10___L4_N13. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (178.095 471.690) on ME1 for NET top/CoreClkxC_10___L4_N15. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (217.495 275.910) on ME1 for NET top/CoreClkxC_10___L4_N19. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (578.430 428.610) on ME1 for NET top/CoreClkxC_10___L4_N23. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (545.430 480.990) on ME1 for NET top/CoreClkxC_10___L4_N25. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (483.230 569.010) on ME1 for NET top/CoreClkxC_10___L4_N29. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (466.315 264.995) on ME1 for NET top/CoreClkxC_10___L4_N3. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (499.655 446.610) on ME1 for NET top/CoreClkxC_10___L4_N30. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (473.030 479.010) on ME1 for NET top/CoreClkxC_10___L4_N30. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (447.255 601.410) on ME1 for NET top/CoreClkxC_10___L4_N9. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (1511.060 1006.590) on ME1 for NET top/CoreClkxC_12___L5_N13. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (1526.055 975.810) on ME1 for NET top/CoreClkxC_12___L5_N14. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (1689.545 1168.590) on ME1 for NET top/CoreClkxC_12___L5_N16. The NET is considered partially routed.
#WARNING (NRDB-1005 Repeated 20 times. Will be suppressed.) Can not establish connection to PIN CK at (1519.740 1256.610) on ME1 for NET top/CoreClkxC_12___L5_N2. The NET is considered partially routed.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_ethz_skein/add_x_264_7_n283 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_blake/datapath_gen/DP_OP_77J1_129_7063_n807 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/FE_OCPN19407_n9487 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/FE_OCPN20785_n11870 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/FE_OCPN22450_n13656 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/FE_OCPN22670_n9749 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/FE_OCPN23287_n25589 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/dp_fx2_256_from_register_244_ are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/dp_fx2_256_rounds_after_shiftrow[297] are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/dp_fx2_256_rounds_after_subbyte[160] are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/dp_fx2_256_to_final_88_ are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/dp_fx2_256_to_reg[232] are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/n10695 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/n12088 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/n12138 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/n1216 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/n12878 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/n13081 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/n13394 are dangling and deleted.
#WARNING (NRDB-874 Repeated 20 times. Will be suppressed.) Some WIRE segments on routed NET top/i_gmu_groestl/n13502 are dangling and deleted.
#6979 routed nets are extracted.
# 5895 (2.08%) extracted nets are partially routed.
#273092 routed nets are imported.
#3737 routed nets are fixed|skipped|trivial (not extracted).
#Total number of nets = 283808.
#Number of eco nets is 5895
#
#Start data preparation...
#Force regenerating Ggrids.
#Auto generating G-grids with size=15 tracks, using layer ME2's pitch = 0.200.
#Using automatically generated G-grids.
#
#Data preparation is done on Fri Sep 30 10:55:12 2011
#
#Analyzing routing resource...
#Routing resource analysis is done on Fri Sep 30 10:55:16 2011
#
# Resource Analysis:
#
# Routing #Avail #Track #Total %Gcell
# Layer Direction Track Blocked Gcell Blocked
# --------------------------------------------------------------
# Metal 1 H 5808 3565 391250 74.27%
# Metal 2 V 5718 3657 391250 43.74%
# Metal 3 H 5885 3489 391250 36.36%
# Metal 4 V 5858 3516 391250 42.89%
# Metal 5 H 7164 2209 391250 22.09%
# Metal 6 V 7101 2273 391250 29.79%
# Metal 7 H 2749 1937 391250 24.29%
# Metal 8 V 239 228 391250 61.74%
# --------------------------------------------------------------
# Total 40525 36.22% 3130000 41.89%
#
# 1568 nets (0.55%) with 1 preferred extra spacing.
# 9 nets (0.00%) with 2 preferred extra spacing.
#
#
#cpu time = 00:00:06, elapsed time = 00:00:06, memory = 6004.00 (Mb)
#
#start global routing iteration 1...
#cpu time = 00:00:04, elapsed time = 00:00:02, memory = 6006.00 (Mb)
#
#start global routing iteration 2...
#cpu time = 00:00:02, elapsed time = 00:00:02, memory = 6026.00 (Mb)
#
#start global routing iteration 3...
#cpu time = 00:00:11, elapsed time = 00:00:06, memory = 6008.00 (Mb)
#
#
# Congestion Analysis: (blocked Gcells are excluded)
#
# OverCon OverCon OverCon OverCon
# #Gcell #Gcell #Gcell #Gcell %Gcell
# Layer (1-3) (4-6) (7-9) (10-13) OverCon
# --------------------------------------------------------------------------
# Metal 1 476(0.32%) 7(0.00%) 0(0.00%) 0(0.00%) (0.33%)
# Metal 2 4404(1.78%) 847(0.34%) 147(0.06%) 31(0.01%) (2.20%)
# Metal 3 2209(0.89%) 352(0.14%) 33(0.01%) 4(0.00%) (1.04%)
# Metal 4 1117(0.44%) 49(0.02%) 1(0.00%) 0(0.00%) (0.46%)
# Metal 5 64(0.02%) 0(0.00%) 0(0.00%) 0(0.00%) (0.02%)
# Metal 6 43(0.01%) 1(0.00%) 0(0.00%) 0(0.00%) (0.01%)
# Metal 7 62(0.02%) 0(0.00%) 0(0.00%) 0(0.00%) (0.02%)
# Metal 8 33(0.02%) 0(0.00%) 0(0.00%) 0(0.00%) (0.02%)
# --------------------------------------------------------------------------
# Total 8408(0.43%) 1256(0.06%) 181(0.01%) 35(0.00%) (0.51%)
#
# The worst congested Gcell overcon (routing demand over resource in number of tracks) = 13
#
#Complete Global Routing.
#Total number of nets with non-default rule or having extra spacing = 1577
#Total wire length = 16459364 um.
#Total half perimeter of net bounding box = 14228523 um.
#Total wire length on LAYER ME1 = 180643 um.
#Total wire length on LAYER ME2 = 2602181 um.
#Total wire length on LAYER ME3 = 3566820 um.
#Total wire length on LAYER ME4 = 3074231 um.
#Total wire length on LAYER ME5 = 3628010 um.
#Total wire length on LAYER ME6 = 2727176 um.
#Total wire length on LAYER ME7 = 509332 um.
#Total wire length on LAYER ME8 = 170971 um.
#Total number of vias = 2808302
#Total number of multi-cut vias = 27521 ( 1.0%)
#Total number of single cut vias = 2780781 ( 99.0%)
#Up-Via Summary (total 2808302):
# single-cut multi-cut Total
#-----------------------------------------------------------
# Metal 1 995993 (100.0%) 0 ( 0.0%) 995993
# Metal 2 1064188 (100.0%) 0 ( 0.0%) 1064188
# Metal 3 384591 (100.0%) 0 ( 0.0%) 384591
# Metal 4 201662 (100.0%) 49 ( 0.0%) 201711
# Metal 5 125464 (100.0%) 0 ( 0.0%) 125464
# Metal 6 0 ( 0.0%) 27472 (100.0%) 27472
# Metal 7 8883 (100.0%) 0 ( 0.0%) 8883
#-----------------------------------------------------------
# 2780781 ( 99.0%) 27521 ( 1.0%) 2808302
#
#Max overcon = 13 tracks.
#Total overcon = 0.51%.
#Worst layer Gcell overcon rate = 1.04%.
#Cpu time = 00:00:40
#Elapsed time = 00:00:32
#Increased memory = 78.00 (Mb)
#Total memory = 5962.00 (Mb)
#Peak memory = 6220.00 (Mb)
#Using multithreading with 8 threads.
#
#Start Detail Routing...
#start initial detail routing ...
# completing 10% with 37 violations
# elapsed time = 00:00:03, memory = 6282.00 (Mb)
# completing 20% with 104 violations
# elapsed time = 00:00:05, memory = 6326.00 (Mb)
# completing 30% with 152 violations
# elapsed time = 00:00:07, memory = 6237.00 (Mb)
# completing 40% with 220 violations
# elapsed time = 00:00:10, memory = 6318.00 (Mb)
# completing 50% with 334 violations
# elapsed time = 00:00:13, memory = 6290.00 (Mb)
# completing 60% with 382 violations
# elapsed time = 00:00:17, memory = 6324.00 (Mb)
# completing 70% with 499 violations
# elapsed time = 00:00:21, memory = 6328.00 (Mb)
# completing 80% with 538 violations
# elapsed time = 00:00:22, memory = 6214.00 (Mb)
# completing 90% with 597 violations
# elapsed time = 00:00:26, memory = 6266.00 (Mb)
# completing 100% with 732 violations
# elapsed time = 00:00:36, memory = 6172.00 (Mb)
# ECO: 0.0% of the total area was rechecked for DRC, and 4.3% required routing.
# number of violations = 732
#2.3% of the total area is being checked for drcs
#2.3% of the total area was checked
# number of violations = 1423
#cpu time = 00:03:32, elapsed time = 00:00:51, memory = 6122.00 (Mb)
#start 1st optimization iteration ...
# number of violations = 108
#cpu time = 00:00:47, elapsed time = 00:00:13, memory = 6115.00 (Mb)
#start 2nd optimization iteration ...
# number of violations = 4
#cpu time = 00:00:03, elapsed time = 00:00:01, memory = 6115.00 (Mb)
#start 3rd optimization iteration ...
# number of violations = 0
#cpu time = 00:00:01, elapsed time = 00:00:01, memory = 6115.00 (Mb)
#Complete Detail Routing.
#Total number of nets with non-default rule or having extra spacing = 1577
#Total wire length = 16459166 um.
#Total half perimeter of net bounding box = 14228523 um.
#Total wire length on LAYER ME1 = 180691 um.
#Total wire length on LAYER ME2 = 2600339 um.
#Total wire length on LAYER ME3 = 3565247 um.
#Total wire length on LAYER ME4 = 3076055 um.
#Total wire length on LAYER ME5 = 3629154 um.
#Total wire length on LAYER ME6 = 2727365 um.
#Total wire length on LAYER ME7 = 509320 um.
#Total wire length on LAYER ME8 = 170996 um.
#Total number of vias = 2811550
#Total number of multi-cut vias = 27510 ( 1.0%)
#Total number of single cut vias = 2784040 ( 99.0%)
#Up-Via Summary (total 2811550):
# single-cut multi-cut Total
#-----------------------------------------------------------
# Metal 1 996911 (100.0%) 0 ( 0.0%) 996911
# Metal 2 1064929 (100.0%) 0 ( 0.0%) 1064929
# Metal 3 385735 (100.0%) 0 ( 0.0%) 385735
# Metal 4 202032 (100.0%) 49 ( 0.0%) 202081
# Metal 5 125549 (100.0%) 0 ( 0.0%) 125549
# Metal 6 0 ( 0.0%) 27461 (100.0%) 27461
# Metal 7 8884 (100.0%) 0 ( 0.0%) 8884
#-----------------------------------------------------------
# 2784040 ( 99.0%) 27510 ( 1.0%) 2811550
#
#Total number of DRC violations = 0
#Total number of violations on LAYER ME1 = 0
#Total number of violations on LAYER ME2 = 0
#Total number of violations on LAYER ME3 = 0
#Total number of violations on LAYER ME4 = 0
#Total number of violations on LAYER ME5 = 0
#Total number of violations on LAYER ME6 = 0
#Total number of violations on LAYER ME7 = 0
#Total number of violations on LAYER ME8 = 0
#
#start routing for process antenna violation fix ...
#cpu time = 00:00:14, elapsed time = 00:00:15, memory = 6085.00 (Mb)
#
#Total number of nets with non-default rule or having extra spacing = 1577
#Total wire length = 16459166 um.
#Total half perimeter of net bounding box = 14228523 um.
#Total wire length on LAYER ME1 = 180691 um.
#Total wire length on LAYER ME2 = 2600339 um.
#Total wire length on LAYER ME3 = 3565247 um.
#Total wire length on LAYER ME4 = 3076055 um.
#Total wire length on LAYER ME5 = 3629154 um.
#Total wire length on LAYER ME6 = 2727365 um.
#Total wire length on LAYER ME7 = 509320 um.
#Total wire length on LAYER ME8 = 170996 um.
#Total number of vias = 2811550
#Total number of multi-cut vias = 27510 ( 1.0%)
#Total number of single cut vias = 2784040 ( 99.0%)
#Up-Via Summary (total 2811550):
# single-cut multi-cut Total
#-----------------------------------------------------------
# Metal 1 996911 (100.0%) 0 ( 0.0%) 996911
# Metal 2 1064929 (100.0%) 0 ( 0.0%) 1064929
# Metal 3 385735 (100.0%) 0 ( 0.0%) 385735
# Metal 4 202032 (100.0%) 49 ( 0.0%) 202081
# Metal 5 125549 (100.0%) 0 ( 0.0%) 125549
# Metal 6 0 ( 0.0%) 27461 (100.0%) 27461
# Metal 7 8884 (100.0%) 0 ( 0.0%) 8884
#-----------------------------------------------------------
# 2784040 ( 99.0%) 27510 ( 1.0%) 2811550
#
#Total number of DRC violations = 0
#Total number of net violated process antenna rule = 0
#Total number of violations on LAYER ME1 = 0
#Total number of violations on LAYER ME2 = 0
#Total number of violations on LAYER ME3 = 0
#Total number of violations on LAYER ME4 = 0
#Total number of violations on LAYER ME5 = 0
#Total number of violations on LAYER ME6 = 0
#Total number of violations on LAYER ME7 = 0
#Total number of violations on LAYER ME8 = 0
#
#detailRoute Statistics:
#Cpu time = 00:04:56
#Elapsed time = 00:01:39
#Increased memory = 117.00 (Mb)
#Total memory = 6079.00 (Mb)
#Peak memory = 6373.00 (Mb)
#Updating routing design signature
#Created 3310 library cell signatures
#Created 283808 NETS and 0 SPECIALNETS signatures
#Created 310894 instance signatures
#
#globalDetailRoute statistics:
#Cpu time = 00:06:00
#Elapsed time = 00:02:35
#Increased memory = -663.00 (Mb)
#Total memory = 5307.00 (Mb)
#Peak memory = 6373.00 (Mb)
#Number of warnings = 80
#Total number of warnings = 344
#Number of fails = 0
#Total number of fails = 0
#Complete globalDetailRoute on Fri Sep 30 10:57:17 2011
#
**optDesign ... cpu = 0:54:38, real = 0:51:18, mem = 5307.4M **
-routeWithEco false # bool, default=false, user setting
-routeSelectedNetOnly false # bool, default=false
-routeWithTimingDriven true # bool, default=false, user setting
-routeWithSiDriven false # bool, default=false, user setting
-drouteStartIteration 0 # int, default=0, user setting
Extraction called for design 'shabziger_chip' of instances=310893 and nets=283808 using extraction engine 'postRoute' at effort level 'low' .
Detail RC Extraction called for design shabziger_chip.
RC Extraction called in multi-corner(2) mode.
Process corner(s) are loaded.
Corner: rc_worst
Corner: rc_best
extractDetailRC Option : -outfile ../tmp/shabziger_chip_wukc1u_9079.rcdb.d -maxResLength 200 -extended
RC Mode: Detail [Extended CapTable, RC Table Resistances]
RC Corner Indexes 0 1
Capacitance Scaling Factor : 1.00000 1.00000
Coupling Cap. Scaling Factor : 1.00000 1.00000
Resistance Scaling Factor : 1.00000 1.00000
Clock Cap. Scaling Factor : 1.00000 1.00000
Clock Res. Scaling Factor : 1.00000 1.00000
Shrink Factor : 1.00000
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Checking LVS Completed (CPU Time= 0:00:01.4 MEM= 5308.3M)
Creating parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' in memory efficient access mode for storing RC.
Extracted 10% (CPU Time= 0:00:08.9 MEM= 5568.4M)
Extracted 20.0001% (CPU Time= 0:00:16.9 MEM= 5568.4M)
Extracted 30.0001% (CPU Time= 0:00:21.5 MEM= 5568.4M)
Extracted 40% (CPU Time= 0:00:28.6 MEM= 5568.4M)
Extracted 50.0001% (CPU Time= 0:00:37.9 MEM= 5568.4M)
Extracted 60.0001% (CPU Time= 0:00:43.9 MEM= 5568.4M)
Extracted 70% (CPU Time= 0:00:53.8 MEM= 5568.4M)
Extracted 80.0001% (CPU Time= 0:01:03 MEM= 5568.4M)
Extracted 90.0001% (CPU Time= 0:01:09 MEM= 5568.4M)
Extracted 100% (CPU Time= 0:01:23 MEM= 5568.4M)
Nr. Extracted Resistors : 5602495
Nr. Extracted Ground Cap. : 5881398
Nr. Extracted Coupling Cap. : 0
Opening parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' for reading.
Detail RC Extraction DONE (CPU Time: 0:01:26 Real Time: 0:01:30 MEM: 5307.414M)
Using new Cte TW Api base...#################################################################################
# Design Stage: PostRoute
# Design Mode: 65nm
# Analysis Mode: MMMC non-OCV
# Extraction Mode: detail/spef
# Delay Calculation Options: engine=signalStorm signOff=true SIAware=false(opt)
# Switching Delay Calculation Engine to signalStorm
#################################################################################
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.5, MEM = 5338.9M, InitMEM = 5338.4M)
Start delay calculation using Signal Storm (mem=5338.875M)...
delayCal using detail RC...
Opening parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' for reading.
RC Database In Completed (CPU Time= 0:00:01.6 MEM= 5413.2M)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Delay calculation completed. (cpu=0:00:52.7 real=0:00:52.0 mem=5815.160M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5815.2M, InitMEM = 5815.2M)
Start delay calculation using Signal Storm (mem=5815.160M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:26.4 real=0:00:27.0 mem=5816.164M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.1, MEM = 5816.2M, InitMEM = 5816.2M)
Start delay calculation using Signal Storm (mem=5816.164M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:26.7 real=0:00:27.0 mem=5816.164M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.1, MEM = 5816.2M, InitMEM = 5816.2M)
Start delay calculation using Signal Storm (mem=5816.164M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:26.9 real=0:00:27.0 mem=5816.164M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.1, MEM = 5816.2M, InitMEM = 5816.2M)
Start delay calculation using Signal Storm (mem=5816.164M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:27.0 real=0:00:27.0 mem=5816.164M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5816.2M, InitMEM = 5816.2M)
Start delay calculation using Signal Storm (mem=5816.164M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:27.0 real=0:00:27.0 mem=5816.164M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.1, MEM = 5816.2M, InitMEM = 5816.2M)
Start delay calculation using Signal Storm (mem=5816.164M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:27.6 real=0:00:28.0 mem=5816.164M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5816.2M, InitMEM = 5816.2M)
Start delay calculation using Signal Storm (mem=5816.164M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:27.8 real=0:00:28.0 mem=5816.164M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5816.2M, InitMEM = 5816.2M)
Start delay calculation using Signal Storm (mem=5816.164M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:29.5 real=0:00:29.0 mem=5816.164M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.1, MEM = 5816.2M, InitMEM = 5816.2M)
Start delay calculation using Signal Storm (mem=5816.164M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:29.2 real=0:00:29.0 mem=5816.164M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.0, MEM = 5816.2M, InitMEM = 5816.2M)
Start delay calculation using Signal Storm (mem=5816.164M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:29.5 real=0:00:29.0 mem=5816.164M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.1, MEM = 5816.2M, InitMEM = 5816.2M)
Start delay calculation using Signal Storm (mem=5816.164M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:28.7 real=0:00:28.0 mem=5816.164M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.1, MEM = 5816.2M, InitMEM = 5816.2M)
Start delay calculation using Signal Storm (mem=5816.164M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:30.9 real=0:00:31.0 mem=5816.164M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.1, MEM = 5816.2M, InitMEM = 5816.2M)
Start delay calculation using Signal Storm (mem=5816.164M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:29.1 real=0:00:29.0 mem=5816.164M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.1, MEM = 5816.2M, InitMEM = 5816.2M)
Start delay calculation using Signal Storm (mem=5816.164M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:29.2 real=0:00:29.0 mem=5816.164M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.1, MEM = 5816.2M, InitMEM = 5816.2M)
Start delay calculation using Signal Storm (mem=5816.164M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:29.0 real=0:00:29.0 mem=5816.164M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.1, MEM = 5816.2M, InitMEM = 5816.2M)
Start delay calculation using Signal Storm (mem=5816.164M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:39.1 real=0:00:39.0 mem=5816.164M 0)
*** CDM Built up (cpu=0:09:42 real=0:09:42 mem= 5816.2M) ***
*** Timing NOT met, worst failing slack is -0.075
*** Check timing (0:10:52)
Clearing footprints for all libraries
Loading footprints for all corners
***** CTE Mode is Operational *****
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
Info: 40 io nets excluded
Info: 567 clock nets excluded from IPO operation.
*** Starting new resizing ***
density before resizing = 60.420%
start postIPO sizing
185 instances have been resized
*summary: 185 instances changed cell type
density after resizing = 60.420%
*** Finish new resizing (cpu=0:00:58.9 mem=6175.8M) ***
*** Starting resizing for timing improvement ***
435 instances have been resized
density change = 0.000%
*summary: 435 instances changed cell type
*** Finish resizing for timing improvement (cpu=0:00:53.4 mem=6183.8M) ***
*** Starting sequential cell resizing ***
density before resizing = 60.420%
*summary: 202 instances changed cell type
density after resizing = 60.420%
*** Finish sequential cell resizing (cpu=0:00:39.2 mem=6181.8M) ***
Instances Resized for DRV : 0
Instances Resized for Timing: 822
Total Instances Resized : 822
Current TNS: -50.968 Prev TNS: -50.968
Current WNS: -0.075 Prev WNS: -0.075
Restoring original footprint information
Clearing footprints for all libraries
Loading footprints for all corners
Latch borrow mode reset to max_borrow
Reported timing to dir timingReports_final
**optDesign ... cpu = 1:10:58, real = 1:07:42, mem = 5513.3M **
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
optDesign Final Summary
------------------------------------------------------------
+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| -0.075 | -0.075 | 0.500 | 0.322 | 18.541 | 15.615 |
| TNS (ns):| -50.945 | -50.945 | 0.000 | 0.000 | 0.000 | 0.000 |
| Violating Paths:| 1563 | 1563 | 0 | 0 | 0 | 0 |
| All Paths:| 85005 | 46605 | 63302 | 19 | 2 | 15 |
+--------------------+---------+---------+---------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 0 (0) | 0.000 | 0 (0) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 60.420%
------------------------------------------------------------
**optDesign ... cpu = 1:22:29, real = 1:18:11, mem = 5822.8M **
**INFO : removing temp dont-use cells (LVT only flow version : 4)
Deleting the dont_use list
*** Finished optDesign ***
Opening parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' for reading.
Closing parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d'. 9129572 times net's RC data read were performed.
RC Database In Completed (CPU Time= 0:00:01.3 MEM= 5714.3M)
timeDesign -expandedViews -reportOnly -outDir timingReports_final -prefix shabziger.postrouteopt3.expV
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
timeDesign Summary
------------------------------------------------------------
+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| -0.075 | -0.075 | 0.500 | 0.322 | 18.541 | 15.615 |
| TNS (ns):| -50.945 | -50.945 | 0.000 | 0.000 | 0.000 | 0.000 |
| Violating Paths:| 1563 | 1563 | 0 | 0 | 0 | 0 |
| All Paths:| 85005 | 46605 | 63302 | 19 | 2 | 15 |
+--------------------+---------+---------+---------+---------+---------+---------+
|dummy_slow_view | 7.872 | 7.872 | 9.009 | 8.722 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5131 | 2517 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_blake_slow_view| 0.035 | 0.035 | 3.896 | 3.722 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 8290 | 4385 | 3887 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_groestl_slow_view
| | -0.061 | -0.061 | 2.609 | 2.322 | N/A | N/A |
| | -1.485 | -1.485 | 0.000 | 0.000 | N/A | N/A |
| | 69 | 69 | 0 | 0 | N/A | N/A |
| | 8236 | 4070 | 4148 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_jh_slow_view | -0.024 | -0.024 | 2.009 | 1.722 | N/A | N/A |
| | -0.028 | -0.028 | 0.000 | 0.000 | N/A | N/A |
| | 2 | 2 | 0 | 0 | N/A | N/A |
| | 8801 | 4640 | 4143 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_keccak_slow_view
| | -0.060 | -0.060 | 0.726 | 0.722 | N/A | N/A |
| | -0.978 | -0.978 | 0.000 | 0.000 | N/A | N/A |
| | 57 | 57 | 0 | 0 | N/A | N/A |
| | 8346 | 4125 | 4203 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_sha2_slow_view | 0.105 | 0.105 | 2.497 | 2.222 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 7204 | 3554 | 3632 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_skein_slow_view| -0.062 | -0.062 | 1.597 | 1.522 | N/A | N/A |
| | -2.052 | -2.052 | 0.000 | 0.000 | N/A | N/A |
| | 76 | 76 | 0 | 0 | N/A | N/A |
| | 9002 | 4517 | 4467 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_blake_slow_view | -0.062 | -0.062 | 2.909 | 2.622 | N/A | N/A |
| | -3.402 | -3.402 | 0.000 | 0.000 | N/A | N/A |
| | 98 | 98 | 0 | 0 | N/A | N/A |
| | 9724 | 5498 | 4208 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_groestl_slow_view
| | -0.075 | -0.075 | 1.041 | 0.822 | N/A | N/A |
| | -33.275 | -33.275 | 0.000 | 0.000 | N/A | N/A |
| | 821 | 821 | 0 | 0 | N/A | N/A |
| | 9252 | 5088 | 4146 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_jh_slow_view | -0.059 | -0.059 | 0.609 | 0.322 | N/A | N/A |
| | -1.742 | -1.742 | 0.000 | 0.000 | N/A | N/A |
| | 100 | 100 | 0 | 0 | N/A | N/A |
| | 10269 | 5853 | 4398 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_keccak_slow_view| -0.069 | -0.069 | 0.609 | 0.322 | N/A | N/A |
| | -6.461 | -6.461 | 0.000 | 0.000 | N/A | N/A |
| | 294 | 294 | 0 | 0 | N/A | N/A |
| | 9926 | 5702 | 4206 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_sha2_slow_view | -0.060 | -0.060 | 0.500 | 0.522 | N/A | N/A |
| | -0.362 | -0.362 | 0.000 | 0.000 | N/A | N/A |
| | 18 | 18 | 0 | 0 | N/A | N/A |
| | 7986 | 4238 | 3730 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_skein_slow_view | -0.060 | -0.060 | 2.614 | 4.222 | N/A | N/A |
| | -1.245 | -1.245 | 0.000 | 0.000 | N/A | N/A |
| | 39 | 39 | 0 | 0 | N/A | N/A |
| | 10156 | 5551 | 4587 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ram1_slow_view | 5.156 | 5.156 | 9.009 | 8.722 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5237 | 2623 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ram2_slow_view | 4.908 | 4.908 | 9.009 | 8.722 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5237 | 2623 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ram3_slow_view | 3.366 | 3.366 | 9.009 | 8.722 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5240 | 2626 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|test_slow_view | 13.339 | 13.339 | 13.778 | 18.521 | 18.541 | 15.615 |
| | 0.000 | 0.000 | 0.000 | 0.000 | 0.000 | 0.000 |
| | 0 | 0 | 0 | 0 | 0 | 0 |
| | 85005 | 46605 | 63302 | 19 | 2 | 15 |
+--------------------+---------+---------+---------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 0 (0) | 0.000 | 0 (0) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 60.420%
------------------------------------------------------------
Reported timing to dir timingReports_final
Total CPU time: 210.33 sec
Total Real time: 153.0 sec
Total Memory Usage: 5716.566406 Mbytes
setNanoRouteMode -drouteMinSlackForWireoptimization 0.1
setNanoRouteMode -droutePostRouteSwapVia multiCut
#WARNING (NRIF-64) When droutePostRouteSwapVia is NOT set to 'false' or 'none', the tool just does post route via optimization and it will NOT do normal routing.
routeDesign -viaOpt
Begin checking placement ... (start mem=5716.6M, init mem=5716.6M)
*info: Placed = 252206
*info: Unplaced = 0
Placement Density:60.42%(1139641/1886211)
Finished checkPlace (cpu: total=0:00:02.6, vio checks=0:00:00.2; mem=5716.6M)
changeUseClockNetStatus Option : -noFixedNetWires
*** Changed status on (0) nets in Clock.
*** End changeUseClockNetStatus (cpu=0:00:00.0, real=0:00:00.0, mem=5716.6M) ***
detailRoute
#Start detailRoute on Fri Sep 30 11:26:47 2011
#
Closing parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d'. 101703 times net's RC data read were performed.
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_0 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_1 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_2 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_3 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_4 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_5 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_6 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_7 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_8 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_9 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_10 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_11 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_12 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_13 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_14 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_15 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_16 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_17 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_18 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34 Repeated 20 times. Will be suppressed.) Power/Ground pin VSSIO of instance fillperi_N_19 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRDB-733) PIN AlgSelxSI[0] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN AlgSelxSI[1] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN AlgSelxSI[2] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN AlgSelxSI[3] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN ClkDxCI in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN ClkxCI in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN CoreScanEnxTI in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN CoreScanInxTI in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[0] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[10] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[11] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[12] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[13] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[14] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[15] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[1] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[2] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[3] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[4] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733 Repeated 20 times. Will be suppressed.) PIN DataOutxDO[5] in CELL_VIEW shabziger_chip,init does not have physical port
#Start reading timing information from file .timing_file_9079.tif.gz ...
#WARNING (NRDB-193)
#Can't find instance top/i_gmu_groestl/FE_OCPC23270_n19298 in db referenced by timing file .timing_file_9079.tif.gz.
#WARNING (NRDB-192)
#Can't find port A in db referenced by timing file .timing_file_9079.tif.gz
#WARNING (NRDB-193)
#Can't find instance top/i_gmu_groestl/FE_OCPC23232_n1314 in db referenced by timing file .timing_file_9079.tif.gz.
#WARNING (NRDB-192)
#Can't find port A in db referenced by timing file .timing_file_9079.tif.gz
#WARNING (NRDB-193)
#Can't find instance top/i_gmu_groestl/FE_OCPUNCOC22977_n32440 in db referenced by timing file .timing_file_9079.tif.gz.
#WARNING (NRDB-192)
#Can't find port A in db referenced by timing file .timing_file_9079.tif.gz
#WARNING (NRDB-193)
#Can't find instance top/i_gmu_groestl/FE_OCPC22697_n9818 in db referenced by timing file .timing_file_9079.tif.gz.
#WARNING (NRDB-192)
#Can't find port A in db referenced by timing file .timing_file_9079.tif.gz
#WARNING (NRDB-193)
#Can't find instance top/i_gmu_groestl/FE_OCPC22676_n9769 in db referenced by timing file .timing_file_9079.tif.gz.
#WARNING (NRDB-192)
#Can't find port A in db referenced by timing file .timing_file_9079.tif.gz
#WARNING (NRDB-193)
#Can't find instance top/i_gmu_groestl/FE_OCPC22558_n37406 in db referenced by timing file .timing_file_9079.tif.gz.
#WARNING (NRDB-192)
#Can't find port A in db referenced by timing file .timing_file_9079.tif.gz
#WARNING (NRDB-193)
#Can't find instance top/i_gmu_groestl/FE_OCPC22439_n21279 in db referenced by timing file .timing_file_9079.tif.gz.
#WARNING (NRDB-192)
#Can't find port A in db referenced by timing file .timing_file_9079.tif.gz
#WARNING (NRDB-193)
#Can't find instance top/i_gmu_groestl/FE_OCPC22373_n24643 in db referenced by timing file .timing_file_9079.tif.gz.
#WARNING (NRDB-192)
#Can't find port A in db referenced by timing file .timing_file_9079.tif.gz
#WARNING (NRDB-193)
#Can't find instance top/i_gmu_groestl/FE_OCPC22186_n9360 in db referenced by timing file .timing_file_9079.tif.gz.
#WARNING (NRDB-192)
#Can't find port A in db referenced by timing file .timing_file_9079.tif.gz
#WARNING (NRDB-193)
#Can't find instance top/i_gmu_groestl/FE_OCP_RBC21910_n9895 in db referenced by timing file .timing_file_9079.tif.gz.
#WARNING (NRDB-192)
#Can't find port A in db referenced by timing file .timing_file_9079.tif.gz
#WARNING (NRDB-193)
#Can't find instance top/i_gmu_groestl/FE_OCPC21623_n11703 in db referenced by timing file .timing_file_9079.tif.gz.
#WARNING (NRDB-192)
#Can't find port A in db referenced by timing file .timing_file_9079.tif.gz
#WARNING (NRDB-193)
#Can't find instance top/i_gmu_groestl/dp_fx2_256_rounds_mc/FE_OCPC21481_dp_fx2_256_rounds_after_shiftrow_404_ in db referenced by timing file .timing_file_9079.tif.gz.
#WARNING (NRDB-192)
#Can't find port A in db referenced by timing file .timing_file_9079.tif.gz
#WARNING (NRDB-193)
#Can't find instance top/i_gmu_groestl/FE_OCPC20178_n1487 in db referenced by timing file .timing_file_9079.tif.gz.
#WARNING (NRDB-192)
#Can't find port A in db referenced by timing file .timing_file_9079.tif.gz
#WARNING (NRDB-193)
#Can't find instance top/i_gmu_groestl/FE_OCPC19510_n20151 in db referenced by timing file .timing_file_9079.tif.gz.
#WARNING (NRDB-192)
#Can't find port A in db referenced by timing file .timing_file_9079.tif.gz
#WARNING (NRDB-193)
#Can't find instance top/i_gmu_groestl/FE_OCPC19250_n1841 in db referenced by timing file .timing_file_9079.tif.gz.
#WARNING (NRDB-192)
#Can't find port A in db referenced by timing file .timing_file_9079.tif.gz
#WARNING (NRDB-193)
#Can't find instance top/i_gmu_groestl/FE_OCPC19232_n9601 in db referenced by timing file .timing_file_9079.tif.gz.
#WARNING (NRDB-192)
#Can't find port A in db referenced by timing file .timing_file_9079.tif.gz
#WARNING (NRDB-193)
#Can't find instance top/i_gmu_groestl/FE_OCPC19133_n9780 in db referenced by timing file .timing_file_9079.tif.gz.
#WARNING (NRDB-192)
#Can't find port A in db referenced by timing file .timing_file_9079.tif.gz
#WARNING (NRDB-193)
#Can't find instance top/i_gmu_groestl/FE_OCPC19054_n21362 in db referenced by timing file .timing_file_9079.tif.gz.
#WARNING (NRDB-192)
#Can't find port A in db referenced by timing file .timing_file_9079.tif.gz
#WARNING (NRDB-193)
#Can't find instance top/i_gmu_groestl/FE_OCPC18901_n11048 in db referenced by timing file .timing_file_9079.tif.gz.
#WARNING (NRDB-192)
#Can't find port A in db referenced by timing file .timing_file_9079.tif.gz
#WARNING (NRDB-193 Repeated 20 times. Will be suppressed.)
#Can't find instance top/i_gmu_groestl/FE_OCPC18831_n27309 in db referenced by timing file .timing_file_9079.tif.gz.
#WARNING (NRDB-192 Repeated 20 times. Will be suppressed.)
#Can't find port A in db referenced by timing file .timing_file_9079.tif.gz
#WARNING (EMS-27) Message (NRDB-193) has exceeded the current message display limit of 20.
#To increase the message display limit, refer to the product command reference manual.
#WARNING (EMS-27) Message (NRDB-192) has exceeded the current message display limit of 20.
#To increase the message display limit, refer to the product command reference manual.
#
# 32 instances referenced by timing file .timing_file_9079.tif.gz are missing in db.
#Read in timing information for 40 ports, 273873 instances from timing file .timing_file_9079.tif.gz.
#NanoRoute Version v10.12-s010 NR110720-1815/10_10_USR2-UB
#Merging special wires using 8 threads...
# ME1 H Track-Pitch = 0.200 Line-2-Via Pitch = 0.185
# ME2 V Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME3 H Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME4 V Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME5 H Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME6 V Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME7 H Track-Pitch = 0.400 Line-2-Via Pitch = 0.400
# ME8 V Track-Pitch = 4.000 Line-2-Via Pitch = 4.000
#2819 routed nets are extracted.
#277252 routed nets are imported.
#3737 routed nets are fixed|skipped|trivial (not extracted).
#Total number of nets = 283808.
#
#Start Post Route via swapping..
# number of violations = 497
#cpu time = 00:19:57, elapsed time = 00:03:34, memory = 5582.00 (Mb)
# number of violations = 496
#cpu time = 00:20:06, elapsed time = 00:03:41, memory = 5559.00 (Mb)
#CELL_VIEW shabziger_chip,init has 496 DRC violations
#Total number of DRC violations = 496
#Total number of net violated process antenna rule = 0
#Total number of violations on LAYER ME1 = 26
#Total number of violations on LAYER ME2 = 162
#Total number of violations on LAYER ME3 = 109
#Total number of violations on LAYER ME4 = 199
#Total number of violations on LAYER ME5 = 0
#Total number of violations on LAYER ME6 = 0
#Total number of violations on LAYER ME7 = 0
#Total number of violations on LAYER ME8 = 0
#Post Route via swapping is done.
#Total number of nets with non-default rule or having extra spacing = 1577
#Total wire length = 16459166 um.
#Total half perimeter of net bounding box = 14228523 um.
#Total wire length on LAYER ME1 = 180691 um.
#Total wire length on LAYER ME2 = 2600339 um.
#Total wire length on LAYER ME3 = 3565247 um.
#Total wire length on LAYER ME4 = 3076055 um.
#Total wire length on LAYER ME5 = 3629154 um.
#Total wire length on LAYER ME6 = 2727365 um.
#Total wire length on LAYER ME7 = 509320 um.
#Total wire length on LAYER ME8 = 170996 um.
#Total number of vias = 2811550
#Total number of multi-cut vias = 1140071 ( 40.5%)
#Total number of single cut vias = 1671479 ( 59.5%)
#Up-Via Summary (total 2811550):
# single-cut multi-cut Total
#-----------------------------------------------------------
# Metal 1 847628 ( 85.0%) 149283 ( 15.0%) 996911
# Metal 2 483593 ( 45.4%) 581336 ( 54.6%) 1064929
# Metal 3 195684 ( 50.7%) 190051 ( 49.3%) 385735
# Metal 4 90716 ( 44.9%) 111365 ( 55.1%) 202081
# Metal 5 47510 ( 37.8%) 78039 ( 62.2%) 125549
# Metal 6 0 ( 0.0%) 27461 (100.0%) 27461
# Metal 7 6348 ( 71.5%) 2536 ( 28.5%) 8884
#-----------------------------------------------------------
# 1671479 ( 59.5%) 1140071 ( 40.5%) 2811550
#
#
#detailRoute statistics:
#Cpu time = 00:20:53
#Elapsed time = 00:04:29
#Increased memory = -403.00 (Mb)
#Total memory = 5313.00 (Mb)
#Peak memory = 6373.00 (Mb)
#Number of warnings = 82
#Total number of warnings = 427
#Number of fails = 0
#Total number of fails = 0
#Complete detailRoute on Fri Sep 30 11:31:16 2011
#
saveDesign save/chip_shabziger_final3.enc
Redoing specifyClockTree ...
Checking spec file integrity...
Writing Netlist "save/chip_shabziger_final3.enc.dat/shabziger_chip.v.gz" ...
Saving clock tree spec file 'save/chip_shabziger_final3.enc.dat/shabziger_chip.ctstch' ...
Saving configuration ...
Saving preference file save/chip_shabziger_final3.enc.dat/enc.pref.tcl ...
Saving floorplan ...
Saving Drc markers ...
... 496 Drc markers are saved ...
Saving placement ...
*** Completed savePlace (cpu=0:00:00.4 real=0:00:01.0 mem=5323.3M) ***
Saving route ...
*** Completed saveRoute (cpu=0:00:05.2 real=0:00:13.0 mem=5323.3M) ***
Writing DEF file 'save/chip_shabziger_final3.enc.dat/shabziger_chip.def.gz', current time is Fri Sep 30 11:33:12 2011 ...
unitPerMicron=1000, dbgMicronPerDBU=0.001000, unitPerDBU=1.000000
DEF file 'save/chip_shabziger_final3.enc.dat/shabziger_chip.def.gz' is written, current time is Fri Sep 30 11:33:13 2011 ...
*** Completed saveYieldMap (cpu=: 0:00:00.0 real=0:00:00.0 mem=: 0.000M) ***
zoomBox 429.178 1781.781 598.618 1626.948
zoomBox 476.324 1717.766 505.282 1701.732
zoomBox 487.367 1714.453 494.975 1708.195
violationBrowser -all -no_display_false
fit
zoomBox 739.955 1136.161 802.455 1069.196
zoomBox 758.269 1114.637 767.038 1104.998
zoomBox 760.238 1112.092 762.763 1109.411
zoomOut
zoomOut
zoomOut
fit
violationBrowser -all -no_display_false
clearDrc
zoomBox -4.066 1875.117 1879.064 -11.961
setNanoRouteMode -drouteStartIteration 20
setNanoRouteMode -drouteEndIteration default
detailRoute
detailRoute
#Start detailRoute on Fri Sep 30 12:35:29 2011
#
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
#Start reading timing information from file .timing_file_9079.tif.gz ...
#
# 32 instances referenced by timing file .timing_file_9079.tif.gz are missing in db.
#Read in timing information for 40 ports, 273873 instances from timing file .timing_file_9079.tif.gz.
#NanoRoute Version v10.12-s010 NR110720-1815/10_10_USR2-UB
#Merging special wires using 8 threads...
# ME1 H Track-Pitch = 0.200 Line-2-Via Pitch = 0.185
# ME2 V Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME3 H Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME4 V Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME5 H Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME6 V Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME7 H Track-Pitch = 0.400 Line-2-Via Pitch = 0.400
# ME8 V Track-Pitch = 4.000 Line-2-Via Pitch = 4.000
#
#Start Post Route via swapping..
# number of violations = 497
#cpu time = 00:17:07, elapsed time = 00:03:18, memory = 5600.00 (Mb)
# number of violations = 496
#cpu time = 00:17:15, elapsed time = 00:03:24, memory = 5573.00 (Mb)
#CELL_VIEW shabziger_chip,init has 496 DRC violations
#Total number of DRC violations = 496
#Total number of net violated process antenna rule = 0
#Total number of violations on LAYER ME1 = 26
#Total number of violations on LAYER ME2 = 162
#Total number of violations on LAYER ME3 = 109
#Total number of violations on LAYER ME4 = 199
#Total number of violations on LAYER ME5 = 0
#Total number of violations on LAYER ME6 = 0
#Total number of violations on LAYER ME7 = 0
#Total number of violations on LAYER ME8 = 0
#Post Route via swapping is done.
#Total number of nets with non-default rule or having extra spacing = 1577
#Total wire length = 16459166 um.
#Total half perimeter of net bounding box = 14228523 um.
#Total wire length on LAYER ME1 = 180691 um.
#Total wire length on LAYER ME2 = 2600339 um.
#Total wire length on LAYER ME3 = 3565247 um.
#Total wire length on LAYER ME4 = 3076055 um.
#Total wire length on LAYER ME5 = 3629154 um.
#Total wire length on LAYER ME6 = 2727365 um.
#Total wire length on LAYER ME7 = 509320 um.
#Total wire length on LAYER ME8 = 170996 um.
#Total number of vias = 2811550
#Total number of multi-cut vias = 1148344 ( 40.8%)
#Total number of single cut vias = 1663206 ( 59.2%)
#Up-Via Summary (total 2811550):
# single-cut multi-cut Total
#-----------------------------------------------------------
# Metal 1 847308 ( 85.0%) 149603 ( 15.0%) 996911
# Metal 2 481060 ( 45.2%) 583869 ( 54.8%) 1064929
# Metal 3 193170 ( 50.1%) 192565 ( 49.9%) 385735
# Metal 4 88908 ( 44.0%) 113173 ( 56.0%) 202081
# Metal 5 46412 ( 37.0%) 79137 ( 63.0%) 125549
# Metal 6 0 ( 0.0%) 27461 (100.0%) 27461
# Metal 7 6348 ( 71.5%) 2536 ( 28.5%) 8884
#-----------------------------------------------------------
# 1663206 ( 59.2%) 1148344 ( 40.8%) 2811550
#
#
#detailRoute statistics:
#Cpu time = 00:18:01
#Elapsed time = 00:04:10
#Increased memory = 6.00 (Mb)
#Total memory = 5315.00 (Mb)
#Peak memory = 6373.00 (Mb)
#Number of warnings = 0
#Total number of warnings = 427
#Number of fails = 0
#Total number of fails = 0
#Complete detailRoute on Fri Sep 30 12:39:39 2011
#
zoomBox 120.246 1092.142 273.593 989.309
zoomBox 152.680 1059.896 163.101 1042.102
addFiller -cell {FILEP64W FILEP32W FILEP16W FILEP8W FILE6W FILE4W FILE3W FIL2W FILEP64S FILEP32S FILEP16S FILEP8S FILE6S FILE4S FILE3S FIL2S FILEP64R FILEP32R FILEP16R FILEP8R FILE6R FILE4R FILE3R FIL2R} -prefix fillcore
*INFO: Adding fillers to top-module.
*INFO: Added 1164 filler insts (cell FILEP64W / prefix fillcore).
*INFO: Added 5013 filler insts (cell FILEP64S / prefix fillcore).
*INFO: Added 246 filler insts (cell FILEP64R / prefix fillcore).
*INFO: Added 5390 filler insts (cell FILEP32W / prefix fillcore).
*INFO: Added 2334 filler insts (cell FILEP32S / prefix fillcore).
*INFO: Added 584 filler insts (cell FILEP32R / prefix fillcore).
*INFO: Added 18211 filler insts (cell FILEP16W / prefix fillcore).
*INFO: Added 6277 filler insts (cell FILEP16S / prefix fillcore).
*INFO: Added 1883 filler insts (cell FILEP16R / prefix fillcore).
*INFO: Added 36756 filler insts (cell FILEP8W / prefix fillcore).
*INFO: Added 8895 filler insts (cell FILEP8S / prefix fillcore).
*INFO: Added 3970 filler insts (cell FILEP8R / prefix fillcore).
*INFO: Added 22703 filler insts (cell FILE6W / prefix fillcore).
*INFO: Added 4561 filler insts (cell FILE6S / prefix fillcore).
*INFO: Added 2326 filler insts (cell FILE6R / prefix fillcore).
*INFO: Added 31369 filler insts (cell FILE4W / prefix fillcore).
*INFO: Added 5940 filler insts (cell FILE4S / prefix fillcore).
*INFO: Added 3241 filler insts (cell FILE4R / prefix fillcore).
*INFO: Added 22393 filler insts (cell FILE3W / prefix fillcore).
*INFO: Added 5740 filler insts (cell FILE3S / prefix fillcore).
*INFO: Added 2304 filler insts (cell FILE3R / prefix fillcore).
*INFO: Added 29428 filler insts (cell FIL2W / prefix fillcore).
*INFO: Added 4154 filler insts (cell FIL2S / prefix fillcore).
*INFO: Added 3018 filler insts (cell FIL2R / prefix fillcore).
*INFO: Total 227900 filler insts added - prefix fillcore (CPU: 0:00:04.3).
For 227900 new insts, *** Applied 4 GNC rules (cpu = 0:00:00.1)
*INFO: Checking for DRC violations on added fillers.
*INFO: Iteration 0-#1, Found 466794 DRC violations (real: 0:00:48.0).
For 184825 new insts, *** Applied 4 GNC rules (cpu = 0:00:00.1)
*INFO: Iteration 0-#2, Found 309395 DRC violations (real: 0:00:40.0).
For 104973 new insts, *** Applied 4 GNC rules (cpu = 0:00:00.1)
*INFO: Iteration 0-#3, Found 197596 DRC violations (real: 0:00:40.0).
For 60953 new insts, *** Applied 4 GNC rules (cpu = 0:00:00.0)
*INFO: Iteration 0-#4, Found 99872 DRC violations (real: 0:00:38.0).
For 29146 new insts, *** Applied 4 GNC rules (cpu = 0:00:00.0)
*INFO: Iteration 0-#5, Found 41374 DRC violations (real: 0:00:35.0).
For 9531 new insts, *** Applied 4 GNC rules (cpu = 0:00:00.0)
*INFO: Iteration 0-#6, Found 9922 DRC violations (real: 0:00:36.0).
For 1892 new insts, *** Applied 4 GNC rules (cpu = 0:00:00.0)
*INFO: Iteration 0-#7, Found 531 DRC violations (real: 0:00:35.0).
For 380 new insts, *** Applied 4 GNC rules (cpu = 0:00:00.0)
*INFO: Iteration 0-#8, Found 0 DRC violation (real: 0:00:36.0).
*INFO: Adding fillers to top-module.
*INFO: Added 153083 filler insts (cell FIL2R / prefix fillcore).
For 153083 new insts, *** Applied 4 GNC rules (cpu = 0:00:00.1)
*INFO: End DRC Checks. (real: 0:05:56 ).
*INFO: Replaced 296872 fillers which had DRC vio's, with 391700 new fillers.
addFiller -cell {FIL1W FIL1R FIL1S} -prefix fillcore
*INFO: Adding fillers to top-module.
*INFO: Added 63059 filler insts (cell FIL1W / prefix fillcore).
*INFO: Added 7414 filler insts (cell FIL1S / prefix fillcore).
*INFO: Added 26538 filler insts (cell FIL1R / prefix fillcore).
*INFO: Total 97011 filler insts added - prefix fillcore (CPU: 0:00:04.8).
For 97011 new insts, *** Applied 4 GNC rules (cpu = 0:00:00.1)
*INFO: Checking for DRC violations on added fillers.
*INFO: Iteration 0-#1, Found 0 DRC violation (real: 0:00:39.0).
*INFO: Adding fillers to top-module.
*INFO: Added 0 filler inst of any cell-type.
For 0 new insts, *** Applied 0 GNC rules.
*INFO: End DRC Checks. (real: 0:00:40.0 ).
setExtractRCMode -engine detail -coupled false -reduce 0.0
**WARN: (ENCEXT-1082): Option '-engine detail' is obsolete. Use '-engine postRoute [-effortLevel low]' to set extraction engine, which is based on recommended convention '-engine postRoute [-effortLevel ]'. The obsolete option still works in this release, but to avoid this warning and to ensure compatibility with future releases, update your script and configuration file to use recommended convention.
**WARN: (ENCEXT-1090): Option '-effortLevel low' specified in past directly by user or in-directly through 'timeDesign -signoff' or similar command. And option '-engine detail' specified now. User is recommended to use either '-engine postRoute [-effortLevel ]' or '-engine default|detail|cce|signoff' because '-engine default|detail|cce|signoff' has implicit meaning for '-effortLevel'. In this case, most recent engine option specified '-engine detail' will be honored by the tool and '-effortLevel' ignored.
extractRC
Extraction called for design 'shabziger_chip' of instances=883715 and nets=283808 using extraction engine 'postRoute' at effort level 'low' .
Detail RC Extraction called for design shabziger_chip.
RC Extraction called in multi-corner(2) mode.
Process corner(s) are loaded.
Corner: rc_worst
Corner: rc_best
extractDetailRC Option : -outfile ../tmp/shabziger_chip_wukc1u_9079.rcdb.d -maxResLength 200 -extended
RC Mode: Detail [Extended CapTable, RC Table Resistances]
RC Corner Indexes 0 1
Capacitance Scaling Factor : 1.00000 1.00000
Coupling Cap. Scaling Factor : 1.00000 1.00000
Resistance Scaling Factor : 1.00000 1.00000
Clock Cap. Scaling Factor : 1.00000 1.00000
Clock Res. Scaling Factor : 1.00000 1.00000
Shrink Factor : 1.00000
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Checking LVS Completed (CPU Time= 0:00:01.5 MEM= 5387.0M)
Creating parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' in memory efficient access mode for storing RC.
Extracted 10% (CPU Time= 0:00:10.3 MEM= 5627.6M)
Extracted 20.0001% (CPU Time= 0:00:18.7 MEM= 5627.6M)
Extracted 30.0001% (CPU Time= 0:00:23.2 MEM= 5627.6M)
Extracted 40% (CPU Time= 0:00:30.4 MEM= 5627.6M)
Extracted 50.0001% (CPU Time= 0:00:39.8 MEM= 5627.6M)
Extracted 60.0001% (CPU Time= 0:00:45.5 MEM= 5627.6M)
Extracted 70% (CPU Time= 0:00:55.0 MEM= 5627.6M)
Extracted 80.0001% (CPU Time= 0:01:05 MEM= 5627.6M)
Extracted 90.0001% (CPU Time= 0:01:11 MEM= 5627.6M)
Extracted 100% (CPU Time= 0:01:26 MEM= 5627.6M)
Nr. Extracted Resistors : 5602495
Nr. Extracted Ground Cap. : 5881398
Nr. Extracted Coupling Cap. : 0
Opening parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' for reading.
Detail RC Extraction DONE (CPU Time: 0:01:32 Real Time: 0:01:36 MEM: 5386.969M)
setAnalysisMode -checkType setup
set_global timing_recompute_sdf_in_setuphold_mode true
write_sdf -precision 4 -min_period_edges posedge -remashold \
-min_view hold_fast_view -typ_view test_slow_view -max_view test_slow_view \
out/${NAME}.sdf.gz
Using new Cte TW Api base...#################################################################################
# Design Stage: PostRoute
# Design Mode: 65nm
# Analysis Mode: MMMC non-OCV
# Extraction Mode: detail/spef
# Delay Calculation Options: engine=signalStorm signOff=true SIAware=false(opt)
# Switching Delay Calculation Engine to signalStorm
#################################################################################
Multi-cpu acceleration using 8 CPU(s).
Topological Sorting (CPU = 0:00:02.6, MEM = 0.3M, InitMEM = 0.8M)
Start delay calculation using Signal Storm (mem=0.328M)...
delayCal using detail RC...
Opening parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' for reading.
RC Database In Completed (CPU Time= 0:00:02.4 MEM= 41.2M)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Delay calculation completed. (cpu=0:00:59.0 real=0:00:56.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.8, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:52.3 real=0:00:49.0 mem=0.000M 0)
Closing parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d'. 652181 times net's RC data read were performed.
Topological Sorting (CPU = 0:00:03.9, MEM = 0.3M, InitMEM = 0.8M)
Start delay calculation using Signal Storm (mem=0.328M)...
delayCal using detail RC...
Opening parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d/header.da' for reading.
RC Database In Completed (CPU Time= 0:00:02.3 MEM= 41.2M)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Delay calculation completed. (cpu=0:01:41 real=0:01:03 mem=0.000M 0)
Topological Sorting (CPU = 0:00:02.6, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:01:35 real=0:00:56.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.3, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:29.0 real=0:00:26.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.3, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:28.7 real=0:00:25.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.3, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:29.3 real=0:00:26.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.3, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:28.9 real=0:00:25.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.3, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:29.5 real=0:00:26.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.3, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:29.5 real=0:00:27.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.3, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:29.8 real=0:00:26.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.3, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:29.6 real=0:00:26.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.3, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:29.3 real=0:00:26.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.2, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:29.7 real=0:00:26.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.9, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:30.2 real=0:00:27.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.3, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:30.0 real=0:00:27.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.3, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:30.2 real=0:00:27.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.3, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:30.0 real=0:00:27.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.3, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:31.9 real=0:00:29.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.3, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:31.8 real=0:00:29.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.3, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:30.8 real=0:00:28.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.3, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:30.7 real=0:00:28.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.3, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:31.8 real=0:00:28.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.3, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:31.6 real=0:00:28.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.4, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:31.1 real=0:00:27.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.3, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:30.9 real=0:00:27.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.3, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:32.9 real=0:00:30.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.3, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:32.7 real=0:00:30.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.3, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:31.4 real=0:00:28.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.3, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:31.2 real=0:00:28.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.3, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:31.3 real=0:00:28.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.3, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:31.2 real=0:00:28.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.3, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:31.5 real=0:00:28.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.3, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:31.3 real=0:00:28.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.3, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:40.4 real=0:00:37.0 mem=0.000M 0)
Topological Sorting (CPU = 0:00:01.3, MEM = 0.0M, InitMEM = 0.0M)
Start delay calculation using Signal Storm (mem=0.000M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:39.9 real=0:00:36.0 mem=0.000M 0)
Closing parasitic data file '../tmp/shabziger_chip_wukc1u_9079.rcdb.d'. 9141073 times net's RC data read were performed.
Topological Sorting (CPU = 0:00:01.4, MEM = 5449.3M, InitMEM = 5449.8M)
*** CDM Built up (cpu=0:27:03 real=0:22:47 mem= 6082.4M) ***
saveNetlist out/shabziger.v -excludeLeafCell -includePhysicalInst
Writing Netlist "out/shabziger.v" ...
Warning (Quiet mode): There are 200 pg terms not connected to global special net.
**WARN: (ENCVL-505): PG terms are not connected to global pg nets.
**WARN: (ENCVL-516): No Power/Ground connections in top module (shabziger_chip).
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_0 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_1 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_2 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_3 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_4 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_5 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_6 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_7 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_8 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_9 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_10 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_11 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_12 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_13 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_14 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_15 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_16 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_17 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_18 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_19 is not connected to a global P/G net.
Pwr name (VDD).
Pwr name (VDDIO).
Gnd name (VSS).
Gnd name (VSSIO).
2 Pwr names and 2 Gnd names.
saveNetlist out/shabziger_lvs.v -excludeLeafCell -includePhysicalInst -phys
Writing Netlist "out/shabziger_lvs.v" ...
Warning (Quiet mode): There are 200 pg terms not connected to global special net.
**WARN: (ENCVL-505): PG terms are not connected to global pg nets.
**WARN: (ENCVL-516): No Power/Ground connections in top module (shabziger_chip).
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_0 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_1 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_2 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_3 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_4 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_5 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_6 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_7 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_8 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_9 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_10 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_11 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_12 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_13 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_14 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_15 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_16 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_17 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_18 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_19 is not connected to a global P/G net.
Pwr name (VDD).
Pwr name (VDDIO).
Gnd name (VSS).
Gnd name (VSSIO).
2 Pwr names and 2 Gnd names.
Creating all pg connections for top cell (shabziger_chip).
setStreamOutMode -SEvianames ON -specifyViaName %t_VIA
streamOut out/shabziger.gds.gz -mapFile tech/streamOut_noObs.map -outputMacros -merge { /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbr/a02/gds/uk65lscllmvbbr.gds /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbl/a02/gds/uk65lscllmvbbl.gds /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbh/a02/gds/uk65lscllmvbbh.gds /usr/pack/umc-65-kgf/umc/ll/u065gioll25mvir/a03/gds/u065gioll25mvir_8m1t0f1u.gds /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_16384X32X1CM16.gds /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_2048X32X1CM4.gds /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SYKA65_2048X32X1CM8.gds }
Finding the highest version number among the merge files
Merge file: /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbr/a02/gds/uk65lscllmvbbr.gds has version number: 5
Merge file: /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbl/a02/gds/uk65lscllmvbbl.gds has version number: 5
Merge file: /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbh/a02/gds/uk65lscllmvbbh.gds has version number: 5
Merge file: /usr/pack/umc-65-kgf/umc/ll/u065gioll25mvir/a03/gds/u065gioll25mvir_8m1t0f1u.gds has version number: 5
Merge file: /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_16384X32X1CM16.gds has version number: 5
Merge file: /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_2048X32X1CM4.gds has version number: 5
Merge file: /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SYKA65_2048X32X1CM8.gds has version number: 5
Parse map file...
Writing GDSII file ...
****** db unit per micron = 1000 ******
****** output gds2 file unit per micron = 1000 ******
****** unit scaling factor = 1 ******
Output for instance
Output for bump
Output for physical terminals
Output for logical terminals
Output for regular nets
Output for special nets and metal fills
Output for via structure generation
Statistics for GDS generated (version 5)
----------------------------------------
Stream Out Layer Mapping Information:
GDS Layer Number GDS Layer Name
----------------------------------------
121 COMP
46 ME1
47 VI1
48 ME2
49 VI2
50 ME3
51 VI3
52 ME4
53 VI4
54 ME5
55 VI5
56 ME6
57 VI6
58 ME7
59 VI7
60 ME8
101 ME1
102 ME2
103 ME3
104 ME4
105 ME5
106 ME6
107 ME7
108 ME8
Stream Out Information Processed for GDS version 5:
Units: 1000 DBU
Object Count
----------------------------------------
Instances 883715
Ports/Pins 0
Nets 2766827
metal layer ME1 167157
metal layer ME2 1101200
metal layer ME3 834078
metal layer ME4 309270
metal layer ME5 205281
metal layer ME6 102820
metal layer ME7 42235
metal layer ME8 4786
Via Instances 2811550
Special Nets 4751
metal layer ME1 4146
metal layer ME2 68
metal layer ME3 57
metal layer ME4 24
metal layer ME5 24
metal layer ME6 24
metal layer ME7 319
metal layer ME8 89
Via Instances 189513
Metal Fills 0
Via Instances 0
Metal FillOPCs 0
Via Instances 0
Text 42
metal layer ME1 2
metal layer ME4 40
Blockages 0
Custom Text 0
Custom Box 0
Merging with GDS libraries
Scanning GDS file /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbr/a02/gds/uk65lscllmvbbr.gds to register cell name ......
Scanning GDS file /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbl/a02/gds/uk65lscllmvbbl.gds to register cell name ......
Scanning GDS file /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbh/a02/gds/uk65lscllmvbbh.gds to register cell name ......
Scanning GDS file /usr/pack/umc-65-kgf/umc/ll/u065gioll25mvir/a03/gds/u065gioll25mvir_8m1t0f1u.gds to register cell name ......
Scanning GDS file /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_16384X32X1CM16.gds to register cell name ......
Scanning GDS file /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_2048X32X1CM4.gds to register cell name ......
Scanning GDS file /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SYKA65_2048X32X1CM8.gds to register cell name ......
Merging GDS file /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbr/a02/gds/uk65lscllmvbbr.gds ......
****** Merge file: /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbr/a02/gds/uk65lscllmvbbr.gds has version number: 5.
****** Merge file: /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbr/a02/gds/uk65lscllmvbbr.gds has units: 1000 per micron.
****** unit scaling factor = 1 ******
Merging GDS file /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbl/a02/gds/uk65lscllmvbbl.gds ......
****** Merge file: /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbl/a02/gds/uk65lscllmvbbl.gds has version number: 5.
****** Merge file: /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbl/a02/gds/uk65lscllmvbbl.gds has units: 1000 per micron.
****** unit scaling factor = 1 ******
Merging GDS file /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbh/a02/gds/uk65lscllmvbbh.gds ......
****** Merge file: /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbh/a02/gds/uk65lscllmvbbh.gds has version number: 5.
****** Merge file: /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbh/a02/gds/uk65lscllmvbbh.gds has units: 1000 per micron.
****** unit scaling factor = 1 ******
Merging GDS file /usr/pack/umc-65-kgf/umc/ll/u065gioll25mvir/a03/gds/u065gioll25mvir_8m1t0f1u.gds ......
****** Merge file: /usr/pack/umc-65-kgf/umc/ll/u065gioll25mvir/a03/gds/u065gioll25mvir_8m1t0f1u.gds has version number: 5.
****** Merge file: /usr/pack/umc-65-kgf/umc/ll/u065gioll25mvir/a03/gds/u065gioll25mvir_8m1t0f1u.gds has units: 1000 per micron.
****** unit scaling factor = 1 ******
Merging GDS file /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_16384X32X1CM16.gds ......
****** Merge file: /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_16384X32X1CM16.gds has version number: 5.
****** Merge file: /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_16384X32X1CM16.gds has units: 1000 per micron.
****** unit scaling factor = 1 ******
Merging GDS file /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_2048X32X1CM4.gds ......
****** Merge file: /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_2048X32X1CM4.gds has version number: 5.
****** Merge file: /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_2048X32X1CM4.gds has units: 1000 per micron.
****** unit scaling factor = 1 ******
WARNING: Ignoring duplicate structure SHKA_DIDO_GAP.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PRED38_GAP.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XDECGAP_BOT_A3.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_BLMUX_AR4.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10028064.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12083272.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12085362.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12105249.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12105528.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12170460.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12285811.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12359965.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14326535.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14330618.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14337440.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14343616.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23646729.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_6232157.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_6317025.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_6395777.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8298672.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CORNER_BOT.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CORNER_TOP.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CORNER_TOP_R.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DELAY_0.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DELAY_1.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DUMBL2.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DUMBL_GAP.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DUMWL4.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DUMX4_BOT.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DUMX4_TOP.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DUMY2.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DUMY2_R.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DUMY_GAP.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DUM_CORNER_BOT.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DUM_CORNER_TOP.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DVSDEBUG_M1.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_GAR_2001977.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_GAR_3531995.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_MTCH_V2.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_419780_SHKA_BTI_0726.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PRED38.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PRED38_GAP_ANTLAYERS.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PREDLS.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PRED_V2.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_RAM4X2.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_RAM_GAP4.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_V1.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_V2.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_V3.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_WEB_M3.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XDEC2_A3.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XDECGAP_BOT.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XDEC_GAP_A3.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XDEC_V2.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_10008858.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3160920.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3170609.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3205977.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3209960.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3221359.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3228325.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3233103.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3321437.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3425269.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3426521.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3426581.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3452029.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3456148.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3463740.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3478292.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3489149.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3749629.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3835106.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3858135.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3889300.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3940578.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3997181.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4498960.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4822324.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4844500.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5226718.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5335262.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5933202.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6518403.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6548882.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_7725639.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_7873963.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_7945450.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_8056179.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_9660467.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_AY0_AR4.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_BLMUX.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_BLMUX_A.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10037589.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10038316.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10134998.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12085174.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12088082.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12088997.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12099175.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12104264.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12105697.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12106424.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12191805.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12197959.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12278541.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12285084.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12288719.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12292394.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12296247.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12296695.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12296974.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12297701.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12302925.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14323697.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14324086.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14324754.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14325914.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14326039.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14327262.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14327713.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14327989.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14328095.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14328150.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14328264.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14328437.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14328598.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14328877.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14329164.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14329387.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14329443.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14329891.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14329993.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14330103.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14331624.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14335986.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14339621.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23890040.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23970077.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24141245.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24174576.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24220647.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24236789.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24260656.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24353232.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24419738.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24496345.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24507306.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24558188.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24677599.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_27874146.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_6239042.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8302216.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8321376.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8495670.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8513101.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DBLRESET_AR8.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DELAY_0_ANTLAYERS.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DELAY_1_ANTLAYERS.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_MATCH_AR8.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_MOSCAPA.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_MOSCAPB.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_MOSCAPC.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_433080.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PRED38_ANTLAYERS.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_WEB_M3_ANTLAYERS.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XDEC_A.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XDEC_GAP_A1.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_10273994.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_11029292.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_11415054.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_11850288.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_12161762.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_16719629.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_20345153.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_2819235.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3213362.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_34797202.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_34873714.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3511167.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3731140.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3905988.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3919509.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3943108.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4012213.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4063591.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4153447.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4197877.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4397290.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4459583.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4476498.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4635864.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4770373.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4829351.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4845450.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4908273.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4922435.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5211455.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5234628.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5409831.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5532826.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5645561.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6051119.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6237011.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6547522.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6567661.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6795078.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6865252.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6905918.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_7498080.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_7536011.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_7549678.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_7689095.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_7705681.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_7922876.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_8555373.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_9307368.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_9411948.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_9515986.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_BLMUX_1.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10017254.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10017533.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10027616.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10027785.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10027895.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10028512.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10029239.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10037868.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10116510.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10117237.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10122860.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10130730.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10131457.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10133112.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10208531.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10218335.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10223111.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10223559.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10938078.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10938526.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10939253.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10939980.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10941174.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10941622.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10950978.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10951426.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10961229.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11039030.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11039478.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11040205.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11040932.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11041659.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11043840.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11046949.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11047675.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11048202.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11049656.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11049857.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11050584.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11056399.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11057126.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11057853.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11133346.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11136254.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11147199.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11152954.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11157730.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12082266.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12084447.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12085920.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12086816.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12087543.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12089724.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12090451.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12092632.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12095445.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12095540.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12096267.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12096620.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12164562.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12169006.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12171914.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12174095.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12183946.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12190968.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12191416.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12192143.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12192870.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12193597.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12193750.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12194324.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12195051.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12195578.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12196505.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12197232.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12198686.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12199413.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12200867.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12201220.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12201594.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12201947.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12202321.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12203048.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12203775.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12204502.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12205229.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12208137.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12208864.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12211772.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12212499.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12247479.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12248654.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12251562.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12277087.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12277814.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12282903.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12286443.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12291219.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12291667.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12301471.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14324145.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14326366.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14326645.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14326983.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14329156.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14332799.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23647287.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23647456.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23647566.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23647735.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23648293.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23648403.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23648462.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23648572.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23648851.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23648910.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23649189.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23649916.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23651370.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23655005.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23657186.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23657913.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23816956.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23816956_FSE0K_A.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23817034.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23863283.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23863361.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23870314.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23889962.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23909610.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23909688.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23936289.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23950351.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23956015.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23982616.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23982694.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24002342.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24028943.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24075270.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24214251.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24233977.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24306667.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24677521.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24697247.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24955483.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_5194519.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_6233053.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_6233660.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_6234108.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_6238594.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_6444266.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_7255157.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_7263802.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8301489.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8301768.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8311572.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8507794.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8512374.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8882870.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8893122.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8978392.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8978840.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_9073867.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_9079091.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_GAR_2089412.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_413100_F.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_413100_SHKA_BTI_0726.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_413640_SHKA_BTI_0726.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_419780_F.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_432540_F.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_463937_F.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_465759_F.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_465999_F.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XDIODE.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_10086253.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_1588363.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_1588781.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_1614729.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_2616968.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_2690537.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_2813413.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3103705.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3193058.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3209137.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3221112.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3231597.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3259615.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3321377.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3410806.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3491211.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3564189.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3599675.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3617789.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3628757.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3694584.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3749060.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3751739.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3798684.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3821577.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3829603.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3846795.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3852026.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3858131.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3924940.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4018282.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4035586.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4129886.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4145097.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4311763.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4339723.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4421332.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4423521.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4428877.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4437005.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4444940.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4466863.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4525653.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4553147.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4553698.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4593509.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4634404.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4642245.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4681731.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4701908.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4709585.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4734365.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4837950.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4845075.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4855525.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4912583.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4952643.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5005409.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5023948.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5052505.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5064787.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5075321.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5095161.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5125877.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5238456.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5352850.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5471841.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5484265.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5499185.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5504434.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5569190.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5607136.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5757317.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5799040.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5934895.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5955236.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6153764.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6199865.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6272006.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6276061.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6726858.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6802803.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6870134.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6956844.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_8555162.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_8647761.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10017981.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10027337.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12082545.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12082993.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12083720.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12085641.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12086089.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12088270.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12095893.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12169733.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12195778.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14325081.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23909610_FSE0K_A.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_25026146.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_6243464.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8312020.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8312747.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_358840.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_413100_FSE0K_A.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_413640_FSE0K_A.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_420640.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_433400.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_438901.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_464477.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_464717.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_467581_SHKA_BTI_0726.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_467821_SHKA_BTI_0726.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_468121.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_468361.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3431959.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3597012.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3722489.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3858075.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4009666.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4258831.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4307140.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4405335.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5574242.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_413100_1_FSE0K_A.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_413640_1_FSE0K_A.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_419780_FSE0K_A.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_432540_SHKA_BTI_0726.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_463937_SHKA_BTI_0726.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_464177.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_465759_SHKA_BTI_0726.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_465999_SHKA_BTI_0726.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_466299_SHKA_BTI_0726.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_466539.
A structure with the same name already exists in one of the merging GDSII files.
There are 529 structures ignored in file /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_2048X32X1CM4.gds
Merging GDS file /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SYKA65_2048X32X1CM8.gds ......
****** Merge file: /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SYKA65_2048X32X1CM8.gds has version number: 5.
****** Merge file: /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SYKA65_2048X32X1CM8.gds has units: 1000 per micron.
****** unit scaling factor = 1 ******
Output for cells
######Streamout is finished!
*** Memory Usage v#8 (Current mem = 5379.145M, initial mem = 59.977M) ***
--- Ending "Encounter" (totcpu=25:56:41, real=26:23:22, mem=5379.1M) ---
Checking out Encounter license ...
Encounter_Digital_Impl_Sys_XL 10.1 license checkout succeeded.
You can run 2 CPU jobs with the base license that is currently checked out.
If required, use the setMultiCpuUsage command to enable multi-CPU processing.
This Encounter release has been compiled with OA version 22.04-p011.
*******************************************************************
* Copyright (c) Cadence Design Systems, Inc. 1996 - 2011. *
* All rights reserved. *
* *
* *
* *
* This program contains confidential and trade secret information *
* of Cadence Design Systems, Inc. and is protected by copyright *
* law and international treaties. Any reproduction, use, *
* distribution or disclosure of this program or any portion of it,*
* or any attempt to obtain a human-readable version of this *
* program, without the express, prior written consent of *
* Cadence Design Systems, Inc., is strictly prohibited. *
* *
* Cadence Design Systems, Inc. *
* 2655 Seely Avenue *
* San Jose, CA 95134, USA *
* *
* *
*******************************************************************
@(#)CDS: Encounter v10.12-s181_1 (64bit) 07/28/2011 22:52 (Linux 2.6)
@(#)CDS: NanoRoute v10.12-s010 NR110720-1815/10_10_USR2-UB (database version 2.30, 124.2.1) {superthreading v1.15}
@(#)CDS: CeltIC v10.12-s013_1 (64bit) 07/27/2011 04:14:35 (Linux 2.6.9-89.0.19.ELsmp)
@(#)CDS: AAE 10.12-s001 (64bit) 07/28/2011 (Linux 2.6.9-89.0.19.ELsmp)
@(#)CDS: CTE 10.12-s010_1 (64bit) Jul 18 2011 22:58:43 (Linux 2.6.9-89.0.19.ELsmp)
@(#)CDS: CPE v10.12-s007
--- Starting "Encounter v10.12-s181_1" on Fri Sep 30 13:44:32 2011 (mem=59.9M) ---
--- Running on aotearoa.ee.ethz.ch (x86_64 w/Linux 2.6.18-238.5.1.el5) ---
This version was compiled on Thu Jul 28 22:52:33 PDT 2011.
Set DBUPerIGU to 1000.
Set net toggle Scale Factor to 1.00
Set Shrink Factor to 1.00000
Sourcing ./enc.tcl
Sourcing tcl/tk file "./enc.tcl" ...
setDelayCalMode -engine signalStorm
set_global report_timing_format {instance arc cell slew load delay arrival}
set_global timing_defer_mmmc_object_updates true
setDoAssign on -buffer BUFM2W
setDesignMode -process 65
Applying the recommended capacitance filtering threshold values for 65nm process node: total_c_th=0, relative_c_th=1 and coupling_c_th=0.1.
These values will be used by all post-route extraction engines, including TQRC, IQRC and QRC extraction.
Capacitance filtering mode(-capFilterMode option of the setExtractRCMode) is 'relAndCoup' for all engines.
The accuracy mode for detail extraction will be set to 'high'.
Default value for EffortLevel(-effortLevel option of the setExtractRCMode) in postRoute extraction mode will be 'medium' if QRC technology file is specified else 'low'.
win
setTrialRouteMode -useM1 true
setMultiCpuUsage -localCpu max
*** Memory pool thread-safe mode activated.
encMessage warning 0
Suppress "**WARN ..." messages.
encMessage debug 0
encMessage info 0
Reading config file - save/chip_shabziger_final2.enc.dat/shabziger_chip.conf
**WARN: (ENCLF-246): The 'UNITS' attribute should be set
in the first lef file (technology lef). There is an attempt to set it
in subsequent lef files which will be ignored.
**WARN: (ENCLF-108): There is no overlap layer defined in any lef file
so you are unable to create rectilinear partition in a hierarchical flow.
**WARN: (ENCLF-246): The 'UNITS' attribute should be set
in the first lef file (technology lef). There is an attempt to set it
in subsequent lef files which will be ignored.
**WARN: (ENCLF-246): The 'UNITS' attribute should be set
in the first lef file (technology lef). There is an attempt to set it
in subsequent lef files which will be ignored.
**WARN: (ENCLF-200): Pin 'ANAIOC' in macro 'DI_GC' has no ANTENNAGATEAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (ENCLF-200): Pin 'ANAIO' in macro 'DI_GIO' has no ANTENNAGATEAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (ENCLF-200): Pin 'ANAIOC' in macro 'DI_PC' has no ANTENNAGATEAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (ENCLF-200): Pin 'ANAIO' in macro 'DI_PIO' has no ANTENNAGATEAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (ENCLF-200): Pin 'ANAIO' in macro 'IANAIO' has no ANTENNAGATEAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (ENCLF-200): Pin 'ANAIOC' in macro 'IANAIOC' has no ANTENNAGATEAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (ENCLF-200): Pin 'A' in macro 'ANTS' has no ANTENNAGATEAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (ENCLF-200): Pin 'A' in macro 'ANTW' has no ANTENNAGATEAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (ENCLF-200): Pin 'A' in macro 'ANTR' has no ANTENNAGATEAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'OUTPUT' of cell 'ICLOCK' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_capacitance' on 'output/inout' pin 'VDD' of cell 'ICLOCK' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'VDD' of cell 'ICLOCK' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_capacitance' on 'output/inout' pin 'VSS' of cell 'ICLOCK' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'VSS' of cell 'ICLOCK' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'XO' of cell 'IOSC' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'XOUT' of cell 'IOSC' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_capacitance' on 'output/inout' pin 'VDD' of cell 'IOSC' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'VDD' of cell 'IOSC' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_capacitance' on 'output/inout' pin 'VSS' of cell 'IOSC' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'VSS' of cell 'IOSC' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_capacitance' on 'output/inout' pin 'VDDIO' of cell 'IOSC' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'VDDIO' of cell 'IOSC' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_capacitance' on 'output/inout' pin 'VSSIO' of cell 'IOSC' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'VSSIO' of cell 'IOSC' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'DI' of cell 'IUMA' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'PAD' of cell 'IUMA' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_capacitance' on 'output/inout' pin 'VDD' of cell 'IUMA' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'VDD' of cell 'IUMA' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_capacitance' on 'output/inout' pin 'VSS' of cell 'IUMA' is not defined in the library.
*** End library_loading (cpu=3.41min, mem=257.2M, fe_cpu=3.51min, fe_mem=780.1M) ***
**WARN: (ENCDB-1256): Power pin VDDIO of instance pad_DataOut15 is connected to non-p/g net VDDIO. Mark the net as power net and create associated snet.
**WARN: (ENCDB-1257): Ground pin VSSIO of instance pad_DataOut15 is connected to non-p/g net VSSIO. Mark the net as ground net and create associated snet.
Loading preference file save/chip_shabziger_final2.enc.dat/enc.pref.tcl ...
Loading mode file save/chip_shabziger_final2.enc.dat/shabziger_chip.mode ...
**WARN: (ENCEXT-1082): Option '-engine detail' is obsolete. Use '-engine postRoute [-effortLevel low]' to set extraction engine, which is based on recommended convention '-engine postRoute [-effortLevel ]'. The obsolete option still works in this release, but to avoid this warning and to ensure compatibility with future releases, update your script and configuration file to use recommended convention.
**WARN: (ENCEXT-1079): Options '-effortLevel low' and '-engine detail' are specified together. User is recommended to use either '-engine preRoute|postRoute [-effortLevel ]' or '-engine default|detail|cce|signoff' because '-engine default|detail|cce|signoff' has implicit meaning for '-effortLevel'. In this case, both the user specified options will be accepted by the tool and interpreted as '-engine postRoute -effortLevel low'
**WARN: (ENCOPT-3058): Cell uk65lscllmvbbr_108c125_wc/AD42M2RA has already a dont_use attribute false.
**WARN: (ENCOPT-3058): Cell uk65lscllmvbbh_108c125_wc/AD42M2SA has already a dont_use attribute false.
**WARN: (ENCOPT-3058): Cell uk65lscllmvbbl_108c125_wc/AD42M2WA has already a dont_use attribute false.
**WARN: (ENCOPT-3058): Cell uk65lscllmvbbr_108c125_wc/AD42M4RA has already a dont_use attribute false.
**WARN: (ENCOPT-3058): Cell uk65lscllmvbbh_108c125_wc/AD42M4SA has already a dont_use attribute false.
**WARN: (ENCOPT-3058): Cell uk65lscllmvbbl_108c125_wc/AD42M4WA has already a dont_use attribute false.
**WARN: (ENCOPT-3058): Cell uk65lscllmvbbr_108c125_wc/ADCSCM2R has already a dont_use attribute false.
**WARN: (ENCOPT-3058): Cell uk65lscllmvbbh_108c125_wc/ADCSCM2S has already a dont_use attribute false.
**WARN: (ENCOPT-3058): Cell uk65lscllmvbbl_108c125_wc/ADCSCM2W has already a dont_use attribute false.
**WARN: (ENCOPT-3058): Cell uk65lscllmvbbr_108c125_wc/ADCSCM4R has already a dont_use attribute false.
**WARN: (ENCOPT-3058): Cell uk65lscllmvbbh_108c125_wc/ADCSCM4S has already a dont_use attribute false.
**WARN: (ENCOPT-3058): Cell uk65lscllmvbbl_108c125_wc/ADCSCM4W has already a dont_use attribute false.
**WARN: (ENCOPT-3058): Cell uk65lscllmvbbr_108c125_wc/ADCSIOM2R has already a dont_use attribute false.
**WARN: (ENCOPT-3058): Cell uk65lscllmvbbh_108c125_wc/ADCSIOM2S has already a dont_use attribute false.
**WARN: (ENCOPT-3058): Cell uk65lscllmvbbl_108c125_wc/ADCSIOM2W has already a dont_use attribute false.
**WARN: (ENCOPT-3058): Cell uk65lscllmvbbr_108c125_wc/ADCSIOM4R has already a dont_use attribute false.
**WARN: (ENCOPT-3058): Cell uk65lscllmvbbh_108c125_wc/ADCSIOM4S has already a dont_use attribute false.
**WARN: (ENCOPT-3058): Cell uk65lscllmvbbl_108c125_wc/ADCSIOM4W has already a dont_use attribute false.
**WARN: (ENCOPT-3058): Cell uk65lscllmvbbr_108c125_wc/ADCSOM2R has already a dont_use attribute false.
**WARN: (ENCOPT-3058): Cell uk65lscllmvbbh_108c125_wc/ADCSOM2S has already a dont_use attribute false.
**WARN: (EMS-62): Message has exceeded the default message display limit of 20.
To avoid this warning, increase the display limit per unique message
by using the set_message_limit command.
The message limit can be removed by using the unset_message_limit command.
Note that setting a very large number using the set_message_limit command
or removing the message limit using the unset_message_limit command can
significantly increase the log file size.
To suppress a message, use suppress_message command.
**WARN: (ENCEXT-2760): Layer M9 in the cap table is larger than max number of layers, 8, defined in the LEF file.
**WARN: (ENCEXT-2771): Top layer, M9, of Via ALVIA in the cap table is larger than max number of layers, 8, defined in the LEF file.
**WARN: (ENCEXT-2710): Cap table for M9 is ignored, the layer is not defined in the design.
**WARN: (ENCEXT-2760): Layer M9 in the cap table is larger than max number of layers, 8, defined in the LEF file.
**WARN: (ENCEXT-2771): Top layer, M9, of Via ALVIA in the cap table is larger than max number of layers, 8, defined in the LEF file.
**WARN: (ENCEXT-2710): Cap table for M9 is ignored, the layer is not defined in the design.
shabziger_chip
shabziger_chip
shabziger_chip
shabziger_chip
shabziger_chip
shabziger_chip
shabziger_chip
shabziger_chip
shabziger_chip
shabziger_chip
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shabziger_chip
loading place ...
loading route ...
setOptMode -setupTargetSlack 0.06
*info: Setting setup target slack to 0.060
*info: Hold target slack is 0.000
optDesign -postroute -outDir timingReports_final -prefix shabziger.postrouteopt3
Disable merging buffers from different footprints for postRoute code for non-MSV designs
Total CPU(s) requested: 8
CPU(s) enabled with current License(s): 2
Additional license(s) checked out: 2 Encounter_Digital_Impl_Sys_XL license(s) for 6 CPU(s)
Total CPU(s) now enabled: 8
Multithreaded Timing Analysis is initialized with 8 threads
**WARN: (ENCOPT-6055): The following cells have a dont_touch property but without being dont_use.
Such configuration can impact the timing closure because they can be inserted in the netlist but never transformed again.
It is recommended that you apply a dont_use attribute on them.
Cell SYKA65_2048X32X1CM8 is dont_touch but not dont_use
Cell SHKA65_2048X32X1CM4 is dont_touch but not dont_use
Cell SHKA65_16384X32X1CM16 is dont_touch but not dont_use
...
Reporting only the 20 first cells found...
COE opt is not supported in non AAE mode. Reverting to non COE postroute flow
**optDesign ... cpu = 0:00:00, real = 0:00:00, mem = 2495.4M **
#Created 3310 library cell signatures
#Created 283804 NETS and 0 SPECIALNETS signatures
#Created 310890 instance signatures
Begin checking placement ... (start mem=2550.7M, init mem=2609.4M)
*info: Placed = 273398
*info: Unplaced = 0
Placement Density:60.38%(1138831/1886211)
Finished checkPlace (cpu: total=0:00:02.5, vio checks=0:00:00.2; mem=2574.3M)
Setting latch borrow mode to budget during optimization.
setExtractRCMode -coupled false
*** optDesign -postRoute ***
DRC Margin: user margin 0.0; extra margin 0
Setup Target Slack: user slack 0.06
Hold Target Slack: user slack 0.0
*info: Setting setup target slack to 0.060
*info: Hold target slack is 0.000
**INFO : Adding temp dont-use cells (LVT only flow version : 4)
Creating information for LVT Only Flow
Num of Buffers : 123
Num of Inverters : 105
Num of VTs : 3
Executing LVT Only Same Size Flow (setting 4)
*Info* Num dontuse cells 311
*Info* Num dontuse cells 2259
Extraction called for design 'shabziger_chip' of instances=310889 and nets=283804 using extraction engine 'postRoute' at effort level 'low' .
Detail RC Extraction called for design shabziger_chip.
RC Extraction called in multi-corner(2) mode.
Process corner(s) are loaded.
Corner: rc_worst
Corner: rc_best
extractDetailRC Option : -outfile ../tmp/shabziger_chip_HQpeam_28299.rcdb.d -extended
RC Mode: Detail [Extended CapTable, RC Table Resistances]
RC Corner Indexes 0 1
Capacitance Scaling Factor : 1.00000 1.00000
Coupling Cap. Scaling Factor : 1.00000 1.00000
Resistance Scaling Factor : 1.00000 1.00000
Clock Cap. Scaling Factor : 1.00000 1.00000
Clock Res. Scaling Factor : 1.00000 1.00000
Shrink Factor : 1.00000
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Checking LVS Completed (CPU Time= 0:00:01.1 MEM= 2501.3M)
Creating parasitic data file '../tmp/shabziger_chip_HQpeam_28299.rcdb.d/header.da' in memory efficient access mode for storing RC.
Extracted 10% (CPU Time= 0:00:06.4 MEM= 2863.3M)
Extracted 20% (CPU Time= 0:00:13.5 MEM= 2869.4M)
Extracted 30% (CPU Time= 0:00:18.5 MEM= 2891.5M)
Extracted 40.0001% (CPU Time= 0:00:28.5 MEM= 2893.5M)
Extracted 50.0001% (CPU Time= 0:00:39.8 MEM= 2924.6M)
Extracted 60.0001% (CPU Time= 0:00:48.2 MEM= 2929.6M)
Extracted 70.0001% (CPU Time= 0:01:02 MEM= 2930.6M)
Extracted 80.0001% (CPU Time= 0:01:15 MEM= 2930.6M)
Extracted 90.0001% (CPU Time= 0:01:24 MEM= 2930.6M)
Extracted 100% (CPU Time= 0:01:42 MEM= 2930.6M)
Nr. Extracted Resistors : 5597909
Nr. Extracted Ground Cap. : 5876804
Nr. Extracted Coupling Cap. : 0
Opening parasitic data file '../tmp/shabziger_chip_HQpeam_28299.rcdb.d/header.da' for reading.
Detail RC Extraction DONE (CPU Time: 0:01:45 Real Time: 0:01:46 MEM: 2516.297M)
Using new Cte TW Api base...#################################################################################
# Design Stage: PostRoute
# Design Mode: 65nm
# Analysis Mode: MMMC non-OCV
# Extraction Mode: detail/spef
# Delay Calculation Options: engine=signalStorm signOff=true SIAware=false(opt)
# Switching Delay Calculation Engine to signalStorm
#################################################################################
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:02.1, MEM = 2596.3M, InitMEM = 2590.8M)
Start delay calculation using Signal Storm (mem=2596.336M)...
Start translating cell libraries into ECSM model (MEM=2596.3M)
End translating ECSM and Loading done (CPU=0:00:17.0, MEM=2821.4M)
delayCal using detail RC...
Opening parasitic data file '../tmp/shabziger_chip_HQpeam_28299.rcdb.d/header.da' for reading.
RC Database In Completed (CPU Time= 0:00:01.9 MEM= 3010.3M)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
**WARN: (ENCTS-403): Delay calculation was forced to extrapolate table data outside of the characterized range. In some cases, extrapolation can reduce the accuracy of the delay calculation. You can enable more detailed reporting of these cases by enabling the command 'setDelayCalMode -reportOutBound'.
Delay calculation completed. (cpu=0:01:38 real=0:01:40 mem=3528.750M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.5, MEM = 3528.8M, InitMEM = 3528.8M)
Start delay calculation using Signal Storm (mem=3528.750M)...
Start translating cell libraries into ECSM model (MEM=3528.8M)
End translating ECSM and Loading done (CPU=0:00:00.1, MEM=3528.8M)
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:39.3 real=0:00:39.0 mem=3530.758M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.5, MEM = 3530.8M, InitMEM = 3530.8M)
Start delay calculation using Signal Storm (mem=3530.758M)...
Start translating cell libraries into ECSM model (MEM=3530.8M)
End translating ECSM and Loading done (CPU=0:00:00.0, MEM=3530.8M)
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:40.1 real=0:00:40.0 mem=3530.758M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.4, MEM = 3530.8M, InitMEM = 3530.8M)
Start delay calculation using Signal Storm (mem=3530.758M)...
Start translating cell libraries into ECSM model (MEM=3530.8M)
End translating ECSM and Loading done (CPU=0:00:00.0, MEM=3530.8M)
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:39.8 real=0:00:39.0 mem=3530.758M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.4, MEM = 3530.8M, InitMEM = 3530.8M)
Start delay calculation using Signal Storm (mem=3530.758M)...
Start translating cell libraries into ECSM model (MEM=3530.8M)
End translating ECSM and Loading done (CPU=0:00:00.0, MEM=3530.8M)
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:40.6 real=0:00:41.0 mem=3530.758M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.5, MEM = 3530.8M, InitMEM = 3530.8M)
Start delay calculation using Signal Storm (mem=3530.758M)...
Start translating cell libraries into ECSM model (MEM=3530.8M)
End translating ECSM and Loading done (CPU=0:00:00.1, MEM=3530.8M)
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:40.1 real=0:00:40.0 mem=3530.758M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.3, MEM = 3530.8M, InitMEM = 3530.8M)
Start delay calculation using Signal Storm (mem=3530.758M)...
Start translating cell libraries into ECSM model (MEM=3530.8M)
End translating ECSM and Loading done (CPU=0:00:00.1, MEM=3530.8M)
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:40.6 real=0:00:40.0 mem=3530.758M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.5, MEM = 3530.8M, InitMEM = 3530.8M)
Start delay calculation using Signal Storm (mem=3530.758M)...
Start translating cell libraries into ECSM model (MEM=3530.8M)
End translating ECSM and Loading done (CPU=0:00:00.1, MEM=3530.8M)
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:40.5 real=0:00:40.0 mem=3531.762M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.5, MEM = 3531.8M, InitMEM = 3531.8M)
Start delay calculation using Signal Storm (mem=3531.762M)...
Start translating cell libraries into ECSM model (MEM=3531.8M)
End translating ECSM and Loading done (CPU=0:00:00.0, MEM=3531.8M)
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:43.5 real=0:00:43.0 mem=3531.762M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.4, MEM = 3531.8M, InitMEM = 3531.8M)
Start delay calculation using Signal Storm (mem=3531.762M)...
Start translating cell libraries into ECSM model (MEM=3531.8M)
End translating ECSM and Loading done (CPU=0:00:00.1, MEM=3531.8M)
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:42.2 real=0:00:42.0 mem=3531.762M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.5, MEM = 3531.8M, InitMEM = 3531.8M)
Start delay calculation using Signal Storm (mem=3531.762M)...
Start translating cell libraries into ECSM model (MEM=3531.8M)
End translating ECSM and Loading done (CPU=0:00:00.1, MEM=3531.8M)
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:43.4 real=0:00:43.0 mem=3532.766M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.4, MEM = 3532.8M, InitMEM = 3532.8M)
Start delay calculation using Signal Storm (mem=3532.766M)...
Start translating cell libraries into ECSM model (MEM=3532.8M)
End translating ECSM and Loading done (CPU=0:00:00.1, MEM=3532.8M)
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:42.3 real=0:00:42.0 mem=3533.770M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.4, MEM = 3533.8M, InitMEM = 3533.8M)
Start delay calculation using Signal Storm (mem=3533.770M)...
Start translating cell libraries into ECSM model (MEM=3533.8M)
End translating ECSM and Loading done (CPU=0:00:00.0, MEM=3533.8M)
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:44.5 real=0:00:45.0 mem=3535.777M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.5, MEM = 3535.8M, InitMEM = 3535.8M)
Start delay calculation using Signal Storm (mem=3535.777M)...
Start translating cell libraries into ECSM model (MEM=3535.8M)
End translating ECSM and Loading done (CPU=0:00:00.0, MEM=3535.8M)
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:42.7 real=0:00:42.0 mem=3535.777M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.3, MEM = 3535.8M, InitMEM = 3535.8M)
Start delay calculation using Signal Storm (mem=3535.777M)...
Start translating cell libraries into ECSM model (MEM=3535.8M)
End translating ECSM and Loading done (CPU=0:00:00.0, MEM=3535.8M)
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:42.8 real=0:00:42.0 mem=3535.777M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.4, MEM = 3535.8M, InitMEM = 3535.8M)
Start delay calculation using Signal Storm (mem=3535.777M)...
Start translating cell libraries into ECSM model (MEM=3535.8M)
End translating ECSM and Loading done (CPU=0:00:00.0, MEM=3535.8M)
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:42.9 real=0:00:43.0 mem=3535.777M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.5, MEM = 3535.8M, InitMEM = 3535.8M)
Start delay calculation using Signal Storm (mem=3535.777M)...
Start translating cell libraries into ECSM model (MEM=3535.8M)
End translating ECSM and Loading done (CPU=0:00:00.0, MEM=3535.8M)
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:54.2 real=0:00:55.0 mem=3535.777M 0)
*** CDM Built up (cpu=0:14:35 real=0:14:36 mem= 3528.8M) ***
-holdSdfFile {} # string, default=""
-holdSdfScript {} # string, default="", private
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
Initial Summary
------------------------------------------------------------
+--------------------+---------+
| Setup mode | all |
+--------------------+---------+
| WNS (ns):| -0.105 |
| TNS (ns):| -55.529 |
| Violating Paths:| 1606 |
| All Paths:| 85005 |
+--------------------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 1 (5) | -0.001 | 1 (5) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 60.377%
------------------------------------------------------------
**optDesign ... cpu = 0:19:07, real = 0:19:09, mem = 3976.3M **
*info: Start fixing DRV (Mem = 4013.21M) ...
*info: Options = -postRoute -maxCap -maxTran -noMaxFanout -noSensitivity -backward -maxIter 1
*info: Start fixing DRV iteration 1 ...
*** Starting dpFixDRCViolation (4013.3M)
*info: 40 io nets excluded
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
*info: 567 clock nets excluded
*info: 4 special nets excluded.
*info: 2406 no-driver nets excluded.
*info: 21 multi-driver nets excluded.
*info: There are 60 candidate Buffer cells
*info: There are 52 candidate Inverter cells
Initializing placement sections/sites ...
Density before buffering = 0.603766
Start fixing design rules ... (0:00:06.2 4158.9M)
All-RC-Corners-Per-Net-In-Memory is turned ON...
Closing parasitic data file '../tmp/shabziger_chip_HQpeam_28299.rcdb.d'. 4618485 times net's RC data read were performed.
Opening parasitic data file '../tmp/shabziger_chip_HQpeam_28299.rcdb.d/header.da' for reading.
RC Database In Completed (CPU Time= 0:00:02.1 MEM= 4035.5M)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Topological Sorting (CPU = 0:00:01.4, MEM = 4191.8M, InitMEM = 4191.8M)
Done fixing design rule (0:01:24 4124.4M)
Summary:
1 buffer added on 1 net (with 0 driver resized)
Density after buffering = 0.603768
Starting refinePlace ...
move report: placeLevelShifters moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Spread Effort: high, post-route mode.
Finished Phase I. CPU Time = 0:00:26.1, Real Time = 0:00:26.0
move report: preRPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: rPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: overall moves 0 insts, mean move: 0.00 um, max move: 0.00 um
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 0.00 um
mean (X+Y) = 0.00 um
Total instances moved : 0
*** cpu=0:00:29.0 mem=4141.6M mem(used)=128.0M***
*** Completed dpFixDRCViolation (0:01:57 4099.1M)
End of fixDrcViolation iteration 1.
*** Starting dpFixDRCViolation (4099.1M)
*info: 40 io nets excluded
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
*info: 567 clock nets excluded
*info: 4 special nets excluded.
*info: 2406 no-driver nets excluded.
*info: 21 multi-driver nets excluded.
Start fixing design rules ... (0:00:06.1 4246.3M)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Done fixing design rule (0:01:12 4183.8M)
Summary:
0 buffer added on 0 net (with 0 driver resized)
Density after buffering = 0.603768
*** Completed dpFixDRCViolation (0:01:13 4099.1M)
*info:
*info: Completed fixing DRV (CPU Time = 0:03:39, Mem = 4099.05M).
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
Summary (cpu=3.66min real=3.65min mem=4099.1M)
------------------------------------------------------------
+--------------------+---------+
| Setup mode | all |
+--------------------+---------+
| WNS (ns):| -0.105 |
| TNS (ns):| -55.523 |
| Violating Paths:| 1606 |
| All Paths:| 85005 |
+--------------------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 0 (0) | 0.000 | 0 (0) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 60.377%
------------------------------------------------------------
**optDesign ... cpu = 0:23:47, real = 0:23:49, mem = 4099.3M **
*** Timing NOT met, worst failing slack is -0.105
*** Check timing (0:00:01.0)
*** Timing NOT met, worst failing slack is -0.105
*** Check timing (0:00:00.1)
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
Info: 40 io nets excluded
Info: 567 clock nets excluded from IPO operation.
*** Start Post Route Setup Fixing (cpu=0:00:00.0 mem=3962.2M) ***
Time Engine : CTE
SSTA Mode : off
MMMC mode : on (11 dominant view(s), 6 view(s) pruned)
Incr. DC : on
Incr POM Mode : on
On Demand POM Mode : on
CTE SubNetWork Mode : on
Up Size : on
Down Size : on
Resize FFs : on
Add Buffer : off
Del Buffer : off
Pin Swap : off
Add InvPair : off
LegalLoc GS : off
Speedup GS : off
Crit. Range : 20%
density before = 60.377%
total 280832 net, 39 ipo_ignored
total 951949 term, 78 ipo_ignored
total 289676 comb inst, 37273 fixed, 273 dont_touch, 36923 no_footp
total 21214 seq inst, 18 fixed, 3 dont_touch, 3 no_footp
total 240 footprint(s)
10 footprint(s) with 0 cell(s)
36 footprint(s) with 1 cell(s)
16 footprint(s) with 2 cell(s)
3 footprint(s) with 3 cell(s)
119 footprint(s) with 4 cell(s)
13 footprint(s) with 5 cell(s)
13 footprint(s) with 6 cell(s)
13 footprint(s) with 7 cell(s)
7 footprint(s) with 8 cell(s)
1 footprint(s) with 9 cell(s)
9 footprint(s) with 10+ cell(s)
Estimated WNS = -0.166ns, TNS = -243.396ns (targetSlack +0.060ns) (cpu=0:00:23.6 mem=4071.1M)
Iter 0 ...
Collected 96198 nets for fixing
Evaluate 750(1008) resize, Select 128 cand. (cpu=0:00:54.2 mem=4077.6M)
Commit 20 cand, 19 upSize, 1 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:00:57.6 mem=4080.1M)
Calc. DC (cpu=0:00:58.1 mem=4080.1M) ***
Estimated WNS = -0.137ns, TNS = -240.291ns (targetSlack +0.060ns) (cpu=0:01:12 mem=4080.1M)
Iter 1 ...
Collected 96082 nets for fixing
Evaluate 750(1879) resize, Select 350 cand. (cpu=0:01:50 mem=4081.3M)
Commit 20 cand, 15 upSize, 5 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:01:55 mem=4081.8M)
Calc. DC (cpu=0:01:55 mem=4081.8M) ***
Estimated WNS = -0.133ns, TNS = -240.000ns (targetSlack +0.060ns) (cpu=0:02:09 mem=4081.8M)
Iter 2 ...
Collected 96060 nets for fixing
Evaluate 754(1932) resize, Select 115 cand. (cpu=0:02:47 mem=4084.1M)
Commit 17 cand, 16 upSize, 1 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:02:48 mem=4084.4M)
Calc. DC (cpu=0:02:49 mem=4084.4M) ***
Estimated WNS = -0.132ns, TNS = -239.805ns (targetSlack +0.060ns) (cpu=0:03:03 mem=4084.4M)
Iter 3 ...
Collected 96046 nets for fixing
Evaluate 751(1556) resize, Select 305 cand. (cpu=0:03:34 mem=4085.4M)
Commit 18 cand, 12 upSize, 6 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:03:36 mem=4087.8M)
Calc. DC (cpu=0:03:36 mem=4087.8M) ***
Estimated WNS = -0.131ns, TNS = -239.631ns (targetSlack +0.060ns) (cpu=0:03:50 mem=4087.8M)
Iter 4 ...
Collected 96042 nets for fixing
Evaluate 763(1993) resize, Select 107 cand. (cpu=0:04:28 mem=4088.8M)
Commit 11 cand, 8 upSize, 3 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:04:28 mem=4088.1M)
Calc. DC (cpu=0:04:29 mem=4088.1M) ***
Estimated WNS = -0.130ns, TNS = -239.537ns (targetSlack +0.060ns) (cpu=0:04:43 mem=4088.1M)
Iter 5 ...
Collected 96040 nets for fixing
Evaluate 755(2485) resize, Select 339 cand. (cpu=0:05:26 mem=4089.1M)
Commit 23 cand, 16 upSize, 5 downSize, 2 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:05:29 mem=4090.4M)
Calc. DC (cpu=0:05:29 mem=4090.4M) ***
Estimated WNS = -0.129ns, TNS = -239.475ns (targetSlack +0.060ns) (cpu=0:05:43 mem=4090.4M)
Iter 6 ...
Collected 96042 nets for fixing
Evaluate 765(2884) resize, Select 149 cand. (cpu=0:06:38 mem=4092.6M)
Commit 31 cand, 25 upSize, 6 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:06:41 mem=4092.9M)
Calc. DC (cpu=0:06:42 mem=4092.9M) ***
Estimated WNS = -0.128ns, TNS = -239.137ns (targetSlack +0.060ns) (cpu=0:06:55 mem=4092.9M)
Iter 7 ...
Collected 96003 nets for fixing
Evaluate 753(2845) resize, Select 399 cand. (cpu=0:07:44 mem=4094.0M)
Commit 30 cand, 20 upSize, 9 downSize, 1 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:07:48 mem=4098.4M)
Calc. DC (cpu=0:07:49 mem=4098.4M) ***
Estimated WNS = -0.128ns, TNS = -238.870ns (targetSlack +0.060ns) (cpu=0:08:03 mem=4098.4M)
Iter 8 ...
Collected 95996 nets for fixing
Evaluate 751(2753) resize, Select 134 cand. (cpu=0:08:50 mem=4100.5M)
Commit 18 cand, 14 upSize, 4 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:08:52 mem=4100.6M)
Calc. DC (cpu=0:08:53 mem=4100.6M) ***
Estimated WNS = -0.128ns, TNS = -238.738ns (targetSlack +0.060ns) (cpu=0:09:07 mem=4100.6M)
Iter 9 ...
Collected 95995 nets for fixing
Evaluate 757(2970) resize, Select 379 cand. (cpu=0:09:54 mem=4102.0M)
Commit 27 cand, 14 upSize, 11 downSize, 2 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:10:00 mem=4103.3M)
Calc. DC (cpu=0:10:01 mem=4103.3M) ***
Estimated WNS = -0.128ns, TNS = -238.227ns (targetSlack +0.060ns) (cpu=0:10:15 mem=4103.3M)
Iter 10 ...
Collected 95851 nets for fixing
Evaluate 751(5988) resize, Select 148 cand. (cpu=0:11:59 mem=4104.3M)
Commit 22 cand, 22 upSize, 0 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:12:02 mem=4106.5M)
Calc. DC (cpu=0:12:02 mem=4106.5M) ***
Estimated WNS = -0.127ns, TNS = -238.074ns (targetSlack +0.060ns) (cpu=0:12:17 mem=4106.5M)
Iter 11 ...
Collected 95837 nets for fixing
Evaluate 752(2937) resize, Select 363 cand. (cpu=0:13:05 mem=4107.6M)
Commit 24 cand, 12 upSize, 11 downSize, 1 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:13:10 mem=4108.6M)
Calc. DC (cpu=0:13:11 mem=4108.6M) ***
Estimated WNS = -0.126ns, TNS = -237.844ns (targetSlack +0.060ns) (cpu=0:13:26 mem=4108.6M)
Iter 12 ...
Collected 95816 nets for fixing
Evaluate 750(2746) resize, Select 148 cand. (cpu=0:14:11 mem=4109.7M)
Commit 28 cand, 22 upSize, 4 downSize, 2 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:14:16 mem=4113.0M)
Calc. DC (cpu=0:14:17 mem=4113.0M) ***
Estimated WNS = -0.126ns, TNS = -236.877ns (targetSlack +0.060ns) (cpu=0:14:31 mem=4113.0M)
Iter 13 ...
Collected 95686 nets for fixing
Evaluate 750(2985) resize, Select 374 cand. (cpu=0:15:21 mem=4114.1M)
Commit 30 cand, 19 upSize, 11 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:15:26 mem=4115.2M)
Calc. DC (cpu=0:15:27 mem=4115.2M) ***
Estimated WNS = -0.126ns, TNS = -236.598ns (targetSlack +0.060ns) (cpu=0:15:40 mem=4115.2M)
Iter 14 ...
Collected 95663 nets for fixing
Evaluate 750(6092) resize, Select 140 cand. (cpu=0:17:20 mem=4116.5M)
Commit 20 cand, 19 upSize, 1 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:17:22 mem=4116.6M)
Calc. DC (cpu=0:17:23 mem=4116.6M) ***
Estimated WNS = -0.126ns, TNS = -236.470ns (targetSlack +0.060ns) (cpu=0:17:37 mem=4116.6M)
Calc. DC (cpu=0:17:37 mem=4116.6M) ***
*summary: 339 instances changed cell type
density after = 60.406%
*** Finish Post Route Setup Fixing (cpu=0:17:41 mem=4030.5M) ***
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
Info: 40 io nets excluded
Info: 567 clock nets excluded from IPO operation.
*** Start Post Route Setup Fixing (cpu=0:00:00.0 mem=4030.5M) ***
Time Engine : CTE
SSTA Mode : off
MMMC mode : on (11 dominant view(s), 6 view(s) pruned)
Incr. DC : on
Incr POM Mode : on
On Demand POM Mode : on
CTE SubNetWork Mode : on
Up Size : on
Down Size : on
Resize FFs : on
Add Buffer : on
Del Buffer : on
Pin Swap : off
Add InvPair : off
LegalLoc GS : off
Speedup GS : off
Crit. Range : 20%
density before = 60.406%
total 280832 net, 39 ipo_ignored
total 951949 term, 78 ipo_ignored
total 289676 comb inst, 37273 fixed, 273 dont_touch, 36923 no_footp
total 21214 seq inst, 18 fixed, 3 dont_touch, 3 no_footp
total 240 footprint(s)
10 footprint(s) with 0 cell(s)
36 footprint(s) with 1 cell(s)
16 footprint(s) with 2 cell(s)
3 footprint(s) with 3 cell(s)
119 footprint(s) with 4 cell(s)
13 footprint(s) with 5 cell(s)
13 footprint(s) with 6 cell(s)
13 footprint(s) with 7 cell(s)
7 footprint(s) with 8 cell(s)
1 footprint(s) with 9 cell(s)
9 footprint(s) with 10+ cell(s)
BUFFER FOOTPRINT (BUFM2S) :
CKBUFM1S(s) CKBUFM2S(s) BUFM2S(s) CKBUFM3S(s) BUFM3S(s)
CKBUFM4S(s) BUFM4S(s) BUFM5S(s) CKBUFM6S(s) BUFM6S(s)
CKBUFM8S(s) BUFM8S(s) BUFM10S(s) CKBUFM12S(s) BUFM12S(s)
BUFM14S(s) CKBUFM16S(s) BUFM16S(s) BUFM18S(s) CKBUFM20S(s)
BUFM20S(s) CKBUFM22SA(s) BUFM22SA(s) CKBUFM24S(s) BUFM24S(s)
CKBUFM26SA(s) BUFM26SA(s) CKBUFM32S(s) BUFM32SA(s) CKBUFM40S(s)
BUFM40SA(s) CKBUFM48S(s) BUFM48SA(s) DEL1M1W(s) CKBUFM1W
BUFM2W CKBUFM2W CKBUFM3W(s) BUFM3W(s) CKBUFM4W
BUFM4W DEL1M4W(s) BUFM5W(s) CKBUFM6W BUFM6W
CKBUFM8W BUFM8W BUFM10W CKBUFM12W BUFM12W
BUFM14W CKBUFM16W BUFM16W BUFM18W CKBUFM20W
BUFM20W CKBUFM22WA BUFM22WA CKBUFM24W BUFM24W
CKBUFM26WA BUFM26WA CKBUFM32W BUFM32WA CKBUFM40W
BUFM40WA CKBUFM48W BUFM48WA CKBUFM1R(s) BUFM2R(s)
CKBUFM2R(s) CKBUFM3R(s) BUFM3R(s) CKBUFM4R(s) BUFM4R(s)
DEL1M4R(s) BUFM5R(s) CKBUFM6R(s) BUFM6R(s) CKBUFM8R(s)
BUFM8R(s) BUFM10R(s) CKBUFM12R(s) BUFM12R(s) BUFM14R(s)
CKBUFM16R(s) BUFM16R(s) BUFM18R(s) CKBUFM20R(s) BUFM20R(s)
CKBUFM22RA(s) BUFM22RA(s) CKBUFM24R(s) BUFM24R(s) CKBUFM26RA(s)
BUFM26RA(s) CKBUFM32R(s) BUFM32RA(s) CKBUFM40R(s) BUFM40RA(s)
CKBUFM48R(s) BUFM48RA(s)
DELAY FOOTPRINT (DEL1M1S) :
DEL4M1S DEL3M1S DEL2M1S DEL1M1S DEL4M4S
DEL3M4S DEL2M4S DEL1M4S DEL4M1W DEL3M1W
DEL2M1W DEL4M4W DEL3M4W DEL2M4W DEL4M1R
DEL3M1R DEL2M1R DEL1M1R DEL4M4R DEL3M4R
DEL2M4R
Estimated WNS = -0.126ns, TNS = -236.470ns (targetSlack +0.060ns) (cpu=0:00:24.2 mem=4121.7M)
Iter 0 ...
Collected 95653 nets for fixing
Evaluate 755(1733) resize, Select 145 cand. (cpu=0:00:59.8 mem=4127.7M)
Evaluate 23(2850) addBuf, Select 3 cand. (cpu=0:01:12 mem=4164.6M)
Evaluate 101(101) delBuf, Select 4 cand. (cpu=0:01:13 mem=4165.6M)
Commit 26 cand, 20 upSize, 1 downSize, 1 sameSize, 2 addBuf, 2 delBuf, 0 pinSwap (cpu=0:01:15 mem=4242.0M)
Calc. DC (cpu=0:01:17 mem=4242.0M) ***
Estimated WNS = -0.125ns, TNS = -236.326ns (targetSlack +0.060ns) (cpu=0:01:31 mem=4242.0M)
Iter 1 ...
Collected 95623 nets for fixing
Evaluate 765(2766) resize, Select 338 cand. (cpu=0:02:19 mem=4243.1M)
Evaluate 40(3744) addBuf, Select 8 cand. (cpu=0:02:38 mem=4243.1M)
Evaluate 101(101) delBuf, Select 0 cand. (cpu=0:02:39 mem=4244.1M)
Commit 36 cand, 22 upSize, 9 downSize, 1 sameSize, 4 addBuf, 0 delBuf, 0 pinSwap (cpu=0:02:43 mem=4245.6M)
Calc. DC (cpu=0:02:45 mem=4245.6M) ***
Estimated WNS = -0.125ns, TNS = -236.024ns (targetSlack +0.060ns) (cpu=0:03:00 mem=4245.6M)
*summary: 54 instances changed cell type
density after = 60.412%
*** Finish Post Route Setup Fixing (cpu=0:03:01 mem=4149.4M) ***
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
*** Timing NOT met, worst failing slack is -0.065
*** Check timing (0:00:00.5)
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
Info: 40 io nets excluded
Info: 567 clock nets excluded from IPO operation.
*** Start Post Route Setup Fixing (cpu=0:00:00.0 mem=4140.7M) ***
Time Engine : CTE
SSTA Mode : off
MMMC mode : on (11 dominant view(s), 6 view(s) pruned)
Incr. DC : on
Incr POM Mode : on
On Demand POM Mode : on
CTE SubNetWork Mode : on
Up Size : on
Down Size : on
Resize FFs : on
Add Buffer : off
Del Buffer : off
Pin Swap : off
Add InvPair : off
LegalLoc GS : off
Speedup GS : off
Crit. Range : 20%
density before = 60.412%
total 280836 net, 39 ipo_ignored
total 951957 term, 78 ipo_ignored
total 289680 comb inst, 37273 fixed, 273 dont_touch, 36923 no_footp
total 21214 seq inst, 18 fixed, 3 dont_touch, 3 no_footp
total 240 footprint(s)
10 footprint(s) with 0 cell(s)
36 footprint(s) with 1 cell(s)
16 footprint(s) with 2 cell(s)
3 footprint(s) with 3 cell(s)
119 footprint(s) with 4 cell(s)
13 footprint(s) with 5 cell(s)
13 footprint(s) with 6 cell(s)
13 footprint(s) with 7 cell(s)
7 footprint(s) with 8 cell(s)
1 footprint(s) with 9 cell(s)
9 footprint(s) with 10+ cell(s)
Estimated WNS = -0.125ns, TNS = -236.024ns (targetSlack +0.060ns) (cpu=0:00:24.4 mem=4237.6M)
Iter 0 ...
Collected 95614 nets for fixing
Evaluate 762(2490) resize, Select 137 cand. (cpu=0:01:08 mem=4244.7M)
Commit 22 cand, 20 upSize, 2 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:01:10 mem=4245.2M)
Calc. DC (cpu=0:01:11 mem=4245.2M) ***
Estimated WNS = -0.125ns, TNS = -235.921ns (targetSlack +0.060ns) (cpu=0:01:25 mem=4245.2M)
Iter 1 ...
Collected 95611 nets for fixing
Evaluate 754(2916) resize, Select 310 cand. (cpu=0:02:11 mem=4247.2M)
Commit 25 cand, 16 upSize, 8 downSize, 1 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:02:15 mem=4247.6M)
Calc. DC (cpu=0:02:16 mem=4247.6M) ***
Estimated WNS = -0.125ns, TNS = -235.788ns (targetSlack +0.060ns) (cpu=0:02:30 mem=4247.6M)
Iter 2 ...
Collected 95606 nets for fixing
Evaluate 750(2365) resize, Select 103 cand. (cpu=0:03:18 mem=4249.7M)
Commit 13 cand, 11 upSize, 2 downSize, 0 sameSize, 0 addBuf, 0 delBuf, 0 pinSwap (cpu=0:03:19 mem=4251.0M)
Calc. DC (cpu=0:03:19 mem=4251.0M) ***
Estimated WNS = -0.125ns, TNS = -235.734ns (targetSlack +0.060ns) (cpu=0:03:34 mem=4251.0M)
Calc. DC (cpu=0:03:34 mem=4251.0M) ***
*summary: 60 instances changed cell type
density after = 60.417%
*** Finish Post Route Setup Fixing (cpu=0:03:35 mem=4144.8M) ***
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
Info: 40 io nets excluded
Info: 567 clock nets excluded from IPO operation.
*** Start Post Route Setup Fixing (cpu=0:00:00.0 mem=4144.8M) ***
Time Engine : CTE
SSTA Mode : off
MMMC mode : on (11 dominant view(s), 6 view(s) pruned)
Incr. DC : on
Incr POM Mode : on
On Demand POM Mode : on
CTE SubNetWork Mode : on
Up Size : on
Down Size : on
Resize FFs : on
Add Buffer : on
Del Buffer : on
Pin Swap : off
Add InvPair : off
LegalLoc GS : off
Speedup GS : off
Crit. Range : 20%
density before = 60.417%
total 280836 net, 39 ipo_ignored
total 951957 term, 78 ipo_ignored
total 289680 comb inst, 37273 fixed, 273 dont_touch, 36923 no_footp
total 21214 seq inst, 18 fixed, 3 dont_touch, 3 no_footp
total 240 footprint(s)
10 footprint(s) with 0 cell(s)
36 footprint(s) with 1 cell(s)
16 footprint(s) with 2 cell(s)
3 footprint(s) with 3 cell(s)
119 footprint(s) with 4 cell(s)
13 footprint(s) with 5 cell(s)
13 footprint(s) with 6 cell(s)
13 footprint(s) with 7 cell(s)
7 footprint(s) with 8 cell(s)
1 footprint(s) with 9 cell(s)
9 footprint(s) with 10+ cell(s)
BUFFER FOOTPRINT (BUFM2S) :
CKBUFM1S(s) CKBUFM2S(s) BUFM2S(s) CKBUFM3S(s) BUFM3S(s)
CKBUFM4S(s) BUFM4S(s) BUFM5S(s) CKBUFM6S(s) BUFM6S(s)
CKBUFM8S(s) BUFM8S(s) BUFM10S(s) CKBUFM12S(s) BUFM12S(s)
BUFM14S(s) CKBUFM16S(s) BUFM16S(s) BUFM18S(s) CKBUFM20S(s)
BUFM20S(s) CKBUFM22SA(s) BUFM22SA(s) CKBUFM24S(s) BUFM24S(s)
CKBUFM26SA(s) BUFM26SA(s) CKBUFM32S(s) BUFM32SA(s) CKBUFM40S(s)
BUFM40SA(s) CKBUFM48S(s) BUFM48SA(s) DEL1M1W(s) CKBUFM1W
BUFM2W CKBUFM2W CKBUFM3W(s) BUFM3W(s) CKBUFM4W
BUFM4W DEL1M4W(s) BUFM5W(s) CKBUFM6W BUFM6W
CKBUFM8W BUFM8W BUFM10W CKBUFM12W BUFM12W
BUFM14W CKBUFM16W BUFM16W BUFM18W CKBUFM20W
BUFM20W CKBUFM22WA BUFM22WA CKBUFM24W BUFM24W
CKBUFM26WA BUFM26WA CKBUFM32W BUFM32WA CKBUFM40W
BUFM40WA CKBUFM48W BUFM48WA CKBUFM1R(s) BUFM2R(s)
CKBUFM2R(s) CKBUFM3R(s) BUFM3R(s) CKBUFM4R(s) BUFM4R(s)
DEL1M4R(s) BUFM5R(s) CKBUFM6R(s) BUFM6R(s) CKBUFM8R(s)
BUFM8R(s) BUFM10R(s) CKBUFM12R(s) BUFM12R(s) BUFM14R(s)
CKBUFM16R(s) BUFM16R(s) BUFM18R(s) CKBUFM20R(s) BUFM20R(s)
CKBUFM22RA(s) BUFM22RA(s) CKBUFM24R(s) BUFM24R(s) CKBUFM26RA(s)
BUFM26RA(s) CKBUFM32R(s) BUFM32RA(s) CKBUFM40R(s) BUFM40RA(s)
CKBUFM48R(s) BUFM48RA(s)
DELAY FOOTPRINT (DEL1M1S) :
DEL4M1S DEL3M1S DEL2M1S DEL1M1S DEL4M4S
DEL3M4S DEL2M4S DEL1M4S DEL4M1W DEL3M1W
DEL2M1W DEL4M4W DEL3M4W DEL2M4W DEL4M1R
DEL3M1R DEL2M1R DEL1M1R DEL4M4R DEL3M4R
DEL2M4R
Estimated WNS = -0.125ns, TNS = -235.734ns (targetSlack +0.060ns) (cpu=0:00:23.5 mem=4244.8M)
Iter 0 ...
Collected 95596 nets for fixing
Evaluate 751(1615) resize, Select 142 cand. (cpu=0:00:55.6 mem=4250.8M)
Evaluate 24(2909) addBuf, Select 3 cand. (cpu=0:01:08 mem=4250.8M)
Evaluate 101(101) delBuf, Select 1 cand. (cpu=0:01:09 mem=4250.8M)
Commit 15 cand, 13 upSize, 1 downSize, 0 sameSize, 0 addBuf, 1 delBuf, 0 pinSwap (cpu=0:01:10 mem=4251.1M)
Calc. DC (cpu=0:01:12 mem=4251.1M) ***
Estimated WNS = -0.125ns, TNS = -235.646ns (targetSlack +0.060ns) (cpu=0:01:26 mem=4251.1M)
*summary: 14 instances changed cell type
density after = 60.420%
*** Finish Post Route Setup Fixing (cpu=0:01:27 mem=4174.1M) ***
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
*** Timing NOT met, worst failing slack is -0.065
*** Check timing (0:00:00.4)
Starting refinePlace ...
Spread Effort: high, post-route mode.
Finished Phase I. CPU Time = 0:00:31.7, Real Time = 0:00:32.0
move report: preRPlace moves 2455 insts, mean move: 0.83 um, max move: 4.80 um
max move on inst (top/i_gmu_groestl/U10741): (229.60, 256.80) --> (230.80, 260.40)
move report: rPlace moves 0 insts, mean move: 0.00 um, max move: 0.00 um
move report: overall moves 2455 insts, mean move: 0.83 um, max move: 4.80 um
max move on inst (top/i_gmu_groestl/U10741): (229.60, 256.80) --> (230.80, 260.40)
Statistics of distance of Instance movement in detailed placement:
maximum (X+Y) = 4.80 um
inst (top/i_gmu_groestl/U10741) with max move: (229.6, 256.8) -> (230.8, 260.4)
mean (X+Y) = 0.83 um
Total instances moved : 2455
*** cpu=0:00:34.6 mem=3968.5M mem(used)=10.7M***
Total net length = 1.413e+07 (6.600e+06 7.531e+06) (ext = 0.000e+00)
default core: bins with density > 0.75 = 24.6 % ( 1908 / 7744 )
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
Summary (cpu=28.98min real=28.98min mem=3961.9M)
------------------------------------------------------------
+--------------------+---------+
| Setup mode | all |
+--------------------+---------+
| WNS (ns):| -0.065 |
| TNS (ns):| -50.813 |
| Violating Paths:| 1570 |
| All Paths:| 84974 |
+--------------------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 0 (0) | 0.000 | 0 (0) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 60.420%
------------------------------------------------------------
**optDesign ... cpu = 0:55:28, real = 0:55:30, mem = 4259.7M **
*** Timing NOT met, worst failing slack is -0.065
*** Check timing (0:00:00.2)
setClockDomains -fromType register -toType register
**WARN: (ENCCTE-318): Paths not in the reg2reg domain will be added 1000ns slack adjustment
*** Timing NOT met, worst failing slack is -0.065
*** Check timing (0:02:38)
Active setup views: dummy_slow_view ethz_blake_slow_view ethz_groestl_slow_view ethz_jh_slow_view ethz_keccak_slow_view ethz_sha2_slow_view ethz_skein_slow_view gmu_blake_slow_view gmu_groestl_slow_view gmu_jh_slow_view gmu_keccak_slow_view gmu_sha2_slow_view gmu_skein_slow_view ram1_slow_view ram2_slow_view ram3_slow_view test_slow_view
Active hold views: hold_fast_view
-routeWithEco false # bool, default=false, user setting
-routeWithEco true # bool, default=false, user setting
-routeSelectedNetOnly false # bool, default=false
-routeWithTimingDriven true # bool, default=false, user setting
-routeWithTimingDriven false # bool, default=false, user setting
-routeWithSiDriven false # bool, default=false, user setting
-drouteStartIteration 0 # int, default=0, user setting
-drouteStartIteration 0 # int, default=0
globalDetailRoute
#Start globalDetailRoute on Fri Sep 30 15:00:42 2011
#
Closing parasitic data file '../tmp/shabziger_chip_HQpeam_28299.rcdb.d'. 358991 times net's RC data read were performed.
#cpu time = 00:00:00, elapsed time = 00:00:00, memory = 3963.00 (Mb)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_49 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_48 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_47 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_46 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_45 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_44 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_43 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_42 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_41 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_40 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_39 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_38 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_37 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_36 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_35 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_34 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_33 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_32 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34) Power/Ground pin VSSIO of instance fillperi_N_31 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (NRIG-34 Repeated 20 times. Will be suppressed.) Power/Ground pin VSSIO of instance fillperi_N_30 is not connected to any power/ground net. Use command globalNetConnect to connect the power/ground pin to a power/ground net.
#WARNING (EMS-27) Message (NRIG-34) has exceeded the current message display limit of 20.
#To increase the message display limit, refer to the product command reference manual.
#WARNING (NRDB-733) PIN AlgSelxSI[0] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN AlgSelxSI[1] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN AlgSelxSI[2] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN AlgSelxSI[3] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN ClkDxCI in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN ClkxCI in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN CoreScanEnxTI in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN CoreScanInxTI in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[0] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[10] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[11] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[12] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[13] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[14] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[15] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[1] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[2] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[3] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733) PIN DataOutxDO[4] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (NRDB-733 Repeated 20 times. Will be suppressed.) PIN DataOutxDO[5] in CELL_VIEW shabziger_chip,init does not have physical port
#WARNING (EMS-27) Message (NRDB-733) has exceeded the current message display limit of 20.
#To increase the message display limit, refer to the product command reference manual.
#NanoRoute Version v10.12-s010 NR110720-1815/10_10_USR2-UB
#Loading the last recorded routing design signature
#Created 7 NETS and 0 SPECIALNETS new signatures
#Summary of the placement changes since last routing:
# Number of instances added (including moved) = 2363
# Number of instances deleted (including moved) = 2359
# Number of instances resized = 302
# Number of instances with same cell size swap = 1
# Number of instances with pin swaps = 7
# Total number of placement changes (moved instances are counted twice) = 5024
#Using multithreading with 8 threads.
# ME1 H Track-Pitch = 0.200 Line-2-Via Pitch = 0.185
# ME2 V Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME3 H Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME4 V Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME5 H Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME6 V Track-Pitch = 0.200 Line-2-Via Pitch = 0.200
# ME7 H Track-Pitch = 0.400 Line-2-Via Pitch = 0.400
# ME8 V Track-Pitch = 4.000 Line-2-Via Pitch = 4.000
#Merging special wires using 8 threads...
#WARNING (NRDB-1005) Can not establish connection to PIN A2 at (512.540 547.475) on ME1 for NET top/Core10InxD[59]. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN A2 at (572.940 428.675) on ME1 for NET top/Core10InxD[87]. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN Z at (1272.650 1314.295) on ME1 for NET top/Core13InxD[180]. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN Z at (1203.130 1191.890) on ME1 for NET top/Core13InxD[188]. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN NA at (1193.955 1192.420) on ME1 for NET top/Core13InxD[357]. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (332.295 250.710) on ME1 for NET top/CoreClkxC_10___L4_N1. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (219.910 639.510) on ME1 for NET top/CoreClkxC_10___L4_N13. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (178.095 471.690) on ME1 for NET top/CoreClkxC_10___L4_N15. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (217.495 275.910) on ME1 for NET top/CoreClkxC_10___L4_N19. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (578.430 428.610) on ME1 for NET top/CoreClkxC_10___L4_N23. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (545.430 480.990) on ME1 for NET top/CoreClkxC_10___L4_N25. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (483.230 569.010) on ME1 for NET top/CoreClkxC_10___L4_N29. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (466.315 264.995) on ME1 for NET top/CoreClkxC_10___L4_N3. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (499.655 446.610) on ME1 for NET top/CoreClkxC_10___L4_N30. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (473.030 479.010) on ME1 for NET top/CoreClkxC_10___L4_N30. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (447.255 601.410) on ME1 for NET top/CoreClkxC_10___L4_N9. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (1511.060 1006.590) on ME1 for NET top/CoreClkxC_12___L5_N13. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (1526.055 975.810) on ME1 for NET top/CoreClkxC_12___L5_N14. The NET is considered partially routed.
#WARNING (NRDB-1005) Can not establish connection to PIN CK at (1689.545 1168.590) on ME1 for NET top/CoreClkxC_12___L5_N16. The NET is considered partially routed.
#WARNING (NRDB-1005 Repeated 20 times. Will be suppressed.) Can not establish connection to PIN CK at (1519.740 1256.610) on ME1 for NET top/CoreClkxC_12___L5_N2. The NET is considered partially routed.
#WARNING (EMS-27) Message (NRDB-1005) has exceeded the current message display limit of 20.
#To increase the message display limit, refer to the product command reference manual.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_ethz_skein/add_x_264_7_n283 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_blake/datapath_gen/DP_OP_77J1_129_7063_n807 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/FE_OCPN19407_n9487 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/FE_OCPN20785_n11870 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/FE_OCPN22450_n13656 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/FE_OCPN22670_n9749 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/FE_OCPN23287_n25589 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/dp_fx2_256_from_register_244_ are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/dp_fx2_256_rounds_after_shiftrow[297] are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/dp_fx2_256_rounds_after_subbyte[160] are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/dp_fx2_256_to_final_88_ are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/dp_fx2_256_to_reg[232] are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/n10695 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/n12088 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/n12138 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/n1216 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/n12878 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/n13081 are dangling and deleted.
#WARNING (NRDB-874) Some WIRE segments on routed NET top/i_gmu_groestl/n13394 are dangling and deleted.
#WARNING (NRDB-874 Repeated 20 times. Will be suppressed.) Some WIRE segments on routed NET top/i_gmu_groestl/n13502 are dangling and deleted.
#WARNING (EMS-27) Message (NRDB-874) has exceeded the current message display limit of 20.
#To increase the message display limit, refer to the product command reference manual.
#6954 routed nets are extracted.
# 5872 (2.07%) extracted nets are partially routed.
#273117 routed nets are imported.
#3737 routed nets are fixed|skipped|trivial (not extracted).
#Total number of nets = 283808.
#Number of eco nets is 5872
#
#Start data preparation...
#Force regenerating Ggrids.
#Auto generating G-grids with size=15 tracks, using layer ME2's pitch = 0.200.
#Using automatically generated G-grids.
#
#Data preparation is done on Fri Sep 30 15:02:16 2011
#
#Analyzing routing resource...
#Routing resource analysis is done on Fri Sep 30 15:02:23 2011
#
# Resource Analysis:
#
# Routing #Avail #Track #Total %Gcell
# Layer Direction Track Blocked Gcell Blocked
# --------------------------------------------------------------
# Metal 1 H 5808 3565 391250 74.27%
# Metal 2 V 5718 3657 391250 43.74%
# Metal 3 H 5885 3489 391250 36.36%
# Metal 4 V 5858 3516 391250 42.89%
# Metal 5 H 7164 2209 391250 22.09%
# Metal 6 V 7101 2273 391250 29.79%
# Metal 7 H 2749 1937 391250 24.29%
# Metal 8 V 239 228 391250 61.74%
# --------------------------------------------------------------
# Total 40525 36.22% 3130000 41.89%
#
# 1568 nets (0.55%) with 1 preferred extra spacing.
# 9 nets (0.00%) with 2 preferred extra spacing.
#
#
#cpu time = 00:00:08, elapsed time = 00:00:08, memory = 4511.00 (Mb)
#
#start global routing iteration 1...
#cpu time = 00:00:05, elapsed time = 00:00:02, memory = 4515.00 (Mb)
#
#start global routing iteration 2...
#cpu time = 00:00:02, elapsed time = 00:00:02, memory = 4536.00 (Mb)
#
#start global routing iteration 3...
#cpu time = 00:00:11, elapsed time = 00:00:06, memory = 4517.00 (Mb)
#
#
# Congestion Analysis: (blocked Gcells are excluded)
#
# OverCon OverCon OverCon OverCon
# #Gcell #Gcell #Gcell #Gcell %Gcell
# Layer (1-3) (4-6) (7-9) (10-13) OverCon
# --------------------------------------------------------------------------
# Metal 1 475(0.32%) 7(0.00%) 0(0.00%) 0(0.00%) (0.33%)
# Metal 2 4406(1.78%) 837(0.34%) 147(0.06%) 31(0.01%) (2.20%)
# Metal 3 2208(0.89%) 347(0.14%) 33(0.01%) 3(0.00%) (1.04%)
# Metal 4 1110(0.44%) 48(0.02%) 1(0.00%) 0(0.00%) (0.46%)
# Metal 5 64(0.02%) 0(0.00%) 0(0.00%) 0(0.00%) (0.02%)
# Metal 6 43(0.01%) 1(0.00%) 0(0.00%) 0(0.00%) (0.01%)
# Metal 7 62(0.02%) 0(0.00%) 0(0.00%) 0(0.00%) (0.02%)
# Metal 8 33(0.02%) 0(0.00%) 0(0.00%) 0(0.00%) (0.02%)
# --------------------------------------------------------------------------
# Total 8401(0.43%) 1240(0.06%) 181(0.01%) 34(0.00%) (0.51%)
#
# The worst congested Gcell overcon (routing demand over resource in number of tracks) = 13
#
#Complete Global Routing.
#Total number of nets with non-default rule or having extra spacing = 1577
#Total wire length = 16459361 um.
#Total half perimeter of net bounding box = 14228533 um.
#Total wire length on LAYER ME1 = 180644 um.
#Total wire length on LAYER ME2 = 2602175 um.
#Total wire length on LAYER ME3 = 3566815 um.
#Total wire length on LAYER ME4 = 3074232 um.
#Total wire length on LAYER ME5 = 3628014 um.
#Total wire length on LAYER ME6 = 2727176 um.
#Total wire length on LAYER ME7 = 509332 um.
#Total wire length on LAYER ME8 = 170971 um.
#Total number of vias = 2808318
#Total number of multi-cut vias = 27521 ( 1.0%)
#Total number of single cut vias = 2780797 ( 99.0%)
#Up-Via Summary (total 2808318):
# single-cut multi-cut Total
#-----------------------------------------------------------
# Metal 1 996000 (100.0%) 0 ( 0.0%) 996000
# Metal 2 1064196 (100.0%) 0 ( 0.0%) 1064196
# Metal 3 384591 (100.0%) 0 ( 0.0%) 384591
# Metal 4 201663 (100.0%) 49 ( 0.0%) 201712
# Metal 5 125464 (100.0%) 0 ( 0.0%) 125464
# Metal 6 0 ( 0.0%) 27472 (100.0%) 27472
# Metal 7 8883 (100.0%) 0 ( 0.0%) 8883
#-----------------------------------------------------------
# 2780797 ( 99.0%) 27521 ( 1.0%) 2808318
#
#Max overcon = 13 tracks.
#Total overcon = 0.51%.
#Worst layer Gcell overcon rate = 1.04%.
#Cpu time = 00:01:33
#Elapsed time = 00:01:25
#Increased memory = 134.00 (Mb)
#Total memory = 4470.00 (Mb)
#Peak memory = 4580.00 (Mb)
#Using multithreading with 8 threads.
#
#Start Detail Routing...
#start initial detail routing ...
# completing 10% with 51 violations
# elapsed time = 00:00:03, memory = 4823.00 (Mb)
# completing 20% with 107 violations
# elapsed time = 00:00:05, memory = 4846.00 (Mb)
# completing 30% with 148 violations
# elapsed time = 00:00:07, memory = 4806.00 (Mb)
# completing 40% with 200 violations
# elapsed time = 00:00:10, memory = 4858.00 (Mb)
# completing 50% with 295 violations
# elapsed time = 00:00:13, memory = 4851.00 (Mb)
# completing 60% with 379 violations
# elapsed time = 00:00:18, memory = 4866.00 (Mb)
# completing 70% with 461 violations
# elapsed time = 00:00:21, memory = 4825.00 (Mb)
# completing 80% with 514 violations
# elapsed time = 00:00:24, memory = 4807.00 (Mb)
# completing 90% with 584 violations
# elapsed time = 00:00:28, memory = 4870.00 (Mb)
# completing 100% with 723 violations
# elapsed time = 00:00:38, memory = 4680.00 (Mb)
# ECO: 0.0% of the total area was rechecked for DRC, and 4.3% required routing.
# number of violations = 723
#2.3% of the total area is being checked for drcs
#2.3% of the total area was checked
# number of violations = 1422
#cpu time = 00:03:30, elapsed time = 00:00:51, memory = 4630.00 (Mb)
#start 1st optimization iteration ...
# number of violations = 109
#cpu time = 00:00:47, elapsed time = 00:00:13, memory = 4624.00 (Mb)
#start 2nd optimization iteration ...
# number of violations = 5
#cpu time = 00:00:03, elapsed time = 00:00:01, memory = 4624.00 (Mb)
#start 3rd optimization iteration ...
# number of violations = 0
#cpu time = 00:00:01, elapsed time = 00:00:00, memory = 4624.00 (Mb)
#Complete Detail Routing.
#Total number of nets with non-default rule or having extra spacing = 1577
#Total wire length = 16459162 um.
#Total half perimeter of net bounding box = 14228533 um.
#Total wire length on LAYER ME1 = 180695 um.
#Total wire length on LAYER ME2 = 2600263 um.
#Total wire length on LAYER ME3 = 3565178 um.
#Total wire length on LAYER ME4 = 3076045 um.
#Total wire length on LAYER ME5 = 3629223 um.
#Total wire length on LAYER ME6 = 2727445 um.
#Total wire length on LAYER ME7 = 509317 um.
#Total wire length on LAYER ME8 = 170996 um.
#Total number of vias = 2811695
#Total number of multi-cut vias = 27512 ( 1.0%)
#Total number of single cut vias = 2784183 ( 99.0%)
#Up-Via Summary (total 2811695):
# single-cut multi-cut Total
#-----------------------------------------------------------
# Metal 1 996900 (100.0%) 0 ( 0.0%) 996900
# Metal 2 1064954 (100.0%) 0 ( 0.0%) 1064954
# Metal 3 385764 (100.0%) 0 ( 0.0%) 385764
# Metal 4 202112 (100.0%) 49 ( 0.0%) 202161
# Metal 5 125569 (100.0%) 0 ( 0.0%) 125569
# Metal 6 0 ( 0.0%) 27463 (100.0%) 27463
# Metal 7 8884 (100.0%) 0 ( 0.0%) 8884
#-----------------------------------------------------------
# 2784183 ( 99.0%) 27512 ( 1.0%) 2811695
#
#Total number of DRC violations = 0
#Total number of violations on LAYER ME1 = 0
#Total number of violations on LAYER ME2 = 0
#Total number of violations on LAYER ME3 = 0
#Total number of violations on LAYER ME4 = 0
#Total number of violations on LAYER ME5 = 0
#Total number of violations on LAYER ME6 = 0
#Total number of violations on LAYER ME7 = 0
#Total number of violations on LAYER ME8 = 0
#
#start routing for process antenna violation fix ...
#cpu time = 00:00:11, elapsed time = 00:00:12, memory = 4596.00 (Mb)
#
#Total number of nets with non-default rule or having extra spacing = 1577
#Total wire length = 16459162 um.
#Total half perimeter of net bounding box = 14228533 um.
#Total wire length on LAYER ME1 = 180695 um.
#Total wire length on LAYER ME2 = 2600263 um.
#Total wire length on LAYER ME3 = 3565178 um.
#Total wire length on LAYER ME4 = 3076045 um.
#Total wire length on LAYER ME5 = 3629223 um.
#Total wire length on LAYER ME6 = 2727445 um.
#Total wire length on LAYER ME7 = 509317 um.
#Total wire length on LAYER ME8 = 170996 um.
#Total number of vias = 2811695
#Total number of multi-cut vias = 27512 ( 1.0%)
#Total number of single cut vias = 2784183 ( 99.0%)
#Up-Via Summary (total 2811695):
# single-cut multi-cut Total
#-----------------------------------------------------------
# Metal 1 996900 (100.0%) 0 ( 0.0%) 996900
# Metal 2 1064954 (100.0%) 0 ( 0.0%) 1064954
# Metal 3 385764 (100.0%) 0 ( 0.0%) 385764
# Metal 4 202112 (100.0%) 49 ( 0.0%) 202161
# Metal 5 125569 (100.0%) 0 ( 0.0%) 125569
# Metal 6 0 ( 0.0%) 27463 (100.0%) 27463
# Metal 7 8884 (100.0%) 0 ( 0.0%) 8884
#-----------------------------------------------------------
# 2784183 ( 99.0%) 27512 ( 1.0%) 2811695
#
#Total number of DRC violations = 0
#Total number of net violated process antenna rule = 0
#Total number of violations on LAYER ME1 = 0
#Total number of violations on LAYER ME2 = 0
#Total number of violations on LAYER ME3 = 0
#Total number of violations on LAYER ME4 = 0
#Total number of violations on LAYER ME5 = 0
#Total number of violations on LAYER ME6 = 0
#Total number of violations on LAYER ME7 = 0
#Total number of violations on LAYER ME8 = 0
#
#detailRoute Statistics:
#Cpu time = 00:04:50
#Elapsed time = 00:01:37
#Increased memory = 120.00 (Mb)
#Total memory = 4590.00 (Mb)
#Peak memory = 4943.00 (Mb)
#Updating routing design signature
#Created 3310 library cell signatures
#Created 283808 NETS and 0 SPECIALNETS signatures
#Created 310894 instance signatures
#
#globalDetailRoute statistics:
#Cpu time = 00:07:01
#Elapsed time = 00:03:38
#Increased memory = -470.00 (Mb)
#Total memory = 3765.00 (Mb)
#Peak memory = 4943.00 (Mb)
#Number of warnings = 84
#Total number of warnings = 84
#Number of fails = 0
#Total number of fails = 0
#Complete globalDetailRoute on Fri Sep 30 15:04:20 2011
#
**optDesign ... cpu = 1:09:50, real = 1:06:30, mem = 3765.6M **
-routeWithEco false # bool, default=false, user setting
-routeSelectedNetOnly false # bool, default=false
-routeWithTimingDriven true # bool, default=false, user setting
-routeWithSiDriven false # bool, default=false, user setting
-drouteStartIteration 0 # int, default=0, user setting
Extraction called for design 'shabziger_chip' of instances=310893 and nets=283808 using extraction engine 'postRoute' at effort level 'low' .
Detail RC Extraction called for design shabziger_chip.
RC Extraction called in multi-corner(2) mode.
Process corner(s) are loaded.
Corner: rc_worst
Corner: rc_best
extractDetailRC Option : -outfile ../tmp/shabziger_chip_HQpeam_28299.rcdb.d -maxResLength 200 -extended
RC Mode: Detail [Extended CapTable, RC Table Resistances]
RC Corner Indexes 0 1
Capacitance Scaling Factor : 1.00000 1.00000
Coupling Cap. Scaling Factor : 1.00000 1.00000
Resistance Scaling Factor : 1.00000 1.00000
Clock Cap. Scaling Factor : 1.00000 1.00000
Clock Res. Scaling Factor : 1.00000 1.00000
Shrink Factor : 1.00000
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Checking LVS Completed (CPU Time= 0:00:01.2 MEM= 3764.2M)
Creating parasitic data file '../tmp/shabziger_chip_HQpeam_28299.rcdb.d/header.da' in memory efficient access mode for storing RC.
Extracted 10.0001% (CPU Time= 0:00:07.5 MEM= 4024.3M)
Extracted 20.0001% (CPU Time= 0:00:14.6 MEM= 4024.3M)
Extracted 30.0001% (CPU Time= 0:00:18.5 MEM= 4024.3M)
Extracted 40.0001% (CPU Time= 0:00:25.4 MEM= 4024.3M)
Extracted 50.0001% (CPU Time= 0:00:33.0 MEM= 4050.4M)
Extracted 60.0001% (CPU Time= 0:00:37.9 MEM= 4055.4M)
Extracted 70% (CPU Time= 0:00:46.6 MEM= 4056.4M)
Extracted 80% (CPU Time= 0:00:54.8 MEM= 4056.4M)
Extracted 90% (CPU Time= 0:01:00 MEM= 4056.4M)
Extracted 100% (CPU Time= 0:01:12 MEM= 4056.4M)
Nr. Extracted Resistors : 5602734
Nr. Extracted Ground Cap. : 5881637
Nr. Extracted Coupling Cap. : 0
Opening parasitic data file '../tmp/shabziger_chip_HQpeam_28299.rcdb.d/header.da' for reading.
Detail RC Extraction DONE (CPU Time: 0:01:15 Real Time: 0:01:18 MEM: 3763.562M)
Using new Cte TW Api base...#################################################################################
# Design Stage: PostRoute
# Design Mode: 65nm
# Analysis Mode: MMMC non-OCV
# Extraction Mode: detail/spef
# Delay Calculation Options: engine=signalStorm signOff=true SIAware=false(opt)
# Switching Delay Calculation Engine to signalStorm
#################################################################################
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:01.3, MEM = 3798.3M, InitMEM = 3798.3M)
Start delay calculation using Signal Storm (mem=3798.285M)...
delayCal using detail RC...
Opening parasitic data file '../tmp/shabziger_chip_HQpeam_28299.rcdb.d/header.da' for reading.
RC Database In Completed (CPU Time= 0:00:01.5 MEM= 3888.7M)
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Delay calculation completed. (cpu=0:00:49.7 real=0:00:50.0 mem=4352.875M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 4352.9M, InitMEM = 4352.9M)
Start delay calculation using Signal Storm (mem=4352.875M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:25.2 real=0:00:25.0 mem=4352.875M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 4352.9M, InitMEM = 4352.9M)
Start delay calculation using Signal Storm (mem=4352.875M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:25.0 real=0:00:25.0 mem=4352.875M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.8, MEM = 4352.9M, InitMEM = 4352.9M)
Start delay calculation using Signal Storm (mem=4352.875M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:25.6 real=0:00:26.0 mem=4352.875M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.8, MEM = 4352.9M, InitMEM = 4352.9M)
Start delay calculation using Signal Storm (mem=4352.875M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:25.6 real=0:00:26.0 mem=4352.875M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 4352.9M, InitMEM = 4352.9M)
Start delay calculation using Signal Storm (mem=4352.875M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:25.1 real=0:00:25.0 mem=4352.875M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 4352.9M, InitMEM = 4352.9M)
Start delay calculation using Signal Storm (mem=4352.875M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:26.0 real=0:00:26.0 mem=4352.875M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 4352.9M, InitMEM = 4352.9M)
Start delay calculation using Signal Storm (mem=4352.875M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:25.9 real=0:00:26.0 mem=4352.875M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.8, MEM = 4352.9M, InitMEM = 4352.9M)
Start delay calculation using Signal Storm (mem=4352.875M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:27.9 real=0:00:28.0 mem=4352.875M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 4352.9M, InitMEM = 4352.9M)
Start delay calculation using Signal Storm (mem=4352.875M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:26.8 real=0:00:26.0 mem=4352.875M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 4352.9M, InitMEM = 4352.9M)
Start delay calculation using Signal Storm (mem=4352.875M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:27.7 real=0:00:28.0 mem=4352.875M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 4352.9M, InitMEM = 4352.9M)
Start delay calculation using Signal Storm (mem=4352.875M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:26.8 real=0:00:27.0 mem=4352.875M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.8, MEM = 4352.9M, InitMEM = 4352.9M)
Start delay calculation using Signal Storm (mem=4352.875M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:28.8 real=0:00:29.0 mem=4354.883M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 4354.9M, InitMEM = 4354.9M)
Start delay calculation using Signal Storm (mem=4354.883M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:27.2 real=0:00:27.0 mem=4354.883M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.8, MEM = 4354.9M, InitMEM = 4354.9M)
Start delay calculation using Signal Storm (mem=4354.883M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:27.2 real=0:00:27.0 mem=4354.883M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 4354.9M, InitMEM = 4354.9M)
Start delay calculation using Signal Storm (mem=4354.883M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:27.0 real=0:00:27.0 mem=4354.883M 0)
Calculate delays in Single mode...
Topological Sorting (CPU = 0:00:00.9, MEM = 4354.9M, InitMEM = 4354.9M)
Start delay calculation using Signal Storm (mem=4354.883M)...
delayCal using detail RC...
Delay calculation completed. (cpu=0:00:36.3 real=0:00:36.0 mem=4354.883M 0)
*** CDM Built up (cpu=0:09:04 real=0:09:04 mem= 4354.9M) ***
*** Timing NOT met, worst failing slack is -0.078
*** Check timing (0:10:11)
Clearing footprints for all libraries
Loading footprints for all corners
***** CTE Mode is Operational *****
Info: 40 top-level, potential tri-state nets excluded from IPO operation.
Info: 40 io nets excluded
Info: 567 clock nets excluded from IPO operation.
*** Starting new resizing ***
density before resizing = 60.420%
start postIPO sizing
264 instances have been resized
*summary: 264 instances changed cell type
density after resizing = 60.420%
*** Finish new resizing (cpu=0:01:07 mem=4717.4M) ***
*** Starting resizing for timing improvement ***
507 instances have been resized
density change = 0.000%
*summary: 507 instances changed cell type
*** Finish resizing for timing improvement (cpu=0:00:55.0 mem=4721.7M) ***
*** Starting sequential cell resizing ***
density before resizing = 60.420%
*summary: 263 instances changed cell type
density after resizing = 60.420%
*** Finish sequential cell resizing (cpu=0:00:40.2 mem=4725.7M) ***
Instances Resized for DRV : 0
Instances Resized for Timing: 1034
Total Instances Resized : 1034
Current TNS: -51.212 Prev TNS: -51.163
Current WNS: -0.078 Prev WNS: -0.078
Restoring original footprint information
Clearing footprints for all libraries
Loading footprints for all corners
Latch borrow mode reset to max_borrow
Reported timing to dir timingReports_final
**optDesign ... cpu = 1:25:25, real = 1:22:08, mem = 4066.9M **
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
optDesign Final Summary
------------------------------------------------------------
+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| -0.078 | -0.078 | 0.500 | 0.322 | 18.541 | 15.615 |
| TNS (ns):| -51.176 | -51.176 | 0.000 | 0.000 | 0.000 | 0.000 |
| Violating Paths:| 1571 | 1571 | 0 | 0 | 0 | 0 |
| All Paths:| 85005 | 46605 | 63302 | 19 | 2 | 15 |
+--------------------+---------+---------+---------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 0 (0) | 0.000 | 0 (0) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 60.420%
------------------------------------------------------------
**optDesign ... cpu = 1:36:09, real = 1:31:51, mem = 4376.1M **
**INFO : removing temp dont-use cells (LVT only flow version : 4)
Deleting the dont_use list
*** Finished optDesign ***
Opening parasitic data file '../tmp/shabziger_chip_HQpeam_28299.rcdb.d/header.da' for reading.
Closing parasitic data file '../tmp/shabziger_chip_HQpeam_28299.rcdb.d'. 9114841 times net's RC data read were performed.
RC Database In Completed (CPU Time= 0:00:01.3 MEM= 4208.4M)
timeDesign -expandedViews -reportOnly -outDir timingReports_final -prefix shabziger.postrouteopt3.expV
Found active setup analysis view dummy_slow_view
Found active setup analysis view ethz_blake_slow_view
Found active setup analysis view ethz_groestl_slow_view
Found active setup analysis view ethz_jh_slow_view
Found active setup analysis view ethz_keccak_slow_view
Found active setup analysis view ethz_sha2_slow_view
Found active setup analysis view ethz_skein_slow_view
Found active setup analysis view gmu_blake_slow_view
Found active setup analysis view gmu_groestl_slow_view
Found active setup analysis view gmu_jh_slow_view
Found active setup analysis view gmu_keccak_slow_view
Found active setup analysis view gmu_sha2_slow_view
Found active setup analysis view gmu_skein_slow_view
Found active setup analysis view ram1_slow_view
Found active setup analysis view ram2_slow_view
Found active setup analysis view ram3_slow_view
Found active setup analysis view test_slow_view
Found active hold analysis view hold_fast_view
------------------------------------------------------------
timeDesign Summary
------------------------------------------------------------
+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| -0.078 | -0.078 | 0.500 | 0.322 | 18.541 | 15.615 |
| TNS (ns):| -51.176 | -51.176 | 0.000 | 0.000 | 0.000 | 0.000 |
| Violating Paths:| 1571 | 1571 | 0 | 0 | 0 | 0 |
| All Paths:| 85005 | 46605 | 63302 | 19 | 2 | 15 |
+--------------------+---------+---------+---------+---------+---------+---------+
|dummy_slow_view | 7.871 | 7.871 | 9.007 | 8.722 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5131 | 2517 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_blake_slow_view| 0.035 | 0.035 | 3.896 | 3.722 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 8290 | 4385 | 3887 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_groestl_slow_view
| | -0.061 | -0.061 | 2.607 | 2.322 | N/A | N/A |
| | -1.603 | -1.603 | 0.000 | 0.000 | N/A | N/A |
| | 72 | 72 | 0 | 0 | N/A | N/A |
| | 8236 | 4070 | 4148 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_jh_slow_view | -0.025 | -0.025 | 2.007 | 1.722 | N/A | N/A |
| | -0.028 | -0.028 | 0.000 | 0.000 | N/A | N/A |
| | 2 | 2 | 0 | 0 | N/A | N/A |
| | 8801 | 4640 | 4143 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_keccak_slow_view
| | -0.060 | -0.060 | 0.726 | 0.722 | N/A | N/A |
| | -0.980 | -0.980 | 0.000 | 0.000 | N/A | N/A |
| | 58 | 58 | 0 | 0 | N/A | N/A |
| | 8346 | 4125 | 4203 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_sha2_slow_view | 0.105 | 0.105 | 2.497 | 2.222 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 7204 | 3554 | 3632 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ethz_skein_slow_view| -0.062 | -0.062 | 1.597 | 1.522 | N/A | N/A |
| | -2.052 | -2.052 | 0.000 | 0.000 | N/A | N/A |
| | 76 | 76 | 0 | 0 | N/A | N/A |
| | 9002 | 4517 | 4467 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_blake_slow_view | -0.062 | -0.062 | 2.907 | 2.622 | N/A | N/A |
| | -3.413 | -3.413 | 0.000 | 0.000 | N/A | N/A |
| | 98 | 98 | 0 | 0 | N/A | N/A |
| | 9724 | 5498 | 4208 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_groestl_slow_view
| | -0.078 | -0.078 | 1.041 | 0.822 | N/A | N/A |
| | -33.348 | -33.348 | 0.000 | 0.000 | N/A | N/A |
| | 822 | 822 | 0 | 0 | N/A | N/A |
| | 9252 | 5088 | 4146 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_jh_slow_view | -0.059 | -0.059 | 0.607 | 0.322 | N/A | N/A |
| | -1.760 | -1.760 | 0.000 | 0.000 | N/A | N/A |
| | 103 | 103 | 0 | 0 | N/A | N/A |
| | 10269 | 5853 | 4398 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_keccak_slow_view| -0.069 | -0.069 | 0.607 | 0.322 | N/A | N/A |
| | -6.466 | -6.466 | 0.000 | 0.000 | N/A | N/A |
| | 294 | 294 | 0 | 0 | N/A | N/A |
| | 9926 | 5702 | 4206 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_sha2_slow_view | -0.060 | -0.060 | 0.500 | 0.522 | N/A | N/A |
| | -0.366 | -0.366 | 0.000 | 0.000 | N/A | N/A |
| | 18 | 18 | 0 | 0 | N/A | N/A |
| | 7986 | 4238 | 3730 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|gmu_skein_slow_view | -0.060 | -0.060 | 2.614 | 4.222 | N/A | N/A |
| | -1.246 | -1.246 | 0.000 | 0.000 | N/A | N/A |
| | 39 | 39 | 0 | 0 | N/A | N/A |
| | 10156 | 5551 | 4587 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ram1_slow_view | 5.156 | 5.156 | 9.007 | 8.722 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5237 | 2623 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ram2_slow_view | 4.909 | 4.909 | 9.007 | 8.722 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5237 | 2623 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|ram3_slow_view | 3.366 | 3.366 | 9.007 | 8.722 | N/A | N/A |
| | 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| | 0 | 0 | 0 | 0 | N/A | N/A |
| | 5240 | 2626 | 2596 | 19 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
|test_slow_view | 13.339 | 13.339 | 13.778 | 18.521 | 18.541 | 15.615 |
| | 0.000 | 0.000 | 0.000 | 0.000 | 0.000 | 0.000 |
| | 0 | 0 | 0 | 0 | 0 | 0 |
| | 85005 | 46605 | 63302 | 19 | 2 | 15 |
+--------------------+---------+---------+---------+---------+---------+---------+
+----------------+-------------------------------+------------------+
| | Real | Total |
| DRVs +------------------+------------+------------------|
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap | 0 (0) | 0.000 | 0 (0) |
| max_tran | 0 (0) | 0.000 | 0 (0) |
| max_fanout | 0 (0) | 0 | 0 (0) |
+----------------+------------------+------------+------------------+
Density: 60.420%
------------------------------------------------------------
Reported timing to dir timingReports_final
Total CPU time: 197.34 sec
Total Real time: 139.0 sec
Total Memory Usage: 4208.433594 Mbytes
saveDesign save/chip_shabziger_final3.enc
Redoing specifyClockTree ...
Checking spec file integrity...
**WARN: (ENCSYT-3036): Design directory save/chip_shabziger_final3.enc.dat exists, rename it to save/chip_shabziger_final3.enc.dat.tmp.
If saveDesign succeeds, it will be deleted.
Writing Netlist "save/chip_shabziger_final3.enc.dat/shabziger_chip.v.gz" ...
Saving clock tree spec file 'save/chip_shabziger_final3.enc.dat/shabziger_chip.ctstch' ...
Saving configuration ...
Saving preference file save/chip_shabziger_final3.enc.dat/enc.pref.tcl ...
Saving floorplan ...
Saving Drc markers ...
... No Drc file written since there is no markers found.
Saving placement ...
*** Completed savePlace (cpu=0:00:00.4 real=0:00:01.0 mem=4170.2M) ***
Saving route ...
*** Completed saveRoute (cpu=0:00:04.4 real=0:00:11.0 mem=4170.2M) ***
Writing DEF file 'save/chip_shabziger_final3.enc.dat/shabziger_chip.def.gz', current time is Fri Sep 30 15:32:25 2011 ...
unitPerMicron=1000, dbgMicronPerDBU=0.001000, unitPerDBU=1.000000
DEF file 'save/chip_shabziger_final3.enc.dat/shabziger_chip.def.gz' is written, current time is Fri Sep 30 15:32:26 2011 ...
*** Completed saveYieldMap (cpu=: 0:00:00.0 real=0:00:00.0 mem=: 0.000M) ***
addFiller -cell {FILEP64W FILEP32W FILEP16W FILEP8W FILE6W FILE4W FILE3W FIL2W FILEP64S FILEP32S FILEP16S FILEP8S FILE6S FILE4S FILE3S FIL2S FILEP64R FILEP32R FILEP16R FILEP8R FILE6R FILE4R FILE3R FIL2R} -prefix fillcore
*INFO: Adding fillers to top-module.
*INFO: Added 1165 filler insts (cell FILEP64W / prefix fillcore).
*INFO: Added 5013 filler insts (cell FILEP64S / prefix fillcore).
*INFO: Added 245 filler insts (cell FILEP64R / prefix fillcore).
*INFO: Added 5394 filler insts (cell FILEP32W / prefix fillcore).
*INFO: Added 2333 filler insts (cell FILEP32S / prefix fillcore).
*INFO: Added 581 filler insts (cell FILEP32R / prefix fillcore).
*INFO: Added 18222 filler insts (cell FILEP16W / prefix fillcore).
*INFO: Added 6272 filler insts (cell FILEP16S / prefix fillcore).
*INFO: Added 1877 filler insts (cell FILEP16R / prefix fillcore).
*INFO: Added 36776 filler insts (cell FILEP8W / prefix fillcore).
*INFO: Added 8890 filler insts (cell FILEP8S / prefix fillcore).
*INFO: Added 3954 filler insts (cell FILEP8R / prefix fillcore).
*INFO: Added 22719 filler insts (cell FILE6W / prefix fillcore).
*INFO: Added 4558 filler insts (cell FILE6S / prefix fillcore).
*INFO: Added 2313 filler insts (cell FILE6R / prefix fillcore).
*INFO: Added 31391 filler insts (cell FILE4W / prefix fillcore).
*INFO: Added 5930 filler insts (cell FILE4S / prefix fillcore).
*INFO: Added 3228 filler insts (cell FILE4R / prefix fillcore).
*INFO: Added 22420 filler insts (cell FILE3W / prefix fillcore).
*INFO: Added 5729 filler insts (cell FILE3S / prefix fillcore).
*INFO: Added 2289 filler insts (cell FILE3R / prefix fillcore).
*INFO: Added 29441 filler insts (cell FIL2W / prefix fillcore).
*INFO: Added 4150 filler insts (cell FIL2S / prefix fillcore).
*INFO: Added 3010 filler insts (cell FIL2R / prefix fillcore).
*INFO: Total 227900 filler insts added - prefix fillcore (CPU: 0:00:04.3).
For 227900 new insts, *** Applied 4 GNC rules (cpu = 0:00:00.1)
*INFO: Checking for DRC violations on added fillers.
*INFO: Iteration 0-#1, Found 436255 DRC violations (real: 0:00:39.0).
For 181904 new insts, *** Applied 4 GNC rules (cpu = 0:00:00.1)
*INFO: Iteration 0-#2, Found 289946 DRC violations (real: 0:00:36.0).
For 102121 new insts, *** Applied 4 GNC rules (cpu = 0:00:00.1)
*INFO: Iteration 0-#3, Found 183707 DRC violations (real: 0:00:35.0).
For 58466 new insts, *** Applied 4 GNC rules (cpu = 0:00:00.0)
*INFO: Iteration 0-#4, Found 93468 DRC violations (real: 0:00:34.0).
For 28338 new insts, *** Applied 4 GNC rules (cpu = 0:00:00.0)
*INFO: Iteration 0-#5, Found 38873 DRC violations (real: 0:00:33.0).
For 9039 new insts, *** Applied 4 GNC rules (cpu = 0:00:00.0)
*INFO: Iteration 0-#6, Found 9396 DRC violations (real: 0:00:31.0).
For 1734 new insts, *** Applied 4 GNC rules (cpu = 0:00:00.0)
*INFO: Iteration 0-#7, Found 477 DRC violations (real: 0:00:31.0).
For 356 new insts, *** Applied 4 GNC rules (cpu = 0:00:00.0)
*INFO: Iteration 0-#8, Found 0 DRC violation (real: 0:00:30.0).
*INFO: Adding fillers to top-module.
*INFO: Added 151391 filler insts (cell FIL2R / prefix fillcore).
For 151391 new insts, *** Applied 4 GNC rules (cpu = 0:00:00.1)
*INFO: End DRC Checks. (real: 0:05:14 ).
*INFO: Replaced 290800 fillers which had DRC vio's, with 381958 new fillers.
addFiller -cell {FIL1W FIL1R FIL1S} -prefix fillcore
*INFO: Adding fillers to top-module.
*INFO: Added 62947 filler insts (cell FIL1W / prefix fillcore).
*INFO: Added 7466 filler insts (cell FIL1S / prefix fillcore).
*INFO: Added 25852 filler insts (cell FIL1R / prefix fillcore).
*INFO: Total 96265 filler insts added - prefix fillcore (CPU: 0:00:04.1).
For 96265 new insts, *** Applied 4 GNC rules (cpu = 0:00:00.0)
*INFO: Checking for DRC violations on added fillers.
*INFO: Iteration 0-#1, Found 0 DRC violation (real: 0:00:34.0).
*INFO: Adding fillers to top-module.
*INFO: Added 0 filler inst of any cell-type.
For 0 new insts, *** Applied 0 GNC rules.
*INFO: End DRC Checks. (real: 0:00:34.0 ).
setExtractRCMode -engine detail -coupled false -reduce 0.0
**WARN: (ENCEXT-1082): Option '-engine detail' is obsolete. Use '-engine postRoute [-effortLevel low]' to set extraction engine, which is based on recommended convention '-engine postRoute [-effortLevel ]'. The obsolete option still works in this release, but to avoid this warning and to ensure compatibility with future releases, update your script and configuration file to use recommended convention.
**WARN: (ENCEXT-1090): Option '-effortLevel low' specified in past directly by user or in-directly through 'timeDesign -signoff' or similar command. And option '-engine detail' specified now. User is recommended to use either '-engine postRoute [-effortLevel ]' or '-engine default|detail|cce|signoff' because '-engine default|detail|cce|signoff' has implicit meaning for '-effortLevel'. In this case, most recent engine option specified '-engine detail' will be honored by the tool and '-effortLevel' ignored.
**WARN: (ENCEXT-3493): Extraction mode changed by calling extraction setup command 'setExtractRCMode'. Therefore, parasitic data in the tool generated as per previous mode is deleted. Call of extractRC/spefIn will generate/bring parasitic data in the tool as per current mode.
extractRC
Extraction called for design 'shabziger_chip' of instances=877607 and nets=283808 using extraction engine 'postRoute' at effort level 'low' .
Detail RC Extraction called for design shabziger_chip.
RC Extraction called in multi-corner(2) mode.
Process corner(s) are loaded.
Corner: rc_worst
Corner: rc_best
extractDetailRC Option : -outfile ../tmp/shabziger_chip_HQpeam_28299.rcdb.d -maxResLength 200 -extended
RC Mode: Detail [Extended CapTable, RC Table Resistances]
RC Corner Indexes 0 1
Capacitance Scaling Factor : 1.00000 1.00000
Coupling Cap. Scaling Factor : 1.00000 1.00000
Resistance Scaling Factor : 1.00000 1.00000
Clock Cap. Scaling Factor : 1.00000 1.00000
Clock Res. Scaling Factor : 1.00000 1.00000
Shrink Factor : 1.00000
Initializing multi-corner capacitance tables ...
Initializing multi-corner resistance tables ...
Checking LVS Completed (CPU Time= 0:00:01.2 MEM= 4313.1M)
Closing parasitic data file '../tmp/shabziger_chip_HQpeam_28299.rcdb.d'. 100593 times net's RC data read were performed.
Creating parasitic data file '../tmp/shabziger_chip_HQpeam_28299.rcdb.d/header.da' in memory efficient access mode for storing RC.
Extracted 10.0001% (CPU Time= 0:00:07.8 MEM= 4546.9M)
Extracted 20.0001% (CPU Time= 0:00:14.8 MEM= 4550.9M)
Extracted 30.0001% (CPU Time= 0:00:18.8 MEM= 4574.0M)
Extracted 40.0001% (CPU Time= 0:00:25.3 MEM= 4576.0M)
Extracted 50.0001% (CPU Time= 0:00:33.0 MEM= 4608.1M)
Extracted 60.0001% (CPU Time= 0:00:37.9 MEM= 4613.1M)
Extracted 70% (CPU Time= 0:00:46.5 MEM= 4613.1M)
Extracted 80% (CPU Time= 0:00:54.6 MEM= 4613.1M)
Extracted 90% (CPU Time= 0:00:59.8 MEM= 4613.1M)
Extracted 100% (CPU Time= 0:01:12 MEM= 4613.1M)
Nr. Extracted Resistors : 5602734
Nr. Extracted Ground Cap. : 5881637
Nr. Extracted Coupling Cap. : 0
Opening parasitic data file '../tmp/shabziger_chip_HQpeam_28299.rcdb.d/header.da' for reading.
Detail RC Extraction DONE (CPU Time: 0:01:15 Real Time: 0:01:17 MEM: 4293.160M)
saveNetlist out/shabziger.v -excludeLeafCell -includePhysicalInst
Writing Netlist "out/shabziger.v" ...
Warning (Quiet mode): There are 200 pg terms not connected to global special net.
**WARN: (ENCVL-505): PG terms are not connected to global pg nets.
**WARN: (ENCVL-516): No Power/Ground connections in top module (shabziger_chip).
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_49 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_48 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_47 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_46 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_45 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_44 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_43 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_42 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_41 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_40 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_39 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_38 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_37 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_36 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_35 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_34 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_33 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_32 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_31 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_30 is not connected to a global P/G net.
**WARN: (EMS-62): Message has exceeded the default message display limit of 20.
To avoid this warning, increase the display limit per unique message
by using the set_message_limit command.
The message limit can be removed by using the unset_message_limit command.
Note that setting a very large number using the set_message_limit command
or removing the message limit using the unset_message_limit command can
significantly increase the log file size.
To suppress a message, use suppress_message command.
Pwr name (VDD).
Pwr name (VDDIO).
Gnd name (VSS).
Gnd name (VSSIO).
2 Pwr names and 2 Gnd names.
saveNetlist out/shabziger_lvs.v -excludeLeafCell -includePhysicalInst -phys
Writing Netlist "out/shabziger_lvs.v" ...
Warning (Quiet mode): There are 200 pg terms not connected to global special net.
**WARN: (ENCVL-505): PG terms are not connected to global pg nets.
**WARN: (ENCVL-516): No Power/Ground connections in top module (shabziger_chip).
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_49 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_48 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_47 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_46 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_45 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_44 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_43 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_42 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_41 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_40 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_39 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_38 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_37 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_36 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_35 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_34 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_33 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_32 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_31 is not connected to a global P/G net.
**WARN: (ENCVL-520): P/G pin VSSIO of instance fillperi_N_30 is not connected to a global P/G net.
Pwr name (VDD).
Pwr name (VDDIO).
Gnd name (VSS).
Gnd name (VSSIO).
2 Pwr names and 2 Gnd names.
Creating all pg connections for top cell (shabziger_chip).
setStreamOutMode -SEvianames ON -specifyViaName %t_VIA
streamOut out/shabziger.gds.gz -mapFile tech/streamOut_noObs.map -outputMacros -merge { /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbr/a02/gds/uk65lscllmvbbr.gds /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbl/a02/gds/uk65lscllmvbbl.gds /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbh/a02/gds/uk65lscllmvbbh.gds /usr/pack/umc-65-kgf/umc/ll/u065gioll25mvir/a03/gds/u065gioll25mvir_8m1t0f1u.gds /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_16384X32X1CM16.gds /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_2048X32X1CM4.gds /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SYKA65_2048X32X1CM8.gds }
Finding the highest version number among the merge files
Merge file: /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbr/a02/gds/uk65lscllmvbbr.gds has version number: 5
Merge file: /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbl/a02/gds/uk65lscllmvbbl.gds has version number: 5
Merge file: /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbh/a02/gds/uk65lscllmvbbh.gds has version number: 5
Merge file: /usr/pack/umc-65-kgf/umc/ll/u065gioll25mvir/a03/gds/u065gioll25mvir_8m1t0f1u.gds has version number: 5
Merge file: /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_16384X32X1CM16.gds has version number: 5
Merge file: /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_2048X32X1CM4.gds has version number: 5
Merge file: /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SYKA65_2048X32X1CM8.gds has version number: 5
Parse map file...
Writing GDSII file ...
****** db unit per micron = 1000 ******
****** output gds2 file unit per micron = 1000 ******
****** unit scaling factor = 1 ******
Output for instance
Output for bump
Output for physical terminals
Output for logical terminals
Output for regular nets
Output for special nets and metal fills
Output for via structure generation
Statistics for GDS generated (version 5)
----------------------------------------
Stream Out Layer Mapping Information:
GDS Layer Number GDS Layer Name
----------------------------------------
121 COMP
46 ME1
47 VI1
48 ME2
49 VI2
50 ME3
51 VI3
52 ME4
53 VI4
54 ME5
55 VI5
56 ME6
57 VI6
58 ME7
59 VI7
60 ME8
101 ME1
102 ME2
103 ME3
104 ME4
105 ME5
106 ME6
107 ME7
108 ME8
Stream Out Information Processed for GDS version 5:
Units: 1000 DBU
Object Count
----------------------------------------
Instances 877607
Ports/Pins 0
Nets 2766921
metal layer ME1 167159
metal layer ME2 1101224
metal layer ME3 834033
metal layer ME4 309293
metal layer ME5 205350
metal layer ME6 102840
metal layer ME7 42236
metal layer ME8 4786
Via Instances 2811695
Special Nets 4751
metal layer ME1 4146
metal layer ME2 68
metal layer ME3 57
metal layer ME4 24
metal layer ME5 24
metal layer ME6 24
metal layer ME7 319
metal layer ME8 89
Via Instances 189513
Metal Fills 0
Via Instances 0
Metal FillOPCs 0
Via Instances 0
Text 42
metal layer ME1 2
metal layer ME4 40
Blockages 0
Custom Text 0
Custom Box 0
Merging with GDS libraries
Scanning GDS file /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbr/a02/gds/uk65lscllmvbbr.gds to register cell name ......
Scanning GDS file /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbl/a02/gds/uk65lscllmvbbl.gds to register cell name ......
Scanning GDS file /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbh/a02/gds/uk65lscllmvbbh.gds to register cell name ......
Scanning GDS file /usr/pack/umc-65-kgf/umc/ll/u065gioll25mvir/a03/gds/u065gioll25mvir_8m1t0f1u.gds to register cell name ......
Scanning GDS file /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_16384X32X1CM16.gds to register cell name ......
Scanning GDS file /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_2048X32X1CM4.gds to register cell name ......
Scanning GDS file /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SYKA65_2048X32X1CM8.gds to register cell name ......
Merging GDS file /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbr/a02/gds/uk65lscllmvbbr.gds ......
****** Merge file: /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbr/a02/gds/uk65lscllmvbbr.gds has version number: 5.
****** Merge file: /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbr/a02/gds/uk65lscllmvbbr.gds has units: 1000 per micron.
****** unit scaling factor = 1 ******
Merging GDS file /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbl/a02/gds/uk65lscllmvbbl.gds ......
****** Merge file: /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbl/a02/gds/uk65lscllmvbbl.gds has version number: 5.
****** Merge file: /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbl/a02/gds/uk65lscllmvbbl.gds has units: 1000 per micron.
****** unit scaling factor = 1 ******
Merging GDS file /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbh/a02/gds/uk65lscllmvbbh.gds ......
****** Merge file: /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbh/a02/gds/uk65lscllmvbbh.gds has version number: 5.
****** Merge file: /usr/pack/umc-65-kgf/umc/ll/uk65lscllmvbbh/a02/gds/uk65lscllmvbbh.gds has units: 1000 per micron.
****** unit scaling factor = 1 ******
Merging GDS file /usr/pack/umc-65-kgf/umc/ll/u065gioll25mvir/a03/gds/u065gioll25mvir_8m1t0f1u.gds ......
****** Merge file: /usr/pack/umc-65-kgf/umc/ll/u065gioll25mvir/a03/gds/u065gioll25mvir_8m1t0f1u.gds has version number: 5.
****** Merge file: /usr/pack/umc-65-kgf/umc/ll/u065gioll25mvir/a03/gds/u065gioll25mvir_8m1t0f1u.gds has units: 1000 per micron.
****** unit scaling factor = 1 ******
Merging GDS file /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_16384X32X1CM16.gds ......
****** Merge file: /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_16384X32X1CM16.gds has version number: 5.
****** Merge file: /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_16384X32X1CM16.gds has units: 1000 per micron.
****** unit scaling factor = 1 ******
Merging GDS file /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_2048X32X1CM4.gds ......
****** Merge file: /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_2048X32X1CM4.gds has version number: 5.
****** Merge file: /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_2048X32X1CM4.gds has units: 1000 per micron.
****** unit scaling factor = 1 ******
WARNING: Ignoring duplicate structure SHKA_DIDO_GAP.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PRED38_GAP.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XDECGAP_BOT_A3.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_BLMUX_AR4.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10028064.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12083272.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12085362.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12105249.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12105528.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12170460.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12285811.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12359965.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14326535.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14330618.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14337440.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14343616.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23646729.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_6232157.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_6317025.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_6395777.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8298672.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CORNER_BOT.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CORNER_TOP.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CORNER_TOP_R.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DELAY_0.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DELAY_1.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DUMBL2.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DUMBL_GAP.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DUMWL4.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DUMX4_BOT.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DUMX4_TOP.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DUMY2.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DUMY2_R.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DUMY_GAP.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DUM_CORNER_BOT.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DUM_CORNER_TOP.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DVSDEBUG_M1.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_GAR_2001977.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_GAR_3531995.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_MTCH_V2.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_419780_SHKA_BTI_0726.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PRED38.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PRED38_GAP_ANTLAYERS.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PREDLS.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PRED_V2.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_RAM4X2.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_RAM_GAP4.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_V1.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_V2.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_V3.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_WEB_M3.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XDEC2_A3.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XDECGAP_BOT.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XDEC_GAP_A3.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XDEC_V2.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_10008858.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3160920.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3170609.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3205977.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3209960.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3221359.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3228325.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3233103.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3321437.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3425269.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3426521.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3426581.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3452029.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3456148.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3463740.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3478292.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3489149.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3749629.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3835106.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3858135.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3889300.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3940578.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3997181.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4498960.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4822324.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4844500.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5226718.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5335262.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5933202.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6518403.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6548882.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_7725639.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_7873963.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_7945450.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_8056179.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_9660467.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_AY0_AR4.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_BLMUX.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_BLMUX_A.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10037589.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10038316.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10134998.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12085174.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12088082.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12088997.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12099175.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12104264.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12105697.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12106424.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12191805.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12197959.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12278541.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12285084.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12288719.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12292394.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12296247.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12296695.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12296974.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12297701.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12302925.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14323697.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14324086.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14324754.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14325914.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14326039.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14327262.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14327713.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14327989.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14328095.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14328150.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14328264.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14328437.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14328598.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14328877.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14329164.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14329387.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14329443.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14329891.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14329993.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14330103.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14331624.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14335986.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14339621.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23890040.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23970077.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24141245.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24174576.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24220647.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24236789.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24260656.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24353232.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24419738.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24496345.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24507306.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24558188.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24677599.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_27874146.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_6239042.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8302216.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8321376.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8495670.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8513101.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DBLRESET_AR8.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DELAY_0_ANTLAYERS.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_DELAY_1_ANTLAYERS.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_MATCH_AR8.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_MOSCAPA.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_MOSCAPB.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_MOSCAPC.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_433080.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PRED38_ANTLAYERS.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_WEB_M3_ANTLAYERS.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XDEC_A.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XDEC_GAP_A1.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_10273994.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_11029292.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_11415054.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_11850288.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_12161762.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_16719629.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_20345153.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_2819235.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3213362.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_34797202.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_34873714.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3511167.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3731140.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3905988.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3919509.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3943108.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4012213.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4063591.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4153447.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4197877.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4397290.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4459583.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4476498.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4635864.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4770373.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4829351.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4845450.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4908273.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4922435.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5211455.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5234628.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5409831.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5532826.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5645561.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6051119.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6237011.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6547522.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6567661.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6795078.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6865252.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6905918.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_7498080.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_7536011.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_7549678.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_7689095.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_7705681.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_7922876.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_8555373.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_9307368.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_9411948.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_9515986.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_BLMUX_1.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10017254.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10017533.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10027616.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10027785.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10027895.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10028512.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10029239.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10037868.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10116510.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10117237.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10122860.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10130730.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10131457.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10133112.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10208531.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10218335.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10223111.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10223559.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10938078.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10938526.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10939253.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10939980.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10941174.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10941622.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10950978.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10951426.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10961229.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11039030.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11039478.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11040205.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11040932.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11041659.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11043840.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11046949.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11047675.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11048202.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11049656.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11049857.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11050584.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11056399.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11057126.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11057853.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11133346.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11136254.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11147199.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11152954.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_11157730.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12082266.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12084447.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12085920.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12086816.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12087543.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12089724.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12090451.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12092632.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12095445.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12095540.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12096267.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12096620.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12164562.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12169006.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12171914.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12174095.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12183946.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12190968.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12191416.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12192143.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12192870.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12193597.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12193750.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12194324.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12195051.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12195578.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12196505.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12197232.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12198686.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12199413.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12200867.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12201220.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12201594.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12201947.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12202321.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12203048.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12203775.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12204502.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12205229.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12208137.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12208864.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12211772.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12212499.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12247479.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12248654.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12251562.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12277087.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12277814.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12282903.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12286443.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12291219.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12291667.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12301471.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14324145.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14326366.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14326645.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14326983.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14329156.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14332799.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23647287.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23647456.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23647566.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23647735.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23648293.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23648403.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23648462.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23648572.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23648851.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23648910.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23649189.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23649916.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23651370.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23655005.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23657186.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23657913.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23816956.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23816956_FSE0K_A.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23817034.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23863283.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23863361.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23870314.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23889962.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23909610.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23909688.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23936289.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23950351.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23956015.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23982616.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23982694.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24002342.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24028943.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24075270.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24214251.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24233977.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24306667.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24677521.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24697247.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_24955483.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_5194519.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_6233053.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_6233660.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_6234108.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_6238594.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_6444266.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_7255157.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_7263802.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8301489.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8301768.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8311572.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8507794.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8512374.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8882870.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8893122.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8978392.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8978840.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_9073867.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_9079091.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_GAR_2089412.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_413100_F.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_413100_SHKA_BTI_0726.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_413640_SHKA_BTI_0726.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_419780_F.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_432540_F.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_463937_F.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_465759_F.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_465999_F.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XDIODE.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_10086253.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_1588363.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_1588781.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_1614729.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_2616968.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_2690537.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_2813413.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3103705.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3193058.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3209137.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3221112.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3231597.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3259615.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3321377.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3410806.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3491211.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3564189.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3599675.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3617789.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3628757.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3694584.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3749060.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3751739.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3798684.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3821577.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3829603.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3846795.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3852026.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3858131.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3924940.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4018282.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4035586.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4129886.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4145097.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4311763.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4339723.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4421332.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4423521.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4428877.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4437005.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4444940.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4466863.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4525653.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4553147.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4553698.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4593509.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4634404.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4642245.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4681731.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4701908.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4709585.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4734365.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4837950.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4845075.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4855525.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4912583.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4952643.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5005409.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5023948.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5052505.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5064787.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5075321.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5095161.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5125877.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5238456.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5352850.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5471841.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5484265.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5499185.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5504434.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5569190.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5607136.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5757317.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5799040.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5934895.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5955236.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6153764.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6199865.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6272006.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6276061.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6726858.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6802803.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6870134.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_6956844.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_8555162.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_8647761.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10017981.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_10027337.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12082545.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12082993.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12083720.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12085641.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12086089.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12088270.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12095893.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12169733.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_12195778.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_14325081.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_23909610_FSE0K_A.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_25026146.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_6243464.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8312020.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_CON_8312747.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_358840.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_413100_FSE0K_A.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_413640_FSE0K_A.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_420640.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_433400.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_438901.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_464477.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_464717.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_467581_SHKA_BTI_0726.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_467821_SHKA_BTI_0726.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_468121.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_468361.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3431959.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3597012.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3722489.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_3858075.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4009666.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4258831.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4307140.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_4405335.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_XTR_5574242.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_413100_1_FSE0K_A.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_413640_1_FSE0K_A.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_419780_FSE0K_A.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_432540_SHKA_BTI_0726.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_463937_SHKA_BTI_0726.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_464177.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_465759_SHKA_BTI_0726.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_465999_SHKA_BTI_0726.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_466299_SHKA_BTI_0726.
A structure with the same name already exists in one of the merging GDSII files.
WARNING: Ignoring duplicate structure SHKA_PCO_466539.
A structure with the same name already exists in one of the merging GDSII files.
There are 529 structures ignored in file /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SHKA65_2048X32X1CM4.gds
Merging GDS file /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SYKA65_2048X32X1CM8.gds ......
****** Merge file: /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SYKA65_2048X32X1CM8.gds has version number: 5.
****** Merge file: /usr/pack//umc-65-kgf/faraday/ll/memaker/200901.1.2/gdsii.dz/SYKA65_2048X32X1CM8.gds has units: 1000 per micron.
****** unit scaling factor = 1 ******
Output for cells
######Streamout is finished!
setAnalysisMode -checkType setup
set_global timing_recompute_sdf_in_setuphold_mode true