############################################################
## Copyright: 2011 Integrated Sytems Laboratory, ETH Zurich
## http://www.iis.ee.ethz.ch/~sha3
############################################################
##########################################################################
# Design Setings
##########################################################################
set DESIGNNAME "shabziger"
set timeRepDir "timingReports_final"
##########################################################################
# General Setings
##########################################################################
#set tempArea /scratch/$env(USER)/
#if {![file exists $tempArea]} {
# file mkdir $tempArea
#}
#rm -r $env(TMPDIR)
#ln -s $tempArea/tmp $env(TMPDIR) .
setTrialRouteMode -useM1 true
setMultiCpuUsage -localCpu max
#set_global timing_enable_multi_threaded_reporting true
#set_table_style -no_frame_fix_width -nosplit
#set_table_style -no_frame_fix_width
##########################################################################
# load Config & FP
##########################################################################
loadConfig ./src/${DESIGNNAME}.conf 0
# copy first setup view to ui_timinglib,max
::Rda_Design::Input::mmmc:copy
commitConfig
floorPlan -site CORE -d 1875 1875 60 60 60 60
source scripts/fillperi-insert.tcl
fit
##########################################################################
# debug constrains
##########################################################################
#report_clocks
#all_constraint_modes
#check_timing
#type: clocks, endpoints, inputs, nets, loops, clock_clipping, clock_gating_inferred and constant_collision.
#check_timing -verbose -type clocks > check_timing.clocks.rpt
##########################################################################
# place RAM macros
##########################################################################
# for instance
# probably it would be better to leave some space at the top for the
# buffers that go to the pins
#setObjFPlanBox Instance top/i_RAM3 148.8 1126.975 771.26 1726.2
#setObjFPlanBox Instance top/i_RAM3 164.2 1111.575 786.66 1710.8
#setObjFPlanBox Instance top/i_RAM2 1506.94 1389.375 1726.2 1726.2
#setObjFPlanBox Instance top/i_RAM1 1075.049 1533.33 1408.899 1726.2
#setObjFPlanBox Instance top/i_RAM3 164.2 1110.975 786.66 1710.2
#setObjFPlanBox Instance top/i_RAM2 1490.94 1373.375 1710.2 1710.2
#setObjFPlanBox Instance top/i_RAM1 1075.049 1517.33 1408.899 1710.2
setObjFPlanBox Instance top/i_RAM3 168.0 1110.975 790.36 1710.2
setObjFPlanBox Instance top/i_RAM2 1481.65 1373.375 1696.051 1710.2
setObjFPlanBox Instance top/i_RAM1 1081.19 1517.33 1419.899 1710.2
#addHaloToBlock 10 10 10 10 top/i_RAM3
#addHaloToBlock 10 10 10 10 top/i_RAM2
#addHaloToBlock 10 10 10 10 top/i_RAM1
# Add halo and fix ram instances
# If there is a way to set the instances fixed wothout dbSet
# I would be happy..
foreach rname {RAM1 RAM2 RAM3} {
addHaloToBlock 10 10 10 10 top/i_${rname}
selectInst top/i_${rname}
dbSet selected.pStatus fixed
}
createObstruct 148.8 1101.0 158.0 1110.975
createObstruct 148.8 1709.4 158.0 1720.2
createObstruct 1710.8 1711.0 1726.2 1720.2
createObstruct 1710.8 1363.375 1726.2 1374.6
# we need to remove the rows here
cutRow
#addRoutingHalo -space 0 -top ME8 -bottom ME1 -allBlocks
#relativePlace top/i_RAM3 CORE -alignedBy T -orientation R0
#relativePlace top/i_RAM2 CORE -alignedBy T -orientation R0
#relativePlace top/i_RAM1 CORE -alignedBy TR -orientation R0
redraw
##########################################################################
# power Route
##########################################################################
source scripts/shabziger_grid.tcl
##########################################################################
# Placement
##########################################################################
source scripts/welltap.tcl
#setPlaceMode -reorderScan false -modulePlan false
#setPlaceMode -congEffort medium \
# -timingDriven 0 \
# -modulePlan 1 \
# -doCongOpt 0 \
# -ignoreScan 1 \
# -reorderScan 0
# moduleplan is multi-threaded.. important detail :)
## KGF1 timedriven + module plan + rpSpreadEffort
setPlaceMode -congEffort high \
-timingDriven 1 \
-modulePlan 1 \
-doCongOpt 0 \
-ignoreScan 0 \
-reorderScan 0 \
-rpSpreadEffort high
placeDesign -prePlaceOpt
source scripts/tiehilo.tcl
# saveDesign save/chip_${DESIGNNAME}.place.enc
##########################################################################
# time Opt
##########################################################################
optDesign -preCTS -drv -outDir ${timeRepDir} -prefix ${DESIGNNAME}_preCTS-drv
#timedesign -reportOnly -outDir ${timeRepDir} -prefix ${DESIGNNAME}.preCTS-drv
timedesign -reportOnly -expandedViews -outDir ${timeRepDir} -prefix ${DESIGNNAME}.preCTS-drv.expV
setOptMode -setupTargetSlack -.050
optDesign -preCTS -outDir ${timeRepDir} -prefix ${DESIGNNAME}.preCTS-opt
#timedesign -preCTS -outDir ${timeRepDir} -prefix ${DESIGNNAME}.preCTS-opt
timedesign -reportOnly -expandedViews -outDir ${timeRepDir} -prefix ${DESIGNNAME}.preCTS-opt.expV
#wireload -instanceBased -outfile preCTS
saveDesign save/chip_${DESIGNNAME}.preCTS-opt.enc
##########################################################################
# CTS
##########################################################################
setCTSMode -reportHTML true
clockDesign -specFile src/${DESIGNNAME}.ctstch -outDir ${timeRepDir} -fixedInstBeforeCTS
#exec mv *.ctsrpt* ${timeRepDir}/..
#exec rm *.rguide *.cts_trace
timedesign -reportOnly -expandedViews -outDir ${timeRepDir} -prefix ${DESIGNNAME}.postCTS.expV
setOptMode -setupTargetSlack -.050
optDesign -postCTS -outDir ${timeRepDir}
timedesign -reportOnly -expandedViews -outDir ${timeRepDir} -prefix ${DESIGNNAME}.postCTS-opt.expV
#wireload -instanceBased -outfile postCTS
saveDesign save/chip_${DESIGNNAME}_postCTS.enc
##########################################################################
# route
##########################################################################
setNanoRouteMode -quiet -routeInsertAntennaDiode 1
setNanoRouteMode -quiet -routeWithTimingDriven 1
setNanoRouteMode -quiet -drouteStartIteration default
setNanoRouteMode -quiet -routeTopRoutingLayer default
setNanoRouteMode -quiet -routeBottomRoutingLayer default
setNanoRouteMode -quiet -drouteEndIteration default
setNanoRouteMode -quiet -routeWithTimingDriven true
setNanoRouteMode -quiet -routeWithSiDriven false
routeDesign -globalDetail
saveDesign save/chip_${DESIGNNAME}_routed.enc
#wireload -instanceBased -outfile postRoute
##########################################################################
# time Opt
##########################################################################
setExtractRCMode -engine postRoute -effortLevel low -coupled false -reduce 0.0
## hold
timedesign -postroute -hold -outDir ${timeRepDir}
##setOptMode -holdTargetSlack 0.2
##optDesign -postroute -hold
## setup
timedesign -expandedViews -postroute -outDir ${timeRepDir} -prefix ${DESIGNNAME}.postroute.expV
setOptMode -setupTargetSlack 0
optDesign -postroute -outDir ${timeRepDir} -prefix ${DESIGNNAME}.postrouteopt
timedesign -expandedViews -reportOnly -outDir ${timeRepDir} -prefix ${DESIGNNAME}.postrouteopt.expV
## do not run these automatically, only if there is need
## One more optimize..
#setOptMode -setupTargetSlack 0
#optDesign -postroute -outDir ${timeRepDir} -prefix ${DESIGNNAME}.postrouteopt2
#timedesign -expandedViews -reportOnly -outDir ${timeRepDir} -prefix ${DESIGNNAME}.postrouteopt2.expV
#saveDesign save/chip_${DESIGNNAME}_final2.enc
## One more optimize..
#setOptMode -setupTargetSlack 0.06
#optDesign -postroute -outDir ${timeRepDir} -prefix ${DESIGNNAME}.postrouteopt3
#timedesign -expandedViews -reportOnly -outDir ${timeRepDir} -prefix ${DESIGNNAME}.postrouteopt3.expV
#saveDesign save/chip_${DESIGNNAME}_final3.enc
##########################################################################
# Insert Filler Cells
##########################################################################
source scripts/fillcore-insert.tcl
#wireload -instanceBased -outfile RoutedOpt
saveDesign save/chip_${DESIGNNAME}_final.enc
# saveDesign save/chip_${DESIGNNAME}_fillcore.enc
##########################################################################
# verify
##########################################################################
#source scripts/checkdesign.tcl
##########################################################################
# Save files
##########################################################################
source scripts/shabziger_exportall.tcl