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## Copyright: 2011 Integrated Sytems Laboratory, ETH Zurich
## http://www.iis.ee.ethz.ch/~sha3
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# power grid creation
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# v1.2 - - Mon Sep 19 16:00:23 CEST 2011
# - swap addStripe
# v1.2 - - Mon Sep 19 10:09:02 CEST 2011
# - increased the spacing around the cores
# v1.1 - - Fri Sep 16 18:20:23 CEST 201
# - added small rings around all four sides of the RAMs
# v1.0 - bm - Tue Sep 13 10:46:04 CEST 2011
# - source shabziger_globalnet.tcl
# v0.1 - bm - Mon Aug 8 14:28:53 CEST 2011
# - copy from umcL130 v0.4 and mod
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## Strong recommended Floorplan sizes
# floorPlan -site CORE -d 1875 1875 60 60 60 60
## let us start with a cleanup
deleteAllPowerPreroutes
clearDrc
## just to be safe
source scripts/shabziger_globalnet.tcl
## standard cell and routing information settings
set cellHeight 1.8
set routGrid 0.2
## Ring settings
set pgr1LayerH ME1
set pgr1LayerV ME2
set pgr2LayerH ME3
set pgr2LayerV ME4
set pgr3LayerH ME5
set pgr3LayerV ME6
set pgr4LayerH ME7
set pgr4LayerV ME8
set pgrSpacing 2
set pgrWidth 12
set pgrOffset 2
set pgrNet "$rda_Input(ui_gndnet) $rda_Input(ui_pwrnet) $rda_Input(ui_gndnet) $rda_Input(ui_pwrnet)"
## Grid settings for UMC65
set grLayerH $pgr4LayerH
set grLayerV $pgr4LayerV
#set grWidthX [expr $routGrid * 10]
set grWidthX [expr $routGrid * 30]
set grWidthY [expr $routGrid * 3]
set grSpacingX [expr $grWidthX * 4 - $grWidthX]
set grSpacingY [expr $routGrid * 26 - $grWidthY]
set grDistanceX [expr $grWidthX * 8]
set grDistanceY [expr $cellHeight * 6]
#set grOffsetX [expr $grWidthX * 1.5 + (0.5 * $routGrid)]
set grOffsetX [expr 23 + (0.5 * $routGrid)]
set grOffsetY [expr $cellHeight - $grWidthY/2]
set grNet "$rda_Input(ui_gndnet) $rda_Input(ui_pwrnet)"
## Core Rings creation and connection at all levels
addRing -spacing_top $pgrSpacing -spacing_bottom $pgrSpacing -spacing_right $pgrSpacing -spacing_left $pgrSpacing \
-width_top $pgrWidth -width_bottom $pgrWidth -width_right $pgrWidth -width_left $pgrWidth \
-offset_top $pgrOffset -offset_bottom $pgrOffset -offset_right $pgrOffset -offset_left $pgrOffset \
-layer_top $pgr1LayerH -layer_bottom $pgr1LayerH -layer_right $pgr1LayerV -layer_left $pgr1LayerV \
-stacked_via_top_layer metal8 -stacked_via_bottom_layer metal1 \
-around core -follow core -use_wire_group 1 \
-nets $pgrNet
addRing -spacing_top $pgrSpacing -spacing_bottom $pgrSpacing -spacing_right $pgrSpacing -spacing_left $pgrSpacing \
-width_top $pgrWidth -width_bottom $pgrWidth -width_right $pgrWidth -width_left $pgrWidth \
-offset_top $pgrOffset -offset_bottom $pgrOffset -offset_right $pgrOffset -offset_left $pgrOffset \
-layer_top $pgr2LayerH -layer_bottom $pgr2LayerH -layer_right $pgr2LayerV -layer_left $pgr2LayerV \
-stacked_via_top_layer metal8 -stacked_via_bottom_layer metal1 \
-around core -follow core -use_wire_group 1 \
-nets $pgrNet
addRing -spacing_top $pgrSpacing -spacing_bottom $pgrSpacing -spacing_right $pgrSpacing -spacing_left $pgrSpacing \
-width_top $pgrWidth -width_bottom $pgrWidth -width_right $pgrWidth -width_left $pgrWidth \
-offset_top $pgrOffset -offset_bottom $pgrOffset -offset_right $pgrOffset -offset_left $pgrOffset \
-layer_top $pgr3LayerH -layer_bottom $pgr3LayerH -layer_right $pgr3LayerV -layer_left $pgr3LayerV \
-stacked_via_top_layer metal8 -stacked_via_bottom_layer metal1 \
-around core -follow core -use_wire_group 1 \
-nets $pgrNet
addRing -spacing_top $pgrSpacing -spacing_bottom $pgrSpacing -spacing_right $pgrSpacing -spacing_left $pgrSpacing \
-width_top $pgrWidth -width_bottom $pgrWidth -width_right $pgrWidth -width_left $pgrWidth \
-offset_top $pgrOffset -offset_bottom $pgrOffset -offset_right $pgrOffset -offset_left $pgrOffset \
-layer_top $pgr4LayerH -layer_bottom $pgr4LayerH -layer_right $pgr4LayerV -layer_left $pgr4LayerV \
-stacked_via_top_layer metal8 -stacked_via_bottom_layer metal1 \
-around core -follow core -use_wire_group 1 \
-nets $pgrNet
## for the RAMS
set corepgrSpacing 2
set corepgrWidth 3
set corepgrOffset 1
selectInst top/i_RAM3
addRing -spacing_top $corepgrSpacing -spacing_bottom $corepgrSpacing -spacing_right $corepgrSpacing -spacing_left $corepgrSpacing \
-width_top $corepgrWidth -width_bottom $corepgrWidth -width_right $corepgrWidth -width_left $corepgrWidth \
-offset_top $corepgrOffset -offset_bottom $corepgrOffset -offset_right $corepgrOffset -offset_left $corepgrOffset \
-layer_top ME1 -layer_bottom ME1 -layer_right ME2 -layer_left ME2 \
-stacked_via_top_layer ME8 -stacked_via_bottom_layer ME1 \
-bl 1 -rt 1 \
-around selected -jog_distance 0.1 -threshold 0.1 -type block_rings \
-use_wire_group 1 -nets $grNet
selectInst top/i_RAM2
addRing -spacing_top $corepgrSpacing -spacing_bottom $corepgrSpacing -spacing_right $corepgrSpacing -spacing_left $corepgrSpacing \
-width_top $corepgrWidth -width_bottom $corepgrWidth -width_right $corepgrWidth -width_left $corepgrWidth \
-offset_top $corepgrOffset -offset_bottom $corepgrOffset -offset_right $corepgrOffset -offset_left $corepgrOffset \
-layer_top ME1 -layer_bottom ME1 -layer_right ME2 -layer_left ME2 \
-stacked_via_top_layer ME8 -stacked_via_bottom_layer ME1 \
-br 1 -lt 1 \
-around selected -jog_distance 0.1 -threshold 0.1 -type block_rings \
-use_wire_group 1 -nets $grNet
selectInst top/i_RAM1
addRing -spacing_top $corepgrSpacing -spacing_bottom $corepgrSpacing -spacing_right $corepgrSpacing -spacing_left $corepgrSpacing \
-width_top $corepgrWidth -width_bottom $corepgrWidth -width_right $corepgrWidth -width_left $corepgrWidth \
-offset_top $corepgrOffset -offset_bottom $corepgrOffset -offset_right $corepgrOffset -offset_left $corepgrOffset \
-layer_top ME1 -layer_bottom ME1 -layer_right ME2 -layer_left ME2 \
-stacked_via_top_layer ME8 -stacked_via_bottom_layer ME1 \
-rt 1 -lt 1 \
-around selected -jog_distance 0.1 -threshold 0.1 -type block_rings \
-use_wire_group 1 -nets $grNet
# connect power pads to power rings
sroute -connect { padPin } -padPinPortConnect { allPort preferLayer } -padPinLayerRange [list $pgr1LayerV $pgr3LayerV ] \
-allowJogging 1 -allowLayerChange 1 -targetViaTopLayer $pgr3LayerV -crossoverViaTopLayer $pgr3LayerV
sroute -connect { padPin } -padPinPortConnect { allPort preferLayer } -padPinLayerRange [list $pgr4LayerH $pgr4LayerV ] \
-allowJogging 0 -allowLayerChange 1
## Grid creation and connection
setAddStripeMode -trim_antenna_back_to_shape stripe
#setAddStripeMode -detailed_log true
addStripe -set_to_set_distance $grDistanceY -ybottom_offset $grOffsetY -spacing $grSpacingY -width $grWidthY \
-allow_jog_padcore_ring 0 -same_layer_target_only 1 -max_same_layer_jog_length 4 \
-direction horizontal -layer $grLayerH -padcore_ring_bottom_layer_limit ME6 \
-nets $grNet
addStripe -set_to_set_distance $grDistanceX -spacing $grSpacingX -xleft_offset $grOffsetX -width $grWidthX \
-allow_jog_padcore_ring 0 -same_layer_target_only 1 -max_same_layer_jog_length 4 \
-layer $grLayerV \
-nets $grNet
# connect macros
# names on the LEF are different
globalNetConnect VDD -type pgpin -pin VCC -inst i_RAM*
globalNetConnect VSS -type pgpin -pin GND -inst i_RAM*
# does not connect at the moment ??
sroute -connect { blockPin } -blockPinRouteWithPinWidth \
-blockPin { all } -nets $grNet
# connect std cells
sroute -connect { corePin } \
-allowLayerChange 1 \
-targetPenetration { stripe 90 }
redraw