create_clock -period  10 [get_ports {ClkxCI}]
set_propagated_clock [get_ports {ClkxCI}]

set_case_analysis 0 [get_ports {ClkDxCI}]
set_case_analysis 0 [get_ports {FuncScanEnxTI}]
set_case_analysis 0 [get_ports {CoreScanEnxTI}]

## The following are our test inputs, they are not required during the normal
## mode.
set_false_path -from [get_ports {FuncScanEnxTI}]
set_false_path -from [get_ports {CoreScanEnxTI}]

## select algorithm
set_case_analysis 1 AlgSelxSI\[0\]
set_case_analysis 1 AlgSelxSI\[1\]
set_case_analysis 1 AlgSelxSI\[2\]
set_case_analysis 0 AlgSelxSI\[3\]

## disable timing in all other cores 
set_disable_timing [get_cells  -hierarchical -regexp top/i_ethz_sha2/.*]
set_disable_timing [get_cells  -hierarchical -regexp top/i_ethz_blake/.*]
set_disable_timing [get_cells  -hierarchical -regexp top/i_ethz_groestl/.*]
set_disable_timing [get_cells  -hierarchical -regexp top/i_ethz_jh/.*]
set_disable_timing [get_cells  -hierarchical -regexp top/i_ethz_keccak/.*]
set_disable_timing [get_cells  -hierarchical -regexp top/i_ethz_skein/.*]
set_disable_timing [get_cells  -hierarchical -regexp top/i_gmu_sha2/.*]
set_disable_timing [get_cells  -hierarchical -regexp top/i_gmu_blake/.*]
set_disable_timing [get_cells  -hierarchical -regexp top/i_gmu_groestl/.*]
set_disable_timing [get_cells  -hierarchical -regexp top/i_gmu_jh/.*]
set_disable_timing [get_cells  -hierarchical -regexp top/i_gmu_keccak/.*]
set_disable_timing [get_cells  -hierarchical -regexp top/i_gmu_skein/.*]