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-- Copyright: 2011 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
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-------------------------------------------------------------------------------
-- Title      : Clock gate RTL description
-- Project    : 
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-- File       : clockgate.vhd
-- Author     : Frank K. Guerkaynak  
-- Company    : Integrated Systems Laboratory, ETH Zurich
-- Created    : 2011-08-25
-- Last update: 2011-08-25
-- Platform   : ModelSim (simulation), Synopsys (synthesis)
-- Standard   : VHDL'87
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-- Description: This is an instance so that we can gate clock both in RTL and
--              gatelevel 
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-- Copyright (c) 2011 Integrated Systems Laboratory, ETH Zurich
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-- Revisions  :
-- Date        Version  Author  Description
-- 2011-08-25  1.0      kgf	Created
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library ieee;
use ieee.std_logic_1164.all;

entity clockgate is
  
  port (
    ClkInxCI  : in  std_logic;
    EnxSI     : in  std_logic;
    ClkOutxCO : out std_logic);

end clockgate;

architecture rtl of clockgate is

 signal LatchOutxD : std_logic;
  
begin  -- rtl
  -- should compile to LAGCE in UMC65LL
  
  -- first a latch
  p_latch: process (EnxSI, ClkInxCI)
  begin  -- process p_latch
    if ClkInxCI = '1' then  -- rising clock edge
      LatchOutxD <= EnxSI;
    end if;
  end process p_latch;

  
  -- followed by an AND
  ClkOutxCO <= LatchOutxD and ClkInxCI;
  

end rtl;