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-- Copyright: 2011 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
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-- Title      : Testbench for design "inputblock"
-- Project    : 
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-- File       : inputblock_tb.vhd
-- Author     : Frank K. Guerkaynak  
-- Company    : Integrated Systems Laboratory, ETH Zurich
-- Created    : 2011-08-16
-- Last update: 2011-08-16
-- Platform   : ModelSim (simulation), Synopsys (synthesis)
-- Standard   : VHDL'87
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-- Description: 
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-- Copyright (c) 2011 Integrated Systems Laboratory, ETH Zurich
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-- Revisions  :
-- Date        Version  Author  Description
-- 2011-08-16  1.0      kgf	Created
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library ieee;
use ieee.std_logic_1164.all;
use work.shabzigerpkg.all;

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entity inputblock_tb is

end inputblock_tb;

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architecture test of inputblock_tb is

  component inputblock
    port (
      AlgSelxSI           : in  std_logic_vector(3 downto 0);
      ClkxCI              : in  std_logic;
      RstxRBI             : in  std_logic;
      FinalBlockxSI       : in  std_logic;
      BlockPenUltCyclexSI : in  std_logic;
      BlockInEnxSO        : out std_logic;
      BlockFinBlockxSO    : out std_logic;
      ScanEnxTI           : in  std_logic;
      ScanInxTI           : in  std_logic;
      ScanOutxTO          : out std_logic;
      DataCntxDO          : out std_logic_vector(63 downto 0);
      DataOutxDO          : out std_logic_vector(1087 downto 0));
  end component;

  component keccak
    port (
      ClkxCI         : in  std_logic;
      RstxRBI        : in  std_logic;
      FinBlockxSI    : in  std_logic;
      INENxEI        : in  std_logic;
      OUTENxEO       : out std_logic;
      PenUltCyclexSO : out std_logic;
      DxDI           : in  std_logic_vector(1087 downto 0);
      DxDO           : out std_logic_vector(255 downto 0));
  end component;

  
  -- component ports
  signal AlgSelxS           : std_logic_vector(3 downto 0);
  signal RstxRB             : std_logic;
  signal FinalBlockxS       : std_logic;
  signal BlockPenUltCyclexS : std_logic;
  signal BlockInEnxS        : std_logic;
  signal BlockFinBlockxS    : std_logic;
  signal ScanEnxT           : std_logic;
  signal ScanInxT           : std_logic;
  signal ScanOutxT          : std_logic;
  signal DataCntxD          : std_logic_vector(63 downto 0);
  signal DataOutxD          : std_logic_vector(1087 downto 0);
  signal DxD                : std_logic_vector(255 downto 0);
  signal OUTENxE            : std_logic;
  
  -- clock
  signal ClkxC : std_logic := '1';

begin  -- test

  -- component instantiation
  DUT: inputblock
    port map (
      AlgSelxSI           => AlgSelxS,
      ClkxCI              => ClkxC,
      RstxRBI             => RstxRB,
      FinalBlockxSI       => FinalBlockxS,
      BlockPenUltCyclexSI => BlockPenUltCyclexS,
      BlockInEnxSO        => BlockInEnxS,
      BlockFinBlockxSO    => BlockFinBlockxS,
      ScanEnxTI           => ScanEnxT,
      ScanInxTI           => ScanInxT,
      ScanOutxTO          => ScanOutxT,
      DataCntxDO          => DataCntxD,
      DataOutxDO          => DataOutxD);


  i_keccak: keccak
    port map (
      ClkxCI         => ClkxC,
      RstxRBI        => RstxRB,
      FinBlockxSI    => BlockFinBlockxS,
      INENxEI        => BlockInEnxS,
      OUTENxEO       => OUTENxE,
      PenUltCyclexSO => BlockPenUltCyclexS,
      DxDI           => DataOutxD,
      DxDO           => DxD);

  
  -- clock generation
  ClkxC <= not ClkxC after 5 ns;

  -- waveform generation
  WaveGen_Proc: process
  begin
    -- insert signal assignments here
    AlgSelxS  <= ETHZKECCAK;
    FinalBlockxS <= '1';
    RstxRB <= '0';
    ScanInxT <= '0';
    ScanEnxT <= '0';
    wait for 2 ns;
    RstxRB <= '1';     
    wait;
  end process WaveGen_Proc;

  

end test;

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configuration inputblock_tb_test_cfg of inputblock_tb is
  for test
  end for;
end inputblock_tb_test_cfg;

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