------------------------------------------------------------
-- Copyright: 2011 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Title      : Padding unit
-- Project    : Shabziger
-------------------------------------------------------------------------------
-- File       : padunit.vhd
-- Author     : Frank K. Guerkaynak  
-- Company    : Integrated Systems Laboratory, ETH Zurich
-- Created    : 2011-08-16
-- Last update: 2011-08-30
-- Platform   : ModelSim (simulation), Synopsys (synthesis)
-- Standard   : VHDL'87
-------------------------------------------------------------------------------
-- Description: This is a simple padding unit at the moment
-------------------------------------------------------------------------------
-- Copyright (c) 2011 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2011-08-16  1.0      kgf	Created
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use work.shabzigerpkg.all;


entity padunit is  
  port (
    DataInxDI  : in  std_logic_vector(1087 downto 0);
    DataOutxDO : out std_logic_vector(1087 downto 0);
    AlgSelxSI  : in  std_logic_vector(3 downto 0);
    DataCntxDI : in  std_logic_vector(63 downto 0)
    );
        
end padunit;

architecture rtl of padunit is
 signal AlgxS : std_logic_vector(2 downto 0);  -- Shorter AlgSelxSI
 constant JHZEROPAD : std_logic_vector(446 downto 0) := (others => '0');
 
begin  -- rtl

  AlgxS <= AlgSelxSI(2 downto 0);
  p_pad_sel: process (AlgxS, DataInxDI, DataCntxDI)
  begin  -- process p_pad_sel
    DataOutxDO <= DataInxDI;
    case AlgxS is
      when KECCAK =>
        DataOutxDO <= DataInxDI(1087 downto 16) & x"0180";
      when BLAKE => 
        DataOutxDO <= DataInxDI(1087 downto 80) & x"8001" & DataCntxDI;
      when GROESTL =>
        DataOutxDO <= DataInxDI(1087 downto 80) & x"8000" & DataCntxDI;
      when SHA2 =>
        DataOutxDO <= DataInxDI(1087 downto 80) & x"8000" & DataCntxDI;
      when JH =>
        DataOutxDO <= DataInxDI(1087 downto 512) & '1'  & JHZEROPAD & DataCntxDI;
      when SKEIN =>
        DataOutxDO <= DataInxDI;
      when others =>
        DataOutxDO <= DataInxDI;
    end case;
  end process p_pad_sel;

end rtl;