------------------------------------------------------------
-- Copyright: 2011 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Title      : simple xor for behaviour modelling
-- Project    : Shabziger
-------------------------------------------------------------------------------
-- File       : sha_xor.vhd
-- Author     : Frank K. Guerkaynak  
-- Company    : Integrated Systems Laboratory, ETH Zurich
-- Created    : 2011-09-01
-- Last update: 2011-09-01
-- Platform   : ModelSim (simulation), Synopsys (synthesis)
-- Standard   : VHDL'87
-------------------------------------------------------------------------------
-- Description: Trick to increase the clock rate 
-------------------------------------------------------------------------------
-- Copyright (c) 2011 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2011-09-01  1.0      kgf	Created
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity sha_xor is
  
  port (
    AxDI : in  std_logic;
    BxDI : in  std_logic;
    ZxDO : out std_logic);

end sha_xor;

architecture rtl of sha_xor is

begin  -- rtl

  -- this is a simpel XOR, we use it to have a pure RTL simulation
  -- without gate delays
  
  ZxDO <=  AxDI xor BxDI;

end rtl;