------------------------------------------------------------ -- Copyright: 2011 Integrated Sytems Laboratory, ETH Zurich -- http://www.iis.ee.ethz.ch/~sha3 ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Title : The top level file of shabziger -- Project : Shabziger ------------------------------------------------------------------------------- -- File : shabziger.vhd -- Author : Frank K. Guerkaynak -- Company : Integrated Systems Laboratory, ETH Zurich -- Created : 2011-08-24 -- Last update: 2011-09-23 -- Platform : ModelSim (simulation), Synopsys (synthesis) -- Standard : VHDL'87 ------------------------------------------------------------------------------- -- Description: This combines all the blocks ------------------------------------------------------------------------------- -- Copyright (c) 2011 Integrated Systems Laboratory, ETH Zurich ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2011-08-24 1.0 kgf Created -- 2011-09-14 1.1 kgf RAMs also get gated clocks -- 2011-09-15 2.0 kgf New inputblock now we have four input registers -- 2011-09-21 2.1 kgf Added a FF to store the value of the -- FinBlockxSI from the inputblock so that it is stored -- 2011-09-23 2.2 kgf Undid the above change We will extract the -- FinblockxS inanother way ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.shabzigerpkg.all; -- the following is to make sure that vsim loads the library -- synopsys does not have a library, it reads individual db files -- synopsys translate_off library fse0k_a_memaker; -- synopsys translate_on entity shabziger is port ( AlgSelxSI : in std_logic_vector(3 downto 0); OutSelxSI : in std_logic_vector(3 downto 0); DataOutxDO : out std_logic_vector(15 downto 0); FinBlockxSI : in std_logic; -- additional Scan data in -- ReservedxDIO : in std_logic_vector(2 downto 0); -- still 3 pins OutWrEnxSO : out std_logic; -- tells that a new output is available -- multiplexed to CoreScanOutxTO InWrEnxSO : out std_logic; -- for monitoring purposes -- multiplexed to FuncScanOutxTO PenUltCyclexSO : out std_logic; -- additional Scan Data out -- Memory MemWrEnxSBI : in std_logic; -- 1: MemWrite 0: MemRead -- Pad Control used for the chip level not connected here PadOutEnxSI : in std_logic; -- test for the pads PadDrive1xSI : in std_logic; -- Pin for pad drive PadDrive2xSI : in std_logic; -- Pin for pad drive PadSlewxSI : in std_logic; -- Slew rate control for the pads -- Scan FuncScanEnxTI : in std_logic; -- Scan enable FuncScanInxTI : in std_logic; -- Scan path through LFSR, input register -- FuncScanOutxTO : out std_logic; -- and output register CoreScanEnxTI : in std_logic; -- scan enable for the cores CoreScanInxTI : in std_logic; -- signal for scan testing of -- CoreScanOutxTO : out std_logic; -- individual cores -- Standard ClkxCI : in std_logic; ClkDxCI : in std_logic; -- Second (delayed) clock for XOR RstxRBI : in std_logic ); end shabziger; architecture rtl of shabziger is ------------------------------------------------------------------------------- -- Components ------------------------------------------------------------------------------- component inputblock port ( AlgSelxSI : in std_logic_vector(3 downto 0); ClkxCI : in std_logic; RstxRBI : in std_logic; FinBlockxSI : in std_logic; BlockPenUltCyclexSI : in std_logic; BlockInWrEnxSO : out std_logic; BlockFinBlockxSO : out std_logic; FuncScanEnxTI : in std_logic; FuncScanInxTI : in std_logic; FuncScanOutxTO : out std_logic; MsgLenxDO : out std_logic_vector(63 downto 0); DataOutxDO : out std_logic_vector(1087 downto 0); Data2OutxDO : out std_logic_vector(511 downto 0); Data3OutxDO : out std_logic_vector(511 downto 0); Data4OutxDO : out std_logic_vector(63 downto 0)); end component; component clockgate port ( ClkInxCI : in std_logic; EnxSI : in std_logic; ClkOutxCO : out std_logic); end component; component sha_xor port ( AxDI : in std_logic; BxDI : in std_logic; ZxDO : out std_logic); end component; -- internal clock signal ClkxC : std_logic; -- signals for interconnection type outdatatype is array (0 to 15) of std_logic_vector(255 downto 0); --type indatatype is array (0 to 15) of std_logic_vector(1087 downto 0); type msglentype is array (0 to 15) of std_logic_vector(63 downto 0); -- connection from the input register signal InxD : std_logic_vector(1087 downto 0); signal In2xD : std_logic_vector(511 downto 0); signal In3xD : std_logic_vector(511 downto 0); signal In4xD : std_logic_vector(63 downto 0); signal MsgLenxD : std_logic_vector(63 downto 0); signal InWrEnxS : std_logic; signal FinBlockxS : std_logic; -- signals that connect all the cores signal CoreOutxD : outdatatype; signal CoreMsgLenxD : msglentype; --signal CoreInxD : indatatype; -- these are now written out separately signal Core0InxD : std_logic_vector(511 downto 0); -- ETHZ-SHA2 signal Core1InxD : std_logic_vector(511 downto 0); -- ETHZ-BLAKE signal Core2InxD : std_logic_vector(511 downto 0); -- ETHZ-GROESTL signal Core3InxD : std_logic_vector(511 downto 0); -- ETHZ-JH signal Core4InxD : std_logic_vector(1087 downto 0); -- ETHZ-KECCAK signal Core5InxD : std_logic_vector(511 downto 0); -- ETHZ-SKEIN signal Core6InxD : std_logic_vector(31 downto 0); -- RAM1 signal Core7InxD : std_logic_vector(31 downto 0); -- RAM2 signal Core8InxD : std_logic_vector(511 downto 0); -- GMU-SHA2 signal Core9InxD : std_logic_vector(511 downto 0); -- GMU-BLAKE signal Core10InxD : std_logic_vector(511 downto 0); -- GMU-GROESTL signal Core11InxD : std_logic_vector(511 downto 0); -- GMU-JH signal Core12InxD : std_logic_vector(1087 downto 0); -- GMU-KECCAK signal Core13InxD : std_logic_vector(511 downto 0); -- GMU-SKEIN signal Core14InxD : std_logic_vector(31 downto 0); -- RAM3 signal Core15InxD : std_logic_vector(63 downto 0); -- DUMMY -- control signals that connect to all cores signal CoreInWrEnxS : std_logic_vector(15 downto 0); signal CoreOutWrEnxS : std_logic_vector(15 downto 0); signal CorePenUltCyclexS : std_logic_vector(15 downto 0); signal CoreFinBlockxS : std_logic_vector(15 downto 0); signal CoreClkEnxS : std_logic_vector(15 downto 0); signal CoreClkxC : std_logic_vector(15 downto 0); -- for input silencing constant ALLZEROES : std_logic_vector(1087 downto 0) := (others => '0'); signal OutRegxDN, OutRegxDP, SelOutxD : std_logic_vector(255 downto 0); signal OutWrEnxSN, OutWrEnxSP, SelOutWrEnxS : std_logic; signal InWrEnxSN, InWrEnxSP, SelInWrEnxS : std_logic; signal PenUltCyclexSN, PenUltCyclexSP, SelPenUltCyclexS : std_logic; signal InBlockScanOutxT : std_logic; -- Stitching the scan chain manually signal CoreScanInxT : std_logic_vector(15 downto 0); signal CoreScanOutxT : std_logic_vector(15 downto 0); signal IntAlgSelxS : integer range 0 to 15; -- signals for weirdness of connections signal ETHZBlakeMsgLenxD : std_logic_vector(63 downto 0); -- Blake length is -- f*cked up -- Signals and Constants for RAM Instantiations constant DVSxD : std_logic_vector(3 downto 0) := "0000"; -- RAM needs this constant OnexD : std_logic := '1'; constant ZeroxD : std_logic := '0'; signal RAM1InxD, RAM1OutxD : std_logic_vector(31 downto 0); signal RAM2InxD, RAM2OutxD : std_logic_vector(31 downto 0); signal RAM3InxD, RAM3OutxD : std_logic_vector(31 downto 0); begin -- rtl ------------------------------------------------------------------------------- -- XOR'ed clock, used to increase the frequency of the clock beyond what can -- go through the pads ------------------------------------------------------------------------------- i_clkxor: sha_xor port map ( AxDI => ClkxCI, -- Main clock input BxDI => ClkDxCI, -- delayed clock for XOR'ed clock ZxDO => ClkxC); -- ClkxC will be the internal clock ------------------------------------------------------------------------------- -- The input block ------------------------------------------------------------------------------- i_inputblock : inputblock port map ( AlgSelxSI => AlgSelxSI, ClkxCI => ClkxC, RstxRBI => RstxRBI, FinBlockxSI => FinBlockxSI, BlockPenUltCyclexSI => SelPenUltCyclexS, BlockInWrEnxSO => InWrEnxS, BlockFinBlockxSO => FinBlockxS, FuncScanEnxTI => FuncScanEnxTI, FuncScanInxTI => FuncScanInxTI, FuncScanOutxTO => InBlockScanOutxT, MsgLenxDO => MsgLenxD, DataOutxDO => InxD, Data2OutxDO => In2xD, Data3OutxDO => In3xD, Data4OutxDO => In4xD); ------------------------------------------------------------------------------- -- Helpful signals ------------------------------------------------------------------------------- IntAlgSelxS <= to_integer(unsigned(AlgSelxSI)); -- makes life easier ------------------------------------------------------------------------------- -- Generate Silenced input signals from the in block to cores ------------------------------------------------------------------------------- p_silence : process (MsgLenxD, IntAlgSelxS, InWrEnxS, FinBlockxS, CoreScanInxTI, FuncScanEnxTI, CoreScanEnxTI) begin -- process p_silence -- by default all of them are zero for i in 0 to 15 loop -- CoreInxD(i) others => '0'); CoreMsgLenxD(i) <= (others => '0'); CoreInWrEnxS(i) <= '0'; CoreFinBlockxS(i) <= '0'; CoreClkEnxS(i) <= '0'; CoreScanInxT(i) <= '0'; end loop; -- i -- only the chosen algorithm keeps the actual message -- CoreInxD(IntAlgSelxS) InxD; CoreMsgLenxD(IntAlgSelxS) <= MsgLenxD; CoreInWrEnxS(IntAlgSelxS) <= InWrEnxS; CoreFinBlockxS(IntAlgSelxS) <= FinBlockxS; CoreScanInxT(IntAlgSelxS) <= CoreScanInxTI; -- only one block -- We will use the funcscan input to initialize the LFSR and the input reg -- as well as reading out the output register. During this time, the cores -- should not do anything, we will simply disable them -- CoreScanEn FuncScanEn CoreClk(Alg) Description -- 0 0 1 Normal operation -- 0 1 0 Load/Unload functional registers -- 1 0 1 Scan core only (test scan chain) -- 1 1 1 Scan test mode, all registers scan if (FuncScanEnxTI = '0') or (CoreScanEnxTI ='1') then CoreClkEnxS(IntAlgSelxS) <= '1'; -- enable of only one block end if; end process p_silence; -- we need a separate process for the inputs. The algorithms are distributed -- to the different registers in the inputblock. So every register drives four -- algorithms. -- InxD 1088 bit : SHA2 and KECCAK -- In2xD 512 bit : BLAKE and GROESTL -- In3xD 512 bit : JH and SKEIN -- In4xD 64 bit : DUMMY and RAM p_datain : process (InxD, In2xD, In3xD, In4xD, AlgSelxSI) begin -- process p_datain -- defaults are all silent Core0InxD <= (others => '0'); Core1InxD <= (others => '0'); Core2InxD <= (others => '0'); Core3InxD <= (others => '0'); Core4InxD <= (others => '0'); Core5InxD <= (others => '0'); Core6InxD <= (others => '0'); Core7InxD <= (others => '0'); Core8InxD <= (others => '0'); Core9InxD <= (others => '0'); Core10InxD <= (others => '0'); Core11InxD <= (others => '0'); Core12InxD <= (others => '0'); Core13InxD <= (others => '0'); Core14InxD <= (others => '0'); Core15InxD <= (others => '0'); case AlgSelxSI is when ETHZSHA2 => Core0InxD <= InxD(511 downto 0); when ETHZBLAKE => Core1InxD <= In2xD; when ETHZGROESTL => Core2InxD <= In2xD; when ETHZJH => Core3InxD <= In3xD; when ETHZKECCAK => Core4InxD <= InxD; when ETHZSKEIN => Core5InxD <= In3xD; when RAM1 => Core6InxD <= In4xD(31 downto 0); when RAM2 => Core7InxD <= In4xD(31 downto 0); when GMUSHA2 => Core8InxD <= InxD(511 downto 0); when GMUBLAKE => Core9InxD <= In2xD; when GMUGROESTL => Core10InxD <= In2xD; when GMUJH => Core11InxD <= In3xD; when GMUKECCAK => Core12InxD <= InxD; when GMUSKEIN => Core13InxD <= In3xD; when RAM3 => Core14InxD <= In4xD(31 downto 0); when others => Core15InxD <= In4xD; end case; end process p_datain; ------------------------------------------------------------------------------- -- The clock gates, instantiate 16 clock gates ------------------------------------------------------------------------------- gen_clock_gates: for i in 0 to 15 generate i_clockgate: clockgate port map ( ClkInxCI => ClkxC, EnxSI => CoreClkEnxS(i), ClkOutxCO => CoreClkxC(i) ); end generate gen_clock_gates; ------------------------------------------------------------------------------- -- Output Register ------------------------------------------------------------------------------- p_outreg: process (OutRegxDP, FuncScanEnxTI, InBlockScanOutxT, SelOutWrEnxS, CoreOutxD, IntAlgSelxS) begin -- process p_outreg OutRegxDN <= OutRegxDP; -- default if FuncScanEnxTI ='1' then OutRegxDN <= OutRegxDP(254 downto 0) & InBlockScanOutxT; else if SelOutWrEnxS ='1' then -- If core has new data OutRegxDN <= CoreOutxD(IntAlgSelxS); end if; end if; end process p_outreg; -- Select the output control signals SelOutWrEnxS <= CoreOutWrEnxS(IntAlgSelxS); SelPenUltCyclexS <= CorePenUltCyclexS(IntAlgSelxS); SelInWrEnxS <= CoreInWrEnxS(IntAlgSelxS); -- next states of internal signals that will be registered OutWrEnxSN <= SelOutWrEnxS; PenUltCyclexSN <= SelPenUltCyclexS; InWrEnxSN <= InWrEnxS; -- outputs of internal signal that are registered -- during scan it is multiplexed OutWrEnxSO <= OutWrEnxSP when CoreScanEnxTI = '0' else CoreScanOutxT(IntAlgSelxS); -- CoreScanOutxTO CoreScanOutxT(IntAlgSelxS); -- select one of cores PenUltCyclexSO <= PenUltCyclexSP; InWrEnxSO <= InWrEnxSP when FuncScanEnxTI = '0' else OutRegxDP(255); -- FuncScanOutxTO OutRegxDP(255); -- manual scan chain ------------------------------------------------------------------------------- -- Output Multiplexer ------------------------------------------------------------------------------- with OutSelxSI select DataOutxDO <= OutRegxDP( 15 downto 0) when "0000", OutRegxDP( 31 downto 16) when "0001", OutRegxDP( 47 downto 32) when "0010", OutRegxDP( 63 downto 48) when "0011", OutRegxDP( 79 downto 64) when "0100", OutRegxDP( 95 downto 80) when "0101", OutRegxDP(111 downto 96) when "0110", OutRegxDP(127 downto 112) when "0111", OutRegxDP(143 downto 128) when "1000", OutRegxDP(159 downto 144) when "1001", OutRegxDP(175 downto 160) when "1010", OutRegxDP(191 downto 176) when "1011", OutRegxDP(207 downto 192) when "1100", OutRegxDP(223 downto 208) when "1101", OutRegxDP(239 downto 224) when "1110", OutRegxDP(255 downto 240) when others; ------------------------------------------------------------------------------- -- Clocked process ------------------------------------------------------------------------------- p_clk : process (ClkxC, RstxRBI) begin -- process p_clk if RstxRBI = '0' then -- asynchronous reset (active low) OutRegxDP <= (others => '0'); OutWrEnxSP <= '0'; PenUltCyclexSP <= '0'; InWrEnxSP <= '0'; elsif ClkxC'event and ClkxC = '1' then -- rising clock edge OutRegxDP <= OutRegxDN; OutWrEnxSP <= OutWrEnxSN; PenUltCyclexSP <= PenUltCyclexSN; InWrEnxSP <= InWrEnxSN; end if; end process p_clk; ------------------------------------------------------------------------------- -- Instantiate all the cores here ------------------------------------------------------------------------------- -- use the ./scripts/all_instantiations.pl to generate the bulk -- it won't work perfectly ETHZ_Blake and ETHZ_SHA2 have some additional problems -- there will be still three RAM instances which will fit in here ------------------------------------------------------------------------------- -- ethz_sha2 - IntAlgSelxS == 0 -- -- Funny connections FirstBlockxSI ReadyxSO i_ethz_sha2 : ethz_sha2 port map (ClkxCI => CoreClkxC(0), ScanInxTI => CoreScanInxT(0), ScanEnxTI => CoreScanEnxTI, ScanOutxTO => CoreScanOutxT(0), InWrEnxSI => CoreInWrEnxS(0), OutWrEnxSO => CoreOutWrEnxS(0), HOutxDO => CoreOutxD(0), FinBlockxSI => CoreFinBlockxS(0), PenUltCyclexSO => CorePenUltCyclexS(0), TextInxDI => Core0InxD, RstxRBI => RstxRBI); ------------------------------------------------------------------------------- -- ethz_blake - IntAlgSelxS == 1 -- weird renaming ETHZBlakeMsgLenxD <= CoreMsgLenxD(1)(31 downto 0) & CoreMsgLenxD(1)(63 downto 32); i_ethz_blake : ethz_blake port map (ClkxCI => CoreClkxC(1), ScanInxTI => CoreScanInxT(1), ScanEnxTI => CoreScanEnxTI, ScanOutxTO => CoreScanOutxT(1), InWrEnxSI => CoreInWrEnxS(1), OutWrEnxSO => CoreOutWrEnxS(1), HxDO => CoreOutxD(1), FinBlockxSI => CoreFinBlockxS(1), PenUltCyclexSO => CorePenUltCyclexS(1), MxDI => Core1InxD, SxDI => ALLZEROES(127 downto 0), MsgLenxDI => ETHZBlakeMsgLenxD, RstxRBI => RstxRBI); ------------------------------------------------------------------------------- -- ethz_groestl - IntAlgSelxS == 2 i_ethz_groestl : ethz_groestl port map (ClkxCI => CoreClkxC(2), ScanInxTI => CoreScanInxT(2), ScanEnxTI => CoreScanEnxTI, ScanOutxTO => CoreScanOutxT(2), InWrEnxSI => CoreInWrEnxS(2), OutWrEnxSO => CoreOutWrEnxS(2), HashOutxDO => CoreOutxD(2), FinBlockxSI => CoreFinBlockxS(2), PenUltCyclexSO => CorePenUltCyclexS(2), MsgInxDI => Core2InxD, RstxRBI => RstxRBI); ------------------------------------------------------------------------------- -- ethz_jh - IntAlgSelxS == 3 i_ethz_jh : ethz_jh port map (ClkxCI => CoreClkxC(3), ScanInxTI => CoreScanInxT(3), ScanEnxTI => CoreScanEnxTI, ScanOutxTO => CoreScanOutxT(3), InWrEnxSI => CoreInWrEnxS(3), OutWrEnxSO => CoreOutWrEnxS(3), HashOutxDO => CoreOutxD(3), FinBlockxSI => CoreFinBlockxS(3), PenUltCyclexSO => CorePenUltCyclexS(3), MsgInxDI => Core3InxD, RstxRBI => RstxRBI); ------------------------------------------------------------------------------- -- ethz_keccak - IntAlgSelxS == 4 i_ethz_keccak : ethz_keccak port map (ClkxCI => CoreClkxC(4), ScanInxTI => CoreScanInxT(4), ScanEnxTI => CoreScanEnxTI, ScanOutxTO => CoreScanOutxT(4), InWrEnxSI => CoreInWrEnxS(4), OutWrEnxSO => CoreOutWrEnxS(4), DxDO => CoreOutxD(4), FinBlockxSI => CoreFinBlockxS(4), PenUltCyclexSO => CorePenUltCyclexS(4), DxDI => Core4InxD, RstxRBI => RstxRBI); ------------------------------------------------------------------------------- -- ethz_skein - IntAlgSelxS == 5 i_ethz_skein : ethz_skein port map (ClkxCI => CoreClkxC(5), ScanInxTI => CoreScanInxT(5), ScanEnxTI => CoreScanEnxTI, ScanOutxTO => CoreScanOutxT(5), InWrEnxSI => CoreInWrEnxS(5), OutWrEnxSO => CoreOutWrEnxS(5), HashxDO => CoreOutxD(5), FinBlockxSI => CoreFinBlockxS(5), PenUltCyclexSO => CorePenUltCyclexS(5), BlockxDI => Core5InxD, MsgLenxDI => CoreMsgLenxD(5), RstxRBI => RstxRBI); ------------------------------------------------------------------------------- -- RAM1: - IntAlgSelxS == 6 i_RAM1 : SYKA65_2048X32X1CM8 port map ( DO => RAM1OutxD, A => CoreMsgLenxD(6)(10 downto 0), DI => RAM1InxD, WEB => MemWrEnxSBI, DVSE => ZeroxD, -- disable DVS DVS => DVSxD, -- All zeroes CK => CoreClkxC(6), CSB => ZeroxD); -- chip select active low -- RAM input is random (taken from LFSR) when OutSelxSI(3) is zero -- or it is the address when OutSelxSI(3) is one -- Since the output is copied to 256 bits, the OutSelxSI has no -- effect on the RAM RAM1InxD <= Core6InxD when OutSelxSI(3) = '0' else CoreMsgLenxD(6)(31 downto 0); -- RAM Output is copied to 256 bits CoreOutxD(6)(31 downto 0) <= RAM1OutxD; CoreOutxD(6)(63 downto 32) <= RAM1OutxD; CoreOutxD(6)(95 downto 64) <= RAM1OutxD; CoreOutxD(6)(127 downto 96) <= RAM1OutxD; CoreOutxD(6)(159 downto 128) <= RAM1OutxD; CoreOutxD(6)(191 downto 160) <= RAM1OutxD; CoreOutxD(6)(223 downto 192) <= RAM1OutxD; CoreOutxD(6)(255 downto 224) <= RAM1OutxD; CorePenUltCyclexS(6) <= '1'; CoreOutWrEnxS(6) <= '1'; ------------------------------------------------------------------------------- -- RAM2: - IntAlgSelxS == 7 i_RAM2 : SHKA65_2048X32X1CM4 port map ( DO => RAM2OutxD, A => CoreMsgLenxD(7)(10 downto 0), DI => RAM2InxD, WEB => MemWrEnxSBI, DVSE => ZeroxD, -- disable DVS DVS => DVSxD(2 downto 0), -- All zeroes CK => CoreClkxC(7), CSB => ZeroxD); -- chip select active low -- RAM input is random (taken from LFSR) when OutSelxSI(3) is zero -- or it is the address when OutSelxSI(3) is one -- Since the output is copied to 256 bits, the OutSelxSI has no -- effect on the RAM RAM2InxD <= Core7InxD when OutSelxSI(3) = '0' else CoreMsgLenxD(7)(31 downto 0); -- RAM Output is copied to 256 bits CoreOutxD(7)(31 downto 0) <= RAM2OutxD; CoreOutxD(7)(63 downto 32) <= RAM2OutxD; CoreOutxD(7)(95 downto 64) <= RAM2OutxD; CoreOutxD(7)(127 downto 96) <= RAM2OutxD; CoreOutxD(7)(159 downto 128) <= RAM2OutxD; CoreOutxD(7)(191 downto 160) <= RAM2OutxD; CoreOutxD(7)(223 downto 192) <= RAM2OutxD; CoreOutxD(7)(255 downto 224) <= RAM2OutxD; CorePenUltCyclexS(7) <= '1'; CoreOutWrEnxS(7) <= '1'; ------------------------------------------------------------------------------- -- gmu_sha2 - IntAlgSelxS == 8 i_gmu_sha2 : gmu_sha2_top port map (ClkxCI => CoreClkxC(8), ScanInxTI => CoreScanInxT(8), ScanEnxTI => CoreScanEnxTI, ScanOutxTO => CoreScanOutxT(8), InWrEnxSI => CoreInWrEnxS(8), OutWrEnxSO => CoreOutWrEnxS(8), DataxDO => CoreOutxD(8), FinBlockxSI => CoreFinBlockxS(8), PenUltCyclexSO => CorePenUltCyclexS(8), DataxDI => Core8InxD, RstxRBI => RstxRBI); ------------------------------------------------------------------------------- -- gmu_blake - IntAlgSelxS == 9 i_gmu_blake : gmu_blake_top port map (ClkxCI => CoreClkxC(9), ScanInxTI => CoreScanInxT(9), ScanEnxTI => CoreScanEnxTI, ScanOutxTO => CoreScanOutxT(9), InEnxSI => CoreInWrEnxS(9), OutEnxSO => CoreOutWrEnxS(9), DataxDO => CoreOutxD(9), FinBlockxSI => CoreFinBlockxS(9), PenUltCyclexSO => CorePenUltCyclexS(9), DataxDI => Core9InxD, MsgLenxDI => CoreMsgLenxD(9), RstxRBI => RstxRBI); ------------------------------------------------------------------------------- -- gmu_groestl - IntAlgSelxS == 10 i_gmu_groestl : gmu_groestl_top port map (ClkxCI => CoreClkxC(10), ScanInxTI => CoreScanInxT(10), ScanEnxTI => CoreScanEnxTI, ScanOutxTO => CoreScanOutxT(10), InEnxSI => CoreInWrEnxS(10), OutEnxSO => CoreOutWrEnxS(10), DataxDO => CoreOutxD(10), FinBlockxSI => CoreFinBlockxS(10), PenUltCyclexSO => CorePenUltCyclexS(10), DataxDI => Core10InxD, RstxRBI => RstxRBI); ------------------------------------------------------------------------------- -- gmu_jh - IntAlgSelxS == 11 i_gmu_jh : gmu_jh_top port map (ClkxCI => CoreClkxC(11), ScanInxTI => CoreScanInxT(11), ScanEnxTI => CoreScanEnxTI, ScanOutxTO => CoreScanOutxT(11), InEnxSI => CoreInWrEnxS(11), OutEnxSO => CoreOutWrEnxS(11), DataxDO => CoreOutxD(11), FinBlockxSI => CoreFinBlockxS(11), PenUltCyclexSO => CorePenUltCyclexS(11), DataxDI => Core11InxD, RstxRBI => RstxRBI); ------------------------------------------------------------------------------- -- gmu_keccak - IntAlgSelxS == 12 i_gmu_keccak : gmu_keccak_top port map (ClkxCI => CoreClkxC(12), ScanInxTI => CoreScanInxT(12), ScanEnxTI => CoreScanEnxTI, ScanOutxTO => CoreScanOutxT(12), InEnxSI => CoreInWrEnxS(12), OutEnxSO => CoreOutWrEnxS(12), DataxDO => CoreOutxD(12), FinBlockxSI => CoreFinBlockxS(12), PenUltCyclexSO => CorePenUltCyclexS(12), DataxDI => Core12InxD, RstxRBI => RstxRBI); ------------------------------------------------------------------------------- -- gmu_skein - IntAlgSelxS == 13 i_gmu_skein : gmu_skein_top port map (ClkxCI => CoreClkxC(13), ScanInxTI => CoreScanInxT(13), ScanEnxTI => CoreScanEnxTI, ScanOutxTO => CoreScanOutxT(13), InEnxSI => CoreInWrEnxS(13), OutEnxSO => CoreOutWrEnxS(13), DataxDO => CoreOutxD(13), FinBlockxSI => CoreFinBlockxS(13), PenUltCyclexSO => CorePenUltCyclexS(13), DataxDI => Core13InxD, MsgLenxDI => CoreMsgLenxD(13), RstxRBI => RstxRBI); ------------------------------------------------------------------------------- -- RAM3: - IntAlgSelxS == 14 i_RAM3 : SHKA65_16384X32X1CM16 port map ( DO => RAM3OutxD, A => CoreMsgLenxD(14)(13 downto 0), DI => RAM3InxD, WEB => MemWrEnxSBI, DVSE => ZeroxD, -- disable DVS DVS => DVSxD(2 downto 0), -- All zeroes CK => CoreClkxC(14), CSB => ZeroxD); -- chip select active low -- RAM input is random (taken from LFSR) when OutSelxSI(3) is zero -- or it is the address when OutSelxSI(3) is one -- Since the output is copied to 256 bits, the OutSelxSI has no -- effect on the RAM RAM3InxD <= Core14InxD when OutSelxSI(3) = '0' else CoreMsgLenxD(14)(31 downto 0); -- RAM Output is copied to 256 bits CoreOutxD(14)(31 downto 0) <= RAM3OutxD; CoreOutxD(14)(63 downto 32) <= RAM3OutxD; CoreOutxD(14)(95 downto 64) <= RAM3OutxD; CoreOutxD(14)(127 downto 96) <= RAM3OutxD; CoreOutxD(14)(159 downto 128) <= RAM3OutxD; CoreOutxD(14)(191 downto 160) <= RAM3OutxD; CoreOutxD(14)(223 downto 192) <= RAM3OutxD; CoreOutxD(14)(255 downto 224) <= RAM3OutxD; CorePenUltCyclexS(14) <= '1'; CoreOutWrEnxS(14) <= '1'; ------------------------------------------------------------------------------- -- Dummy - IntAlgSelxS == 15 -- This should copy all inpouts to its outputs, and still allow the -- input block to supply him with data CoreScanOutxT(15) <= CoreScanInxT(15); -- scan is through CoreOutWrEnxS(15) <= CoreInWrEnxS(15); -- Write enable is through CoreOutxD(15)(63 downto 0) <= Core15InxD; -- 64 bit CoreOutxD(15)(255 downto 64) <= (others => '0'); -- rest is zero CorePenUltCyclexS(15) <= '1'; -- always last cycle end rtl;