------------------------------------------------------------
-- Copyright: 2011 Integrated Sytems Laboratory, ETH Zurich
-- http://www.iis.ee.ethz.ch/~sha3
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Title : Shabziger constants
-- Project : Shabziger
-------------------------------------------------------------------------------
-- File : shabzigerpkg.vhd
-- Author : Frank K. Guerkaynak
-- Company : Integrated Systems Laboratory, ETH Zurich
-- Created : 2011-08-16
-- Last update: 2011-09-10
-- Platform : ModelSim (simulation), Synopsys (synthesis)
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Constants used in Shabziger
-------------------------------------------------------------------------------
-- Copyright (c) 2011 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-08-16 1.0 kgf Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package shabzigerpkg is
-- Number of rounds to assemble the input from LFSR
type numrounds is array (0 to 15) of integer range 0 to 16;
constant NUMROUND : numrounds := ( 7, -- ETHZ SHA2
7, -- ETHZ BLAKE
7, -- ETHZ GROESTL
7, -- ETHZ JH
16, -- ETHZ KECCAK
7, -- ETHZ SKEIN
0, -- RAM1 - SYKA65_2048X32X1CM8
0, -- RAM2 - SHKA65_2048X32X1CM4
7, -- GMU SHA2
7, -- GMU BLAKE
7, -- GMU GROESTL
7, -- GMU JH
16, -- GMU KECCAK
7, -- GMU SKEIN
0, -- RAM3 - SHKA65_16384X32X1CM16
0); -- DUMMY
-- Number of bits per normal round
type bits_per_rounds is array (0 to 15) of integer range 0 to 2047;
constant BITSPERROUND : bits_per_rounds :=
( 512, -- ETHZ SHA2
512, -- ETHZ BLAKE
1, -- ETHZ GROESTL
512, -- ETHZ JH
1088, -- ETHZ KECCAK
64, -- ETHZ SKEIN
1, -- RAM1 - SYKA65_2048X32X1CM8
1, -- RAM2 - SHKA65_2048X32X1CM4
512, -- GMU SHA2
512, -- GMU BLAKE
1, -- GMU GROESTL
512, -- GMU JH
1088, -- GMU KECCAK
64, -- GMU SKEIN
1, -- RAM3 - SHKA65_16384X32X1CM16
32); -- DUMMY
-- Number of bits per last round minus the padding
type bits_last_rounds is array (0 to 15) of integer range 0 to 2047;
constant BITSLASTROUND : bits_per_rounds :=
( 432, -- ETHZ SHA2
432, -- ETHZ BLAKE (*)
1, -- ETHZ GROESTL (*)
0, -- ETHZ JH
1072, -- ETHZ KECCAK (*)
64, -- ETHZ SKEIN
64, -- RAM1 - SYKA65_2048X32X1CM8
64, -- RAM2 - SHKA65_2048X32X1CM4
432, -- GMU SHA2
432, -- GMU BLAKE
1, -- GMU GROESTL (*)
0, -- GMU JH
1072, -- GMU KECCAK
64, -- GMU SKEIN
1, -- RAM3 - SHKA65_16384X32X1CM16
32); -- DUMMY
-- AlgSelxSI constants
constant ETHZSHA2 : std_logic_vector(3 downto 0) := "0000";
constant ETHZBLAKE : std_logic_vector(3 downto 0) := "0001";
constant ETHZGROESTL : std_logic_vector(3 downto 0) := "0010";
constant ETHZJH : std_logic_vector(3 downto 0) := "0011";
constant ETHZKECCAK : std_logic_vector(3 downto 0) := "0100";
constant ETHZSKEIN : std_logic_vector(3 downto 0) := "0101";
constant RAM1 : std_logic_vector(3 downto 0) := "0110";
constant RAM2 : std_logic_vector(3 downto 0) := "0111";
constant GMUSHA2 : std_logic_vector(3 downto 0) := "1000";
constant GMUBLAKE : std_logic_vector(3 downto 0) := "1001";
constant GMUGROESTL : std_logic_vector(3 downto 0) := "1010";
constant GMUJH : std_logic_vector(3 downto 0) := "1011";
constant GMUKECCAK : std_logic_vector(3 downto 0) := "1100";
constant GMUSKEIN : std_logic_vector(3 downto 0) := "1101";
constant RAM3 : std_logic_vector(3 downto 0) := "1110";
constant DUMMYALG : std_logic_vector(3 downto 0) := "1111";
-- 3 bit select signals AlgSelxSI(2 downto 0) for algorithms
constant SHA2 : std_logic_vector(2 downto 0) := "000";
constant BLAKE : std_logic_vector(2 downto 0) := "001";
constant GROESTL : std_logic_vector(2 downto 0) := "010";
constant JH : std_logic_vector(2 downto 0) := "011";
constant KECCAK : std_logic_vector(2 downto 0) := "100";
constant SKEIN : std_logic_vector(2 downto 0) := "101";
constant DUMMY : std_logic_vector(2 downto 0) := "111";
-- Length of the LFSR -1
constant LFSRLEN : integer := 72;
-------------------------------------------------------------------------------
-- Component definitions for all cores
-------------------------------------------------------------------------------
--foreach d (ethz_blake ethz_groestl ethz_jh ethz_keccak ethz_sha2 ethz_skein \
-- gmu_blake gmu_groestl gmu_jh gmu_keccak gmu_sha2 gmu_skein \
-- )
--
--echo "-- $d"
--cd $d
--
--perl -ne 'print if (/^\s*component/../^\s*end/)' sourcecode/${d}_tb.vhd
--cd ..
--end
--
-- This is scripts/all_entities.csh
--
-------------------------------------------------------------------------------
-- ethz_blake
component ethz_blake
port (
CLKxCI : in std_logic;
RstxRBI : in std_logic;
ScanInxTI : in std_logic;
ScanOutxTO : out std_logic;
ScanEnxTI : in std_logic;
MxDI : in std_logic_vector(511 downto 0);
SxDI : in std_logic_vector(127 downto 0);
MsgLenxDI : in std_logic_vector( 63 downto 0);
HxDO : out std_logic_vector(255 downto 0);
FinBlockxSI : in std_logic;
PenUltCyclexSO : out std_logic;
InWrEnxSI : in std_logic;
OutWrEnxSO : out std_logic);
end component;
-------------------------------------------------------------------------------
-- ethz_groestl
component ethz_groestl
port (
ClkxCI : in std_logic;
RstxRBI : in std_logic;
ScanInxTI : in std_logic;
ScanOutxTO : out std_logic;
ScanEnxTI : in std_logic;
InWrEnxSI : in std_logic;
FinBlockxSI : in std_logic;
OutWrEnxSO : out std_logic;
PenUltCyclexSO : out std_logic;
MsgInxDI : in std_logic_vector(511 downto 0);
HashOutxDO : out std_logic_vector(255 downto 0));
end component;
-------------------------------------------------------------------------------
-- ethz_jh
component ethz_jh
port (
ClkxCI : in std_logic;
RstxRBI : in std_logic;
ScanInxTI : in std_logic;
ScanOutxTO : out std_logic;
ScanEnxTI : in std_logic;
InWrEnxSI : in std_logic;
OutWrEnxSO : out std_logic;
PenUltCyclexSO : out std_logic;
FinBlockxSI : in std_logic;
MsgInxDI : in std_logic_vector(511 downto 0);
HashOutxDO : out std_logic_vector(255 downto 0));
end component;
-------------------------------------------------------------------------------
-- ethz_keccak
component ethz_keccak
port (
ClkxCI : in std_logic;
RstxRBI : in std_logic;
ScanInxTI : in std_logic;
ScanOutxTO : out std_logic;
ScanEnxTI : in std_logic;
FinBlockxSI : in std_logic;
InWrEnxSI : in std_logic;
OutWrEnxSO : out std_logic;
PenUltCyclexSO : out std_logic;
DxDI : in std_logic_vector(1087 downto 0);
DxDO : out std_logic_vector(255 downto 0));
end component;
-------------------------------------------------------------------------------
-- ethz_sha2
component ethz_sha2
port (
ClkxCI : in std_logic;
RstxRBI : in std_logic;
FinBlockxSI : in std_logic;
InWrEnxSI : in std_logic;
PenUltCyclexSO : out std_logic;
OutWrEnxSO : out std_logic;
TextInxDI : in std_logic_vector(511 downto 0);
HOutxDO : out std_logic_vector(255 downto 0);
ScanInxTI : in std_logic;
ScanEnxTI : in std_logic;
ScanOutxTO : out std_logic);
end component;
-------------------------------------------------------------------------------
-- ethz_skein
component ethz_skein
port (
ClkxCI : in std_logic;
RstxRBI : in std_logic;
FinBlockxSI : in std_logic;
InWrEnxSI : in std_logic;
OutWrEnxSO : out std_logic;
PenUltCyclexSO : out std_logic;
BlockxDI : in std_logic_vector(511 downto 0);
MsgLenxDI : in std_logic_vector(63 downto 0);
HashxDO : out std_logic_vector(255 downto 0);
ScanInxTI : in std_logic;
ScanEnxTI : in std_logic;
ScanOutxTO : out std_logic);
end component;
-------------------------------------------------------------------------------
-- gmu_blake
component gmu_blake_top
port (
ClkxCI : in std_logic;
RstxRBI : in std_logic;
ScanInxTI : in std_logic;
ScanOutxTO : out std_logic;
ScanEnxTI : in std_logic;
InEnxSI : in std_logic;
FinBlockxSI : in std_logic;
DataxDI : in std_logic_vector(511 downto 0);
MsgLenxDI : in std_logic_vector(63 downto 0);
OutEnxSO : out std_logic;
PenUltCyclexSO : out std_logic;
DataxDO : out std_logic_vector(255 downto 0));
end component;
-------------------------------------------------------------------------------
-- gmu_groestl
component gmu_groestl_top
port (
ClkxCI : in std_logic;
RstxRBI : in std_logic;
ScanInxTI : in std_logic;
ScanOutxTO : out std_logic;
ScanEnxTI : in std_logic;
InEnxSI : in std_logic;
FinBlockxSI : in std_logic;
DataxDI : in std_logic_vector(511 downto 0);
OutEnxSO : out std_logic;
PenUltCyclexSO : out std_logic;
DataxDO : out std_logic_vector(255 downto 0));
end component;
-------------------------------------------------------------------------------
-- gmu_jh
component gmu_jh_top
port (
ClkxCI : in std_logic;
RstxRBI : in std_logic;
ScanInxTI : in std_logic;
ScanOutxTO : out std_logic;
ScanEnxTI : in std_logic;
InEnxSI : in std_logic;
FinBlockxSI : in std_logic;
DataxDI : in std_logic_vector(511 downto 0);
OutEnxSO : out std_logic;
PenUltCyclexSO : out std_logic;
DataxDO : out std_logic_vector(255 downto 0));
end component;
-------------------------------------------------------------------------------
-- gmu_keccak
component gmu_keccak_top
port (
ClkxCI : in std_logic;
RstxRBI : in std_logic;
ScanInxTI : in std_logic;
ScanOutxTO : out std_logic;
ScanEnxTI : in std_logic;
InEnxSI : in std_logic;
FinBlockxSI : in std_logic;
DataxDI : in std_logic_vector(1087 downto 0);
OutEnxSO : out std_logic;
PenUltCyclexSO : out std_logic;
DataxDO : out std_logic_vector(255 downto 0));
end component;
-------------------------------------------------------------------------------
-- gmu_sha2
component gmu_sha2_top
port (
ClkxCI : in std_logic;
RstxRBI : in std_logic;
InWrEnxSI : in std_logic;
FinBlockxSI : in std_logic;
DataxDI : in std_logic_vector(511 downto 0);
ScanInxTI : in std_logic;
ScanEnxTI : in std_logic;
ScanOutxTO : out std_logic;
OutWrEnxSO : out std_logic;
PenUltCyclexSO : out std_logic;
DataxDO : out std_logic_vector(255 downto 0));
end component;
-------------------------------------------------------------------------------
-- gmu_skein
component gmu_skein_top
port (
ClkxCI : in std_logic;
RstxRBI : in std_logic;
ScanInxTI : in std_logic;
ScanOutxTO : out std_logic;
ScanEnxTI : in std_logic;
InEnxSI : in std_logic;
FinBlockxSI : in std_logic;
DataxDI : in std_logic_vector(511 downto 0);
MsgLenxDI : in std_logic_vector(63 downto 0);
OutEnxSO : out std_logic;
PenUltCyclexSO : out std_logic;
DataxDO : out std_logic_vector(255 downto 0));
end component;
-------------------------------------------------------------------------------
-- RAM Components
-------------------------------------------------------------------------------
-- component SHKA65_16384X32X1CM16 -- RAM3
component SHKA65_16384X32X1CM16
port(
DO : OUT std_logic_vector (31 downto 0);
A : IN std_logic_vector (13 downto 0);
DI : IN std_logic_vector (31 downto 0);
WEB : IN std_logic;
DVSE : IN std_logic;
DVS : IN std_logic_vector (2 downto 0);
CK : IN std_logic;
CSB : IN std_logic );
end component;
-- component SHKA65_2048X32X1CM4 -- RAM2
component SHKA65_2048X32X1CM4
port(
DO : OUT std_logic_vector (31 downto 0);
A : IN std_logic_vector (10 downto 0);
DI : IN std_logic_vector (31 downto 0);
WEB : IN std_logic;
DVSE : IN std_logic;
DVS : IN std_logic_vector (2 downto 0);
CK : IN std_logic;
CSB : IN std_logic );
end component;
-- component SYKA65_2048X32X1CM8 -- RAM1
component SYKA65_2048X32X1CM8
port(
DO : OUT std_logic_vector (31 downto 0);
A : IN std_logic_vector (10 downto 0);
DI : IN std_logic_vector (31 downto 0);
WEB : IN std_logic;
DVSE : IN std_logic;
DVS : IN std_logic_vector (3 downto 0);
CK : IN std_logic;
CSB : IN std_logic );
end component;
end shabzigerpkg;