############################################################
## Copyright: 2011 Integrated Sytems Laboratory, ETH Zurich
##            http://www.iis.ee.ethz.ch/~sha3
############################################################


#the two gate instantiations
read_verilog -netlist ../sourcecode/sha_xor.v

# the name of the lib could change 
remove_attribute [get_lib_cells uk65lscllmvbbr_108c125_wc/LAGCEM2R] dont_use
read_verilog -netlist ../sourcecode/clockgate.v

# let us start reading in the files
read_verilog -netlist ../../ethz_sha2/synopsys/netlists/ethz_sha2.v
read_verilog -netlist ../../ethz_blake/synopsys/netlists/ethz_blake.v
read_verilog -netlist ../../ethz_groestl/synopsys/netlists/ethz_groestl.v
read_verilog -netlist ../../ethz_jh/synopsys/netlists/ethz_jh.v
read_verilog -netlist ../../ethz_keccak/synopsys/netlists/ethz_keccak.v
read_verilog -netlist ../../ethz_skein/synopsys/netlists/ethz_skein.v

read_verilog -netlist ../../gmu_sha2/synopsys/netlists/gmu_sha2.v
read_verilog -netlist ../../gmu_blake/synopsys/netlists/gmu_blake.v
read_verilog -netlist ../../gmu_groestl/synopsys/netlists/gmu_groestl.v
read_verilog -netlist ../../gmu_jh/synopsys/netlists/gmu_jh.v
read_verilog -netlist ../../gmu_keccak/synopsys/netlists/gmu_keccak.v
read_verilog -netlist ../../gmu_skein/synopsys/netlists/gmu_skein.v

#now let us analyze the rest normally 
analyze -f vhdl { \
                    ../sourcecode/shabzigerpkg.vhd \
                    ../sourcecode/lfsr73.vhd \
                    ../sourcecode/padunit.vhd \
                    ../sourcecode/inputblock.vhd \
                    ../sourcecode/shabziger.vhd \
                  }
elaborate shabziger
current_design shabziger


# make sure we do not modify them at the moment 
set_dont_touch [find design clockgate]
set_dont_touch [find design sha_xor]
set_dont_touch [find design ethz_*]
set_dont_touch [find design gmu_*_top]

# we will read the shabziger_chip at the very end