############################################################
## Copyright: 2011 Integrated Sytems Laboratory, ETH Zurich
## http://www.iis.ee.ethz.ch/~sha3
############################################################
# v0.1 - - Tue Sep 6 18:13:49 CEST 2011
# - script to compilethe shabziger
# copied from v0.3 sha3_syn.tcl
# -- clean start
remove_design -design
sh rm -rf WORK/*
# ---------------------------------------------------------------------------------------
set NumberThreads [exec cat /proc/cpuinfo | grep -c processor]
# there is not much improvement with this at the moment
#set_host_options -max_cores $NumberThreads
# ---------------------------------------------------------------------------------------
# Default Setings
# ---------------------------------------------------------------------------------------
set CLOCK 3.5
set IN 0
set OUT 0
set PAD_IN 0.5
set PAD_OUT 1.5
set CLK_TREE 1
set LIB u065gioll25mvir_25_wc
set DRIV_CELL IUMB
set DRIV_PIN DI
set LOAD_CELL IUMB
set LOAD_PIN DO
# -- sets for every case a list
set libraryset("wc") [list uk65lscllmvbbr_108c125_wc.db uk65lscllmvbbl_108c125_wc.db uk65lscllmvbbh_108c125_wc.db u065gioll25mvir_25_wc.db]
set libraryset("tc") [list uk65lscllmvbbr_120c25_tc.db uk65lscllmvbbl_120c25_tc.db uk65lscllmvbbh_120c25_tc.db u065gioll25mvir_25_tc.db]
set libraryset("bc") [list uk65lscllmvbbr_132c0_bc.db uk65lscllmvbbl_132c0_bc.db uk65lscllmvbbh_132c0_bc.db u065gioll25mvir_25_bc.db]
# -- driver library the same way
set driverlibrary("wc") uk65lscllmvbbr_108c125_wc
set driverlibrary("tc") uk65lscllmvbbr_120c25_tc
set driverlibrary("bc") uk65lscllmvbbr_132c0_bc
# these are always typical case.. but it is ok..
set ramset [list SHKA65_16384X32X1CM16_TC.db SHKA65_2048X32X1CM4_TC.db SYKA65_2048X32X1CM8_TC.db]
# -- Overwrites the target_library set by .synopsys_dc.setup withe the Worst Case lib
set corner wc
set target_library $libraryset("$corner")
set link_library [concat [list "*"] $libraryset("$corner") $ramset]
set reportname shabziger_${CLOCK}_${corner}
# high fanout threshold, we have 1088 bit wide things
set high_fanout_net_threshold 1200
# auto recognize clock gate cells in the netlist
set power_cg_auto_identify true
# -- Load the design
source scripts/assemble.tcl
# ---------------------------------------------------------------------------------------
# Compile first the inputblock with stricter timing constraints
# ---------------------------------------------------------------------------------------
current_design inputblock
# strict constraints
create_clock ClkxCI -period 2.0
set_input_delay 0 -clock ClkxCI [all_inputs]
set_output_delay 1.75 -clock ClkxCI [all_outputs]
set_driving_cell -no_design_rule -library $driverlibrary("$corner") -lib_cell BUFM4R -pin Z [all_inputs]
set_load [expr 8 *[load_of $driverlibrary("$corner")/BUFM4R/A]] [all_outputs]
# do not merge registers in input_block, they are there for a reason
set_register_merging [all_registers] false
# this should have been enough actually but...
set compile_enable_register_merging false
# now compile the inputblock
compile_ultra -scan
# ---------------------------------------------------------------------------------------
# set up timing constraints
# ---------------------------------------------------------------------------------------
# -- pessimistic wire load model
#set_wire_load_mode top
# if there is a script to add the wireload, do it here
if {[file exists ./scripts/wireload.tcl]} {
puts "*INFO: wireload.tcl exists and will be executed"
source ./scripts/wireload.tcl
}
current_design shabziger
# create the main Clock
create_clock ClkxCI -period $CLOCK
# clocked inputs have the input delay minus the clock tree
set_input_delay [expr $IN + $CLK_TREE] -clock ClkxCI [all_inputs]
# These are the outputs that go to next stage
set_output_delay [expr $OUT + $PAD_OUT - $CLK_TREE] -clock ClkxCI [all_outputs]
# All inputs are the pads
set_driving_cell -no_design_rule -library ${LIB} -lib_cell ${DRIV_CELL} -pin ${DRIV_PIN} \
[remove_from_collection [all_inputs] ClkxCI]
# all Outputs have the equivalent load of an output pad
set_load [load_of ${LIB}/${LOAD_CELL}/${LOAD_PIN}] [all_outputs]
### IMPORTANT
### The XOR'ed clock input is 0 for synthesis
set_case_analysis 0 ClkDxCI
## Set false paths
set_false_path -from [get_ports {CoreScanEnxTI}]
set_false_path -from [get_ports {FuncScanEnxTI}]
set_false_path -from [get_ports {RstxRBI}]
set_false_path -from [get_ports {OutSelxSI*}]
## Constants for teh pad drive
set_case_analysis 1 [get_ports {PadOutEnxSI}]
set_case_analysis 1 [get_ports {PadDrive1xSI}]
set_case_analysis 0 [get_ports {PadDrive2xSI}]
## ungroup inputblock so that the dffs can be better distributed
ungroup [get_cells *input*]
## make sure that the FinBlockxSP is not optimized
set compile_delete_unloaded_sequential_cells false
## write the last version before the compile
write -f ddc -h -o DDC/${reportname}_precomp.ddc
# ---------------------------------------------------------------------------------------
# compilation
# ---------------------------------------------------------------------------------------
# note at this point the cores are don't touched
# write out check
check_design -multiple_designs > reports/${reportname}_check_before_compile.rep
report_design > reports/${reportname}_report_before_compile.rep
# compile
compile_ultra -scan
write -f ddc -h -o DDC/${reportname}_compile.ddc
# ---------------------------------------------------------------------------------------
# Insert DFT
# ---------------------------------------------------------------------------------------
reset_dft_configuration
set_dft_insertion_configuration -synthesis_optimization none
set test_disable_enhanced_dft_drc_report FALSE
set_scan_configuration -style multiplexed_flip_flop
set_dft_signal -view existing -type Constant -port ClkDxCI -active_state 0
set_dft_signal -view existing -type ScanClock -port ClkxCI -timing {45 55}
set_dft_signal -view existing -type Reset -port RstxRBI -active_state 0
set_dft_signal -view spec -type ScanEnable -port CoreScanEnxTI -active_state 1
## There are two additional scan chains which are connected directly
##
##
## CoreScanInxTI -> OutWrEnxSO (controlled by CoreScanEnxTI)
## - selected by AlgSelxSI connects the scan chain of the core
##
# -- create 1 chain
set_scan_configuration -chain_count 1
# -- define scan chains
set_dft_signal -view spec -type ScanDataIn -port FinBlockxSI
set_dft_signal -view spec -type ScanDataOut -port PenUltCyclexSO
## FuncScanInxTI -> InWrEnxSO (controlled by FuncScanEnxTI)
## - goes through the LFSR, the input register and then the output register
## set_dft_signal -view spec -type ScanDataIn -port FuncScanInxTI
## set_dft_signal -view spec -type ScanDataOut -port InWrEnxSO
## set_dft_signal -view spec -type ScanEnable -port FuncScanEnxTI -active_state 1
## disable scan on the elements that are part of the functional
## scan path
set_scan_element false [find cell OutRegxDP_reg*]
set_scan_element false [find cell i_inputblock/DataxDP_reg*]
set_scan_element false [find cell i_inputblock/i_lfsr/DataxDP_reg*]
## these guys are actually identical to the DataxDP, the Functional
## scan will also update these simultaneously. This is not a problem
## as all outputs go to independent cores
set_scan_element false [find cell i_inputblock/Data*xDP_reg*]
create_test_protocol
# write out report
dft_drc -verbose > reports/${reportname}_scanchain.rep
report_dft_signal >> reports/${reportname}_scanchain.rep
# -- insert scan chains - only 77 FFs here
insert_dft
# write out report
report_scan_path >> reports/${reportname}_scanchain.rep
dft_drc -coverage_estimate >> reports/${reportname}_scanchain.rep
# let us also balance the buffer trees
report_net_fanout -hi > reports/${reportname}_fanout.rep
foreach SIG {RstxRBI CoreScanEnxTI FuncScanEnxTI} {
clean_buffer_tree -from ${SIG}
balance_buffer -from ${SIG} -prefer BUFM16R -library $driverlibrary("$corner")
report_buffer_tree -from ${SIG} >> reports/${reportname}_fanout.rep
}
# need if "set_dft_insertion_configuration -synthesis_optimization none" is set,
# so "insert_dft" is not doing a additional compile. Should be faster.
compile_ultra -incremental
write -f ddc -h -o DDC/${reportname}_final.ddc
# ---------------------------------------------------------------------------------------
# generate reports
# ---------------------------------------------------------------------------------------
# display some useful report
# report_timing
# report_area -hierarchy
# write out report
report_area -hierarchy -nosplit > reports/${reportname}_area.rpt
report_net_fanout -hi > reports/${reportname}_fanout.rpt
# echo "IN2REG TIMING" > ./reports/${reportname}_timing.rep
# report_timing -from [all_inputs] -to [all_registers -data_pins] >> ./reports/${reportname}_timing.rep
# echo "REG2REG TIMING" >> ./reports/${reportname}_timing.rep
# report_timing -from [all_registers -clock_pins] -to [all_registers -data_pins] >> ./reports/${reportname}_timing.rep
# echo "REG2OUT TIMING" >> ./reports/${reportname}_timing.rep
# report_timing -from [all_registers -clock_pins] -to [all_outputs] >> ./reports/${reportname}_timing.rep
# echo "IN2OUT TIMING" >> ./reports/${reportname}_timing.rep
# report_timing -from [all_inputs] -to [all_outputs] >> ./reports/${reportname}_timing.rep
}
# ---------------------------------------------------------------------------------------
# Write out data (verilog netlist and DDC file)
# ---------------------------------------------------------------------------------------
# clock gates are not uniquified ?? don't know why..
uniquify -cell [get_cells *clock*]
# now the top
read_verilog -netlist ../sourcecode/shabziger_chip.v
current_design shabziger_chip
write -f ddc -h -o DDC/${reportname}_chip.ddc
define_name_rules verilog -add_dummy_nets
change_names -h -rules verilog
write -h -f verilog -o netlists/shabziger_chip.v
# now it is time to bow out
exit