############################################################
## Copyright: 2011 Integrated Sytems Laboratory, ETH Zurich
##            http://www.iis.ee.ethz.ch/~sha3
############################################################
#
# ---------------------------------------------------------------------------------------
# Default Setings
# ---------------------------------------------------------------------------------------
set CLOCK 3.5 
set IN  0
set OUT 0

set PAD_IN   0.5
set PAD_OUT  1.5
set CLK_TREE 1

set LIB       u065gioll25mvir_25_wc
set DRIV_CELL IUMB
set DRIV_PIN  DI
set LOAD_CELL IUMB
set LOAD_PIN  DO

# -- sets for every case a list
set libraryset("wc") [list uk65lscllmvbbr_108c125_wc.db uk65lscllmvbbl_108c125_wc.db uk65lscllmvbbh_108c125_wc.db u065gioll25mvir_25_wc.db]
set libraryset("tc") [list uk65lscllmvbbr_120c25_tc.db uk65lscllmvbbl_120c25_tc.db uk65lscllmvbbh_120c25_tc.db u065gioll25mvir_25_tc.db]
set libraryset("bc") [list uk65lscllmvbbr_132c0_bc.db uk65lscllmvbbl_132c0_bc.db uk65lscllmvbbh_132c0_bc.db u065gioll25mvir_25_bc.db]

# -- driver library the same way
set driverlibrary("wc") uk65lscllmvbbr_108c125_wc
set driverlibrary("tc") uk65lscllmvbbr_120c25_tc
set driverlibrary("bc") uk65lscllmvbbr_132c0_bc

# these are always typical case.. but it is ok..
set ramset [list SHKA65_16384X32X1CM16_TC.db SHKA65_2048X32X1CM4_TC.db SYKA65_2048X32X1CM8_TC.db]

# -- Overwrites the target_library set by .synopsys_dc.setup  withe the Worst Case lib
set corner         wc


set target_library $libraryset("$corner")
set link_library   [concat [list "*"] $libraryset("$corner") $ramset] 
set reportname shabziger_${CLOCK}_${corner}

# high fanout threshold, we have 1088 bit wide things
set high_fanout_net_threshold 1200

# auto recognize clock gate cells in the netlist
set power_cg_auto_identify true

# read in the wireload library
read_lib ../../shabziger/synopsys/encounter_wireload.lib

set_wire_load_mode enclosed