############################################################ ## Copyright: 2011 Integrated Sytems Laboratory, ETH Zurich ## http://www.iis.ee.ethz.ch/~sha3 ############################################################ ## set the wireload model from encounter ## this could be much better ## read in the wireload library read_lib ../../shabziger/synopsys/encounter_wireload.lib set_wire_load_mode enclosed #egrep -h "^(current_design|set_wire_load_model)" */synopsys/scripts/wireload.tcl | less #------------------------------------------------------------------------- #current_design roundreg #set_wire_load_model -library shabziger_chip_flat -name roundreg_test_1.top.i_ethz_blake.i_blake_u_roundreg_flat current_design ethz_blake set_wire_load_model -library shabziger_chip_flat -name ethz_blake.top.i_ethz_blake_flat #------------------------------------------------------------------------- current_design ethz_groestl set_wire_load_model -library shabziger_chip_flat -name ethz_groestl.top.i_ethz_groestl_flat #current_design groestl_p #set_wire_load_model -library shabziger_chip_flat -name groestl_p_test_1.top.i_ethz_groestl.i_p_flat #current_design groestl_q #set_wire_load_model -library shabziger_chip_flat -name groestl_q_test_3.top.i_ethz_groestl.i_q_flat #------------------------------------------------------------------------- current_design ethz_jh set_wire_load_model -library shabziger_chip_flat -name ethz_jh.top.i_ethz_jh_flat #------------------------------------------------------------------------- current_design ethz_keccak set_wire_load_model -library shabziger_chip_flat -name ethz_keccak.top.i_ethz_keccak_flat #------------------------------------------------------------------------- current_design ethz_sha2 set_wire_load_model -library shabziger_chip_flat -name ethz_sha2.top.i_ethz_sha2_flat #------------------------------------------------------------------------- current_design ethz_skein set_wire_load_model -library shabziger_chip_flat -name ethz_skein.top.i_ethz_skein_flat #------------------------------------------------------------------------- current_design gmu_blake_top set_wire_load_model -library shabziger_chip_flat -name gmu_blake_top.top.i_gmu_blake_flat #------------------------------------------------------------------------- current_design gmu_groestl_top set_wire_load_model -library shabziger_chip_flat -name gmu_groestl_top.top.i_gmu_groestl_flat #------------------------------------------------------------------------- current_design gmu_jh_top set_wire_load_model -library shabziger_chip_flat -name gmu_jh_top.top.i_gmu_jh_flat #------------------------------------------------------------------------- #current_design keccak_round #set_wire_load_model -library shabziger_chip_flat -name keccak_round.top.i_gmu_keccak.datapath_gen_rd_flat current_design gmu_keccak_top set_wire_load_model -library shabziger_chip_flat -name gmu_keccak_top.top.i_gmu_keccak_flat #------------------------------------------------------------------------- current_design gmu_sha2_top set_wire_load_model -library shabziger_chip_flat -name gmu_sha2_top.top.i_gmu_sha2_flat #------------------------------------------------------------------------- current_design gmu_skein_top set_wire_load_model -library shabziger_chip_flat -name gmu_skein_top.top.i_gmu_skein_flat #------------------------------------------------------------------------- # now the last one current_design shabziger set_wire_load_model -library shabziger_chip_flat -name shabziger.top_flat