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-- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
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library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use work.shavitepkg.all;

-- AES round without ARK, i.e. not using a key
entity aes is

  port (
    ClkxCI   : in  std_logic;
    RstxRBI  : in  std_logic;
    PlainxDI : in  wordmat128;
    OutxDO   : out wordmat128);
end aes;

architecture rtl of aes is

  -- Combinational S-Box
  component subbytes is
    port (
      ClkxCI  : in  std_logic;
      RstxRBI : in  std_logic;
      DxDI    : in  std_logic_vector(7 downto 0);
      DxDO    : out std_logic_vector(7 downto 0));
  end component;
  
  signal SBoxedxD, RowShiftedxD : bytemat128;
  signal Shift1xD, Mult3xD      : bytemat128;
  signal ColMixedxD             : bytemat128;
  
begin  -- rtl
  
  sboxi : for i in 3 downto 0 generate  -- SBox components
    sboxj : for j in 3 downto 0 generate
      sbox : subbytes
        port map (
          ClkxCI  => ClkxCI,
          RstxRBI => RstxRBI,
          DxDI    => PlainxDI(i)(8*j+7 downto 8*j),
          DxDO    => SBoxedxD(i*4+3-j));
    end generate sboxj;
  end generate sboxi;
  
  -- LUT-based S-Box, too big
  --  purpose: Calculates the S-Box of the input
  --  type   : combinational
  --  inputs : PlainxDI
  --  outputs: SBoxedxD
  --  p_sbox : process (PlainxDI)
  --  begin  -- process p_sbox
  --    for i in 3 downto 0 loop
  --      for j in 3 downto 0 loop
  --        SBoxedxD(i*4+3-j) PlainxDI(i)(8*j+7 downto 8*j))));
  --      end loop;  -- j
  --    end loop;  -- i          
  --  end process p_sbox;

  
  -- ShiftRows
  sr : for i in 3 downto 0 generate
    srword : for j in 3 downto 0 generate
      RowShiftedxD(i*4+j) <= SBoxedxD(((i+j) mod 4)*4+j);
    end generate srword;
  end generate sr;

  -- purpose: Calculates a bit-shifted signal needed for MixColumns
  -- type   : combinational
  -- inputs : RowShiftedxD
  -- outputs: Shift1xD
  p_bitshift : process (RowShiftedxD)
  begin  -- process p_bitshift
    for i in 0 to 15 loop
      if RowShiftedxD(i)(7) = '1' then
        Shift1xD(i) <= (RowShiftedxD(i)(6 downto 0) & '0') xor X"1b";
      else
        Shift1xD(i) <= RowShiftedxD(i)(6 downto 0) & '0';
      end if;
    end loop;
  end process p_bitshift;

  -- Calculate the Mult3xD auxiliary signal for MixColumns
  mult3 : for i in 0 to 15 generate
    Mult3xD(i) <= Shift1xD(i) xor RowShiftedxD(i);
  end generate mult3;

  -- MixColumns
  mc : for i in 0 to 3 generate
    ColMixedxD(4*i)   <= Shift1xD(4*i) xor Mult3xD(4*i+1) xor RowShiftedxD(4*i+2) xor RowShiftedxD(4*i+3);
    ColMixedxD(4*i+1) <= RowShiftedxD(4*i) xor Shift1xD(4*i+1) xor Mult3xD(4*i+2) xor RowShiftedxD(4*i+3);
    ColMixedxD(4*i+2) <= RowShiftedxD(4*i) xor RowShiftedxD(4*i+1) xor Shift1xD(4*i+2) xor Mult3xD(4*i+3);
    ColMixedxD(4*i+3) <= Mult3xD(4*i) xor RowShiftedxD(4*i+1) xor RowShiftedxD(4*i+2) xor Shift1xD(4*i+3);
  end generate mc;

  -- Output conversion
  -- purpose: Calculate the output word matrix
  -- type   : combinational
  -- inputs : ColMixedxD
  -- outputs: OutxDO
  p_outconv : process (ColMixedxD)
  begin  -- process p_outconv
    for i in 0 to 3 loop
      for j in 0 to 3 loop
        OutxDO(i)(8*j+7 downto 8*j) <= ColMixedxD(i*4+3-j);
      end loop;  -- j
    end loop;  -- i
  end process p_outconv;
  

end rtl;