------------------------------------------------------------ -- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich -- http://www.iis.ee.ethz.ch/~sha3 ------------------------------------------------------------ library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; use work.shavitepkg.all; entity f3 is port ( ClkxCI : in std_logic; RstxRBI : in std_logic; InputEnxEI : in std_logic; DataxDI : in wordmat128; SubKeyxDI : in wordmat128; OutxDO : out wordmat128); end f3; architecture rtl of f3 is component aes port ( ClkxCI : in std_logic; RstxRBI : in std_logic; PlainxDI : in wordmat128; OutxDO : out wordmat128); end component; signal AESInxD, AESOutxD : wordmat128; signal StatexDP, StatexDN : unsigned(1 downto 0); signal StateMatxDP, StateMatxDN : wordmat128; begin -- rtl u_aes : aes port map ( ClkxCI => ClkxCI, RstxRBI => RstxRBI, PlainxDI => AESInxD, OutxDO => AESOutxD); OutxDO <= StateMatxDN; fsm : for i in 3 downto 0 generate -- Use the data input every three cycles, otherwise work with the state register -- (This component has no idle state, so it is always ready for a message to arrive) AESInxD(i) <= DataxDI(i) xor SubKeyxDI(i) when to_integer(StatexDP) = 0 or InputEnxEI = '1' else StateMatxDP(i) xor SubkeyxDI(i); StateMatxDN(i) <= AESOutxD(i); end generate fsm; StatexDN <= "01" when InputEnxEI = '1' else (others => '0') when to_integer(StatexDP) = 2 else StatexDP + 1; p_mem : process (ClkxCI, RstxRBI) begin -- process p_mem if RstxRBI = '0' then -- asynchronous reset (active low) StatexDP <= (others => '0'); StateMatxDP <= (others => (others => '0')); elsif ClkxCI'event and ClkxCI = '1' then -- rising clock edge StatexDP <= StatexDN; StateMatxDP <= StateMatxDN; end if; end process p_mem; end rtl;