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-- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity subbytes is
  port (
    ClkxCI  : in  std_logic;
    RstxRBI : in  std_logic;
    DxDI    : in  std_logic_vector(7 downto 0);
    DxDO    : out std_logic_vector(7 downto 0));

end subbytes;

architecture rtl of subbytes is

  component gf4map_3
    port (
      AxDI  : in  std_logic_vector(7 downto 0);
      AhxDO : out std_logic_vector(3 downto 0);
      AlxDO : out std_logic_vector(3 downto 0));
  end component;

  component gf4sqr_3
    port (
      AxDI  : in  std_logic_vector(3 downto 0);
      A2xDO : out std_logic_vector(3 downto 0));
  end component;

  component gf4inv_3
    port (
      AxDI    : in  std_logic_vector(3 downto 0);
      AInvxDO : out std_logic_vector(3 downto 0));
  end component;

  component gf4mult_3
    port (
      AxDI : in  std_logic_vector(3 downto 0);
      BxDI : in  std_logic_vector(3 downto 0);
      CxDO : out std_logic_vector(3 downto 0));
  end component;
  
  component gf4imapaffine_3
    port (
      AhxDI : in  std_logic_vector(3 downto 0);
      AlxDI : in  std_logic_vector(3 downto 0);
      AxDO  : out std_logic_vector(7 downto 0));
  end component;

  signal AhxD, AlxD                   : std_logic_vector(3 downto 0);
  signal Ah2xD, Al2xD                 : std_logic_vector(3 downto 0);
  signal AmxD, ApxD                   : std_logic_vector(3 downto 0);
  signal AexD, Ael2pxD, AppxD, AinvxD : std_logic_vector(3 downto 0);
  signal AhsxD, AlsxD                 : std_logic_vector(3 downto 0);

begin  -- rtl

  u_gf4map: gf4map_3
    port map (
      AxDI  => DxDI,
      AhxDO => AhxD,
      AlxDO => AlxD);

  u_gf4sqr_h: gf4sqr_3
    port map (
      AxDI  => AhxD,
      A2xDO => Ah2xD);

  u_gf4sqr_l: gf4sqr_3
    port map (
      AxDI  => AlxD,
      A2xDO => Al2xD);

  u_gf4mult_e: gf4mult_3
    port map (
      AxDI => Ah2xD,
      BxDI => "1110",
      CxDO => AexD);

  u_gf4mult: gf4mult_3
    port map (
      AxDI => AlxD,
      BxDI => AhxD,
      CxDO => AmxD);

  ApxD    <= AlxD xor AhxD;
  Ael2pxD <= AexD xor Al2xD;
  AppxD   <= Ael2pxD xor AmxD;

  u_gf4inv: gf4inv_3
    port map (
      AxDI    => AppxD,
      AInvxDO => AinvxD);
  
  u_gf4mult_h: gf4mult_3
    port map (
      AxDI => AhxD,
      BxDI => AinvxD,
      CxDO => AhsxD);

  u_gf4mult_l: gf4mult_3
    port map (
      AxDI => AinvxD,
      BxDI => ApxD,
      CxDO => AlsxD);

  u_gf4imapaffine: gf4imapaffine_3
    port map (
      AhxDI => AhsxD,
      AlxDI => AlsxD,
      AxDO  => DxDO);
  
  
end rtl;