# we would need a 0.71ns clock for 20 Gbps..  is a target that we can reach
# at least for the preCTS
create_clock -period 2.72 [get_ports {ClkxCI}]
set_propagated_clock [get_ports {ClkxCI}]

#-----------------------------------------------------------------------------
# IO-Timing
#-----------------------------------------------------------------------------
#
# - If the input delay is not specified on an input port, it is assumed
#   to be zero (and NOT unconstrained!)
# - set_input_delay on clock ports will be ignored (-> warning)
# - Order is important if the same port is constrained more than
#   once, e.g. with global and then per-port settings (last setting
#   takes effect) 
#

# our drivers for the input
set_driving_cell -no_design_rule  -library fsd0a_a_generic_core_ss1p08v125c -lib_cell BUFX8 [remove_from_collection [all_inputs] ClkxCI]

## this should compensate for the clock insertion delay
set_input_delay  0.5 -clock {ClkxCI} [remove_from_collection [all_inputs] [get_ports {ClkxCI}]]
set_output_delay 0 -clock {ClkxCI} [all_outputs]



# 0.1ns input transition, 50fF output load

set_input_transition 0.1 [all_inputs]
set_load 0.05 [all_outputs]