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-- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;

entity controller is

  port (
    ClkxCI   : in  std_logic;
    RstxRBI  : in  std_logic;
    InEnxEI  : in  std_logic;
    FinxSI   : in  std_logic;
    IfMajxSO : out std_logic;
    IxDO     : out unsigned(5 downto 0);
    IPxDO    : out unsigned(5 downto 0);
    StartxSO : out std_logic;
    SavexSO : out std_logic;
    OutEnxEO : out std_logic);

end controller;

architecture rtl of controller is

  type state is (idle, fround, round, fin);
  signal StatexDP, StatexDN : state;

  signal IxDP, IxDN     : unsigned(5 downto 0);
  
begin  -- rtl

  IxDO <= IxDP;
  IfMajxSO <= IxDP(2);

  IPxDO <= IxDN when IxDN < 32 else (others => '0');

  p_fsm: process (INENxEI, IxDP, StatexDP)
  begin  -- process p_fsm

    StatexDN <= StatexDP;
    IxDN     <= (others => '0');
    OutEnxEO <= '0';
    StartxSO <= '0';
    SavexSO  <= '0';

    case StatexDP is
      -------------------------------------------------------------------------
      when idle =>
        
        if INENxEI = '1' then
          StatexDN <= fround;
          
        end if;

      -------------------------------------------------------------------------
      when fround =>

        if IxDP = 35 then
          StartxSO <= '1';
          SavexSO  <= '1';
          StatexDN <= round;

        else
          IxDN <= IxDP + 1;
          
        end if;
        
      -------------------------------------------------------------------------
      when round =>

        if IxDP = 35 then
          SavexSO  <= '1';
          
          if INENxEI = '0' then
            StatexDN <= fin;
          
          end if;

        else
          IxDN <= IxDP + 1;
          
        end if;

      -------------------------------------------------------------------------
      when fin =>

        if IxDP = 35 then
          OutEnxEO <= '1';
          StatexDN <= idle;

        else
          IxDN <= IxDP + 1;
          
        end if;
        
      -------------------------------------------------------------------------
      when others => StatexDN <= idle;
                     
    end case;
    
  end process p_fsm;

  p_mem : process (ClkxCI, RstxRBI)
  begin  -- process p_mem
    if RstxRBI = '0' then               -- asynchronous reset (active low)
      StatexDP <= idle;
      IxDP     <= (others => '0');
      
    elsif ClkxCI'event and ClkxCI = '1' then  -- rising clock edge
      StatexDP  <= StatexDN;
      IxDP   <= IxDN;
      
    end if;
  end process p_mem;

end rtl;