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-- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich
-- http://www.iis.ee.ethz.ch/~sha3
------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use work.simdpkg.all;
entity simd is
port (
ClkxCI : in std_logic;
RstxRBI : in std_logic;
InEnxEI : in std_logic;
FinxSI : in std_logic;
OutEnxEO : out std_logic;
DxDI : in std_logic_vector(511 downto 0);
DxDO : out std_logic_vector(255 downto 0));
end simd;
architecture rtl of simd is
component controller
port (
ClkxCI : in std_logic;
RstxRBI : in std_logic;
InEnxEI : in std_logic;
FinxSI : in std_logic;
IfMajxSO : out std_logic;
IxDO : out unsigned(5 downto 0);
IPxDO : out unsigned(5 downto 0);
StartxSO : out std_logic;
SavexSO : out std_logic;
OutEnxEO : out std_logic
);
end component;
component mexpansion
port (
ClkxCI : in std_logic;
RstxRBI : in std_logic;
InEnxEI : in std_logic;
FinxSI : in std_logic;
IxDI : in unsigned(5 downto 0);
IPxDI : in unsigned(5 downto 0);
MxDI : in marray;
MmemxDI : in marray;
WxDO : out simdline);
end component;
signal SxDP, SxDN, RoundOutxD, RoundOut2xD : simdstate;
signal PxD, SPermxD : simdline;
signal IfMajxS, StartxS, SavexS : std_logic;
signal RotInSxD, RotOutSxD, RotOutRxD : simdline;
signal IxD : unsigned(5 downto 0);
signal IPxD : unsigned(5 downto 0);
signal MinxD, MixD : marray;
signal WxD, WIVxD : simdline;
signal SrxD, RrxD : integer;
signal SIVxDP : simdstate;
signal MxDP : std_logic_vector(511 downto 0);
begin -- rtl
DxDO(255 downto 224) <= SxDN(0,0)(7 downto 0) & SxDN(0,0)(15 downto 8) & SxDN(0,0)(23 downto 16) & SxDN(0,0)(31 downto 24);
DxDO(223 downto 192) <= SxDN(1,0)(7 downto 0) & SxDN(1,0)(15 downto 8) & SxDN(1,0)(23 downto 16) & SxDN(1,0)(31 downto 24);
DxDO(191 downto 160) <= SxDN(2,0)(7 downto 0) & SxDN(2,0)(15 downto 8) & SxDN(2,0)(23 downto 16) & SxDN(2,0)(31 downto 24);
DxDO(159 downto 128) <= SxDN(3,0)(7 downto 0) & SxDN(3,0)(15 downto 8) & SxDN(3,0)(23 downto 16) & SxDN(3,0)(31 downto 24);
DxDO(127 downto 96) <= SxDN(0,1)(7 downto 0) & SxDN(0,1)(15 downto 8) & SxDN(0,1)(23 downto 16) & SxDN(0,1)(31 downto 24);
DxDO( 95 downto 64) <= SxDN(1,1)(7 downto 0) & SxDN(1,1)(15 downto 8) & SxDN(1,1)(23 downto 16) & SxDN(1,1)(31 downto 24);
DxDO( 63 downto 32) <= SxDN(2,1)(7 downto 0) & SxDN(2,1)(15 downto 8) & SxDN(2,1)(23 downto 16) & SxDN(2,1)(31 downto 24);
DxDO( 31 downto 0) <= SxDN(3,1)(7 downto 0) & SxDN(3,1)(15 downto 8) & SxDN(3,1)(23 downto 16) & SxDN(3,1)(31 downto 24);
-- Controller
-----------------------------------------------------------------------------
u_controller : controller
port map (
ClkxCI => ClkxCI,
RstxRBI => RstxRBI,
InEnxEI => InEnxEI,
FinxSI => FinxSI,
IfMajxSO => IfMajxS,
IxDO => IxD,
IPxDO => IPxD,
StartxSO => StartxS,
SavexSO => SavexS,
OutEnxEO => OutEnxEO);
-- Input Mux(s)
-----------------------------------------------------------------------------
RoundOut2xD <= IV when StartxS = '1' else RoundOutxD;
f_in2a : for i in 0 to 3 generate
f_in2b : for j in 0 to 3 generate
SxDN(j, i) <= RoundOut2xD(j, i) xor MxDP(128*(4-i)-j*32-1 downto 128*(4-i)-(j+1)*32) when SavexS = '1' else RoundOut2xD(j, i);
end generate f_in2b;
end generate f_in2a;
-- Message Expansion
-----------------------------------------------------------------------------
f_mess : for i in 0 to 15 generate
MinxD(i*4) <= MxDP((16-i)*32-24-1 downto (16-i)*32-32);
MinxD(i*4+1) <= MxDP((16-i)*32-16-1 downto (16-i)*32-24);
MinxD(i*4+2) <= MxDP((16-i)*32-8-1 downto (16-i)*32-16);
MinxD(i*4+3) <= MxDP((16-i)*32-1 downto (16-i)*32-8);
MixD(i*4) <= DxDI((16-i)*32-24-1 downto (16-i)*32-32);
MixD(i*4+1) <= DxDI((16-i)*32-16-1 downto (16-i)*32-24);
MixD(i*4+2) <= DxDI((16-i)*32-8-1 downto (16-i)*32-16);
MixD(i*4+3) <= DxDI((16-i)*32-1 downto (16-i)*32-8);
end generate f_mess;
u_mexpansion : mexpansion
port map (
ClkxCI => ClkxCI,
RstxRBI => RstxRBI,
InEnxEI => InEnxEI,
FinxSI => FinxSI,
IxDI => IxD,
IPxDI => IPxD,
MxDI => MixD,
MmemxDI => MinxD,
WxDO => WxD);
-- Step
-----------------------------------------------------------------------------
f_step: for i in 0 to 3 generate
PxD(i) <= (SxDP(i,0) and SxDP(i,1)) or (not(SxDP(i,0)) and SxDP(i,2)) when IfMajxS = '0' else
(SxDP(i,0) and (SxDP(i,1) or SxDP(i,2))) or (SxDP(i,1) and SxDP(i,2));
WIVxD(i) <= std_logic_vector(SIVxDP(i,to_integer(IxD)-32)) when IxD > 31 else WxD(i);
RotInSxD(i) <= std_logic_vector(unsigned(SxDP(i, 3)) + unsigned(WIVxD(i)) + unsigned(PxD(i)));
with SrxD select
RotOutSxD(i) <=
RotInSxD(i)(31-23 downto 0) & RotInSxD(i)(31 downto 32-23) when 23,
RotInSxD(i)(31-17 downto 0) & RotInSxD(i)(31 downto 32-17) when 17,
RotInSxD(i)(31-27 downto 0) & RotInSxD(i)(31 downto 32-27) when 27,
RotInSxD(i)(31- 3 downto 0) & RotInSxD(i)(31 downto 32- 3) when 3,
RotInSxD(i)(31-19 downto 0) & RotInSxD(i)(31 downto 32-19) when 19,
RotInSxD(i)(31-22 downto 0) & RotInSxD(i)(31 downto 32-22) when 22,
RotInSxD(i)(31- 7 downto 0) & RotInSxD(i)(31 downto 32- 7) when 7,
RotInSxD(i)(31-28 downto 0) & RotInSxD(i)(31 downto 32-28) when 28,
RotInSxD(i)(31- 9 downto 0) & RotInSxD(i)(31 downto 32- 9) when 9,
RotInSxD(i)(31-15 downto 0) & RotInSxD(i)(31 downto 32-15) when 15,
RotInSxD(i)(31- 5 downto 0) & RotInSxD(i)(31 downto 32- 5) when 5,
RotInSxD(i)(31-29 downto 0) & RotInSxD(i)(31 downto 32-29) when 29,
RotInSxD(i)(31-13 downto 0) & RotInSxD(i)(31 downto 32-13) when 13,
RotInSxD(i)(31-10 downto 0) & RotInSxD(i)(31 downto 32-10) when 10,
RotInSxD(i)(31-25 downto 0) & RotInSxD(i)(31 downto 32-25) when 25,
RotInSxD(i)(31- 4 downto 0) & RotInSxD(i)(31 downto 32- 4) when 4,
RotInSxD(i) when others;
with RrxD select
RotOutRxD(i) <=
SxDP(i,0)(31- 3 downto 0) & SxDP(i,0)(31 downto 32- 3) when 3,
SxDP(i,0)(31-23 downto 0) & SxDP(i,0)(31 downto 32-23) when 23,
SxDP(i,0)(31-17 downto 0) & SxDP(i,0)(31 downto 32-17) when 17,
SxDP(i,0)(31-27 downto 0) & SxDP(i,0)(31 downto 32-27) when 27,
SxDP(i,0)(31-28 downto 0) & SxDP(i,0)(31 downto 32-28) when 28,
SxDP(i,0)(31-19 downto 0) & SxDP(i,0)(31 downto 32-19) when 19,
SxDP(i,0)(31-22 downto 0) & SxDP(i,0)(31 downto 32-22) when 22,
SxDP(i,0)(31- 7 downto 0) & SxDP(i,0)(31 downto 32- 7) when 7,
SxDP(i,0)(31-29 downto 0) & SxDP(i,0)(31 downto 32-29) when 29,
SxDP(i,0)(31- 9 downto 0) & SxDP(i,0)(31 downto 32- 9) when 9,
SxDP(i,0)(31-15 downto 0) & SxDP(i,0)(31 downto 32-15) when 15,
SxDP(i,0)(31- 5 downto 0) & SxDP(i,0)(31 downto 32- 5) when 5,
SxDP(i,0)(31- 4 downto 0) & SxDP(i,0)(31 downto 32- 4) when 4,
SxDP(i,0)(31-13 downto 0) & SxDP(i,0)(31 downto 32-13) when 13,
SxDP(i,0)(31-10 downto 0) & SxDP(i,0)(31 downto 32-10) when 10,
SxDP(i,0)(31-25 downto 0) & SxDP(i,0)(31 downto 32-25) when 25,
SxDP(i,0) when others;
RoundOutxD(i,0) <= std_logic_vector(unsigned(RotOutSxD(i)) + unsigned(SPermxD(i)));
RoundOutxD(i,1) <= RotOutRxD(i);
RoundOutxD(i,2) <= SxDP(i,1);
RoundOutxD(i,3) <= SxDP(i,2);
end generate f_step;
with to_integer(IxD) mod 3 select
SPermxD <=
(RotOutRxD(1), RotOutRxD(0), RotOutRxD(3), RotOutRxD(2)) when 0,
(RotOutRxD(2), RotOutRxD(3), RotOutRxD(0), RotOutRxD(1)) when 1,
(RotOutRxD(3), RotOutRxD(2), RotOutRxD(1), RotOutRxD(0)) when others;
SrxD <= RS(to_integer(IxD(5 downto 3) & IxD(1 downto 0)), 1);
RrxD <= RS(to_integer(IxD(5 downto 3) & IxD(1 downto 0)), 0);
-- Memroy
-----------------------------------------------------------------------------
p_mem : process (ClkxCI, RstxRBI)
begin -- process p_mem
if RstxRBI = '0' then -- asynchronous reset (active low)
SxDP <= (others => (others => (others => '0')));
SIVxDP <= (others => (others => (others => '0')));
MxDP <= (others => '0');
elsif ClkxCI'event and ClkxCI = '1' then -- rising clock edge
SxDP <= SxDN;
if InEnxEI = '1' then
MxDP <= DxDI;
end if;
if SavexS = '1' then
SIVxDP <= RoundOut2xD;
end if;
end if;
end process p_mem;
end rtl;