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-- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
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library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;

entity permix is

  port (
    MxDI         : in  std_logic_vector(255 downto 0);
    PerselectxSI : in  std_logic;
    MxDO         : out std_logic_vector(255 downto 0));

end permix;

architecture rtl of permix is

  signal P0xD : unsigned(63 downto 0);
  signal P1xD : unsigned(63 downto 0);
  signal P2xD : unsigned(63 downto 0);
  signal P3xD : unsigned(63 downto 0);

  signal Pa0xD : unsigned(63 downto 0);
  signal Pa1xD : unsigned(63 downto 0);
  signal Pa2xD : unsigned(63 downto 0);
  signal Pa3xD : unsigned(63 downto 0);

  signal Pb0xD : unsigned(63 downto 0);
  signal Pb1xD : unsigned(63 downto 0);
  signal Pb2xD : unsigned(63 downto 0);
  signal Pb3xD : unsigned(63 downto 0);

  signal Pc0xD : unsigned(63 downto 0);
  signal Pc1xD : unsigned(63 downto 0);
  signal Pc2xD : unsigned(63 downto 0);
  signal Pc3xD : unsigned(63 downto 0);

  signal Pd0xD : unsigned(63 downto 0);
  signal Pd1xD : unsigned(63 downto 0);
  signal Pd2xD : unsigned(63 downto 0);
  signal Pd3xD : unsigned(63 downto 0);

  signal Rotation1axS : integer;
  signal Rotation1bxS : integer;
  signal Rotation2axS : integer;
  signal Rotation2bxS : integer;
  signal Rotation3axS : integer;
  signal Rotation3bxS : integer;
  signal Rotation4axS : integer;
  signal Rotation4bxS : integer;
  
begin  -- rtl
  
  Rotation1axS <= 5  when PerselectxSI = '1' else 26;
  Rotation1bxS <= 56 when PerselectxSI = '1' else 20;
  Rotation2axS <= 36 when PerselectxSI = '1' else 53;
  Rotation2bxS <= 28 when PerselectxSI = '1' else 35;
  Rotation3axS <= 13 when PerselectxSI = '1' else 11;
  Rotation3bxS <= 46 when PerselectxSI = '1' else 42;
  Rotation4axS <= 58 when PerselectxSI = '1' else 59;
  Rotation4bxS <= 44 when PerselectxSI = '1' else 50;

  P0xD <= unsigned(MxDI(255 downto 192));
  P1xD <= unsigned(MxDI(191 downto 128));
  P2xD <= unsigned(MxDI(127 downto 64));
  P3xD <= unsigned(MxDI(63 downto 0));

  Pa0xD <= P0xD + P1xD;
  Pa3xD <= (P1xD rol Rotation1axS) xor Pa0xD;
  Pa2xD <= P2xD + P3xD;
  Pa1xD <= (P3xD rol Rotation1bxS) xor Pa2xD;

  Pb0xD <= Pa0xD + Pa1xD;
  Pb3xD <= (Pa1xD rol Rotation2axS) xor Pb0xD;
  Pb2xD <= Pa2xD + Pa3xD;
  Pb1xD <= (Pa3xD rol Rotation2bxS) xor Pb2xD;

  Pc0xD <= Pb0xD + Pb1xD;
  Pc3xD <= (Pb1xD rol Rotation3axS) xor Pc0xD;
  Pc2xD <= Pb2xD + Pb3xD;
  Pc1xD <= (Pb3xD rol Rotation3bxS) xor Pc2xD;

  Pd0xD <= Pc0xD + Pc1xD;
  Pd3xD <= (Pc1xD rol Rotation4axS) xor Pd0xD;
  Pd2xD <= Pc2xD + Pc3xD;
  Pd1xD <= (Pc3xD rol Rotation4bxS) xor Pd2xD;

  MxDO(255 downto 192) <= std_logic_vector(Pd0xD);
  MxDO(191 downto 128) <= std_logic_vector(Pd1xD);
  MxDO(127 downto 64)  <= std_logic_vector(Pd2xD);
  MxDO(63 downto 0)    <= std_logic_vector(Pd3xD);

end rtl;