------------------------------------------------------------ -- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich -- http://www.iis.ee.ethz.ch/~sha3 ------------------------------------------------------------ library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; entity skein is port ( ClkxCI : in std_logic; RstxRBI : in std_logic; BlockAvailablexSI : in std_logic; FinBlockxSI : in std_logic; BlockxDI : in std_logic_vector(255 downto 0); HashAvailablexSO : out std_logic; HashxDO : out std_logic_vector(255 downto 0)); end skein; architecture rtl of skein is component permix port ( MxDI : in std_logic_vector(255 downto 0); PerselectxSI : in std_logic; MxDO : out std_logic_vector(255 downto 0)); end component; component subkey port ( KxDI : in std_logic_vector(255 downto 0); SxSI : in std_logic_vector(4 downto 0); KenablexSI : in std_logic; KinitxSI : in std_logic; RstxRBI : in std_logic; ClkxCI : in std_logic; TxDI : in std_logic_vector(127 downto 0); KsxDO : out std_logic_vector(255 downto 0)); end component; component tweak port ( BnxSI : in std_logic_vector(95 downto 0); FirstxSI : in std_logic; FinalxSI : in std_logic; OutxSI : in std_logic; TxDO : out std_logic_vector(127 downto 0)); end component; component controller port ( BlockAvailablexSI : in std_logic; ClkxCI : in std_logic; RstxRBI : in std_logic; SxSO : out std_logic_vector(4 downto 0); MenablexSO : out std_logic; GselectxSO : out std_logic; PerselectxSO : out std_logic; KenablexSO : out std_logic; BcontrolxSO : out std_logic_vector(1 downto 0); FirstxSO : out std_logic; FinBlockxSI : in std_logic; OutxSO : out std_logic; KinitxSO : out std_logic; MzeroxSO : out std_logic; HashAvailablexSO : out std_logic); end component; signal MxDN, MxDP, GxDN, GxDP, GtxDP, GKxD, PMxD, GXxD, KsxD : std_logic_vector(255 downto 0); signal BnxSN, BnxSP, BnxS : std_logic_vector(95 downto 0); signal GselectxS, KenablexS, FirstxS, FinalxS, OutxS, MzeroxS : std_logic; signal KinitxS, MenablexS, GenablexS, PerselectxS, FinalFlagxS : std_logic; signal BcontrolxS : std_logic_vector(1 downto 0); signal SxS : std_logic_vector(4 downto 0); signal TxD : std_logic_vector(127 downto 0); -- constant IV : std_logic_vector(255 downto 0) := (X"388512680E660046" & X"4B72D5DEC5A8FF01" & X"281A9298CA5EB3A5" & X"54CA5249F46070C4"); begin -- rtl i_controller : controller port map ( BlockAvailablexSI => BlockAvailablexSI, ClkxCI => ClkxCI, RstxRBI => RstxRBI, SxSO => SxS, MenablexSO => MenablexS, GselectxSO => GselectxS, PerselectxSO => PerselectxS, KenablexSO => KenablexS, BcontrolxSO => BcontrolxS, FirstxSO => FirstxS, FinBlockxSI => FinalFlagxS, OutxSO => OutxS, KinitxSO => KinitxS, MzeroxSO => MzeroxS, HashAvailablexSO => HashAvailablexSO); i_permix : permix port map ( MxDI => GKxD, PerselectxSI => PerselectxS, MxDO => PMxD); i_subkey : subkey port map ( KxDI => GXxD, SxSI => SxS, KenablexSI => KenablexS, KinitxSI => KinitxS, RstxRBI => RstxRBI, ClkxCI => ClkxCI, TxDI => TxD, KsxDO => KsxD); i_tweak : tweak port map ( BnxSI => BnxS, FirstxSI => FirstxS, FinalxSI => FinBlockxSI, OutxSI => OutxS, TxDO => TxD); MxDN <= BlockxDI when MzeroxS = '0' else (others => '0'); GxDN <= MxDN when GselectxS = '0' else PMxD; GxDP <= GtxDP when MzeroxS = '0' else (others => '0'); GKxD(255 downto 192) <= std_logic_vector(unsigned(GxDP(255 downto 192)) + unsigned(KsxD(255 downto 192))); GKxD(191 downto 128) <= std_logic_vector(unsigned(GxDP(191 downto 128)) + unsigned(KsxD(191 downto 128))); GKxD(127 downto 64) <= std_logic_vector(unsigned(GxDP(127 downto 64)) + unsigned(KsxD(127 downto 64))); GKxD(63 downto 0) <= std_logic_vector(unsigned(GxDP(63 downto 0)) + unsigned(KsxD(63 downto 0))); GXxD <= MxDP xor GKxD; -- GXxD(255 downto 248) MxDP(199 downto 192) xor GKxD(255 downto 248); -- GXxD(247 downto 240) MxDP(207 downto 200) xor GKxD(247 downto 240); -- GXxD(239 downto 232) MxDP(215 downto 208) xor GKxD(239 downto 232); -- GXxD(231 downto 224) MxDP(223 downto 216) xor GKxD(231 downto 224); -- GXxD(223 downto 216) MxDP(231 downto 224) xor GKxD(223 downto 216); -- GXxD(215 downto 208) MxDP(239 downto 232) xor GKxD(215 downto 208); -- GXxD(207 downto 200) MxDP(247 downto 240) xor GKxD(207 downto 200); -- GXxD(199 downto 192) MxDP(255 downto 248) xor GKxD(199 downto 192); -- GXxD(191 downto 184) MxDP(135 downto 128) xor GKxD(191 downto 184); -- GXxD(183 downto 176) MxDP(143 downto 136) xor GKxD(183 downto 176); -- GXxD(175 downto 168) MxDP(151 downto 144) xor GKxD(175 downto 168); -- GXxD(167 downto 160) MxDP(159 downto 152) xor GKxD(167 downto 160); -- GXxD(159 downto 152) MxDP(167 downto 160) xor GKxD(159 downto 152); -- GXxD(151 downto 144) MxDP(175 downto 168) xor GKxD(151 downto 144); -- GXxD(143 downto 136) MxDP(183 downto 176) xor GKxD(143 downto 136); -- GXxD(135 downto 128) MxDP(191 downto 184) xor GKxD(135 downto 128); -- GXxD(127 downto 120) MxDP(71 downto 64) xor GKxD(127 downto 120); -- GXxD(119 downto 112) MxDP(79 downto 72) xor GKxD(119 downto 112); -- GXxD(111 downto 104) MxDP(87 downto 80) xor GKxD(111 downto 104); -- GXxD(103 downto 96) MxDP(95 downto 88) xor GKxD(103 downto 96); -- GXxD(95 downto 88) MxDP(103 downto 96) xor GKxD(95 downto 88); -- GXxD(87 downto 80) MxDP(111 downto 104) xor GKxD(87 downto 80); -- GXxD(79 downto 72) MxDP(119 downto 112) xor GKxD(79 downto 72); -- GXxD(71 downto 64) MxDP(127 downto 120) xor GKxD(71 downto 64); -- GXxD(63 downto 56) MxDP(7 downto 0) xor GKxD(63 downto 56); -- GXxD(55 downto 48) MxDP(15 downto 8) xor GKxD(55 downto 48); -- GXxD(47 downto 40) MxDP(23 downto 16) xor GKxD(47 downto 40); -- GXxD(39 downto 32) MxDP(31 downto 24) xor GKxD(39 downto 32); -- GXxD(31 downto 24) MxDP(39 downto 32) xor GKxD(31 downto 24); -- GXxD(23 downto 16) MxDP(47 downto 40) xor GKxD(23 downto 16); -- GXxD(15 downto 8) MxDP(55 downto 48) xor GKxD(15 downto 8); -- GXxD(7 downto 0) MxDP(63 downto 56) xor GKxD(7 downto 0); HashxDO <= GXxD; -- BnxS Counter ----------------------------------------------------------------------------- BnxSN <= std_logic_vector(unsigned(BnxSP) + 32); BnxS <= BnxSP; bn_counter : process (ClkxCI, RstxRBI) begin -- process bn_counter if RstxRBI = '0' then -- asynchronous reset (active low) BnxSP <= (others => '0'); elsif ClkxCI'event and ClkxCI = '1' then -- rising clock edge if BcontrolxS = "11" then BnxSP <= BnxSP; elsif BcontrolxS = "10" then BnxSP(95 downto 6) <= (others => '0'); BnxSP(5 downto 0) <= "100000"; elsif BcontrolxS = "01" then BnxSP <= BnxSN; elsif BcontrolxS = "00" then BnxSP(95 downto 6) <= (others => '0'); BnxSP(5 downto 0) <= "001000"; else BnxSP <= (others => '0'); end if; end if; end process bn_counter; -- M-register ----------------------------------------------------------------------------- M_mem : process (ClkxCI, RstxRBI) begin -- process M_mem if RstxRBI = '0' then -- asynchronous reset (active low) MxDP <= (others => '0'); elsif ClkxCI'event and ClkxCI = '1' then -- rising clock edge if MEnablexS = '1' then MxDP <= MxDN; end if; end if; end process M_mem; ----------------------------------------------------------------------------- -- F-register ----------------------------------------------------------------------------- F_mem : process (ClkxCI, RstxRBI) begin -- process F_mem if RstxRBI = '0' then -- asynchronous reset (active low) FinalFlagxS <= '0'; elsif ClkxCI'event and ClkxCI = '1' then -- rising clock edge if MEnablexS = '1' then FinalFlagxS <= FinBlockxSI; end if; end if; end process F_mem; ----------------------------------------------------------------------------- -- G-register ----------------------------------------------------------------------------- G_mem : process (ClkxCI, RstxRBI) begin -- process G_mem if RstxRBI = '0' then -- asynchronous reset (active low) GtxDP <= (others => '0'); elsif ClkxCI'event and ClkxCI = '1' then -- rising clock edge GtxDP <= GxDN; end if; end process G_mem; ----------------------------------------------------------------------------- end rtl;