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-- Copyright: 2010 Integrated Sytems Laboratory, ETH Zurich
--            http://www.iis.ee.ethz.ch/~sha3
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library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;

entity tweak is

  port (
    BnxSI    : in  std_logic_vector(95 downto 0);
    FirstxSI : in  std_logic;
    FinalxSI : in  std_logic;
    TxDO     : out std_logic_vector(127 downto 0);
    OutxSI   : in  std_logic);


end tweak;

architecture rtl of tweak is


  signal TtxD : std_logic_vector(127 downto 0);

begin  -- rtl




  TtxD(95 downto 4) <= BnxSI(95 downto 4) when OutxSI = '0' else (others => '0');
  TtxD(3 downto 0)  <= BnxSI(3 downto 0)  when OutxSI = '0' else "1000";

  TtxD(119 downto 96)  <= (others => '0');
  TtxD(125 downto 120) <= "110000" when OutxSI = '0' else "111111";
  TtxD(126)            <= FirstxSI;
  TtxD(127)            <= FinalxSI;

  TxDO(127 downto 64) <= TtxD(63 downto 0);
  TxDO(63 downto 0)   <= TtxD(127 downto 64);
    
end rtl;