Module cdc_2phase

A two-phase clock domain crossing.

CONSTRAINT: Requires max_delay of min_period(src_clk_i, dst_clk_i) through the paths async_req, async_ack, async_data.

Parameters

`T`

Ports

`src_rst_ni`

`src_clk_i`

`src_data_i`

`src_valid_i`

`src_ready_o`

`dst_rst_ni`

`dst_clk_i`

`dst_data_o`

`dst_valid_o`

`dst_ready_i`

Signals

`async_data: T`