Enables simple structural composition similar to graphical editors.
Simplifies the creation of higher design levels where subcomponents
are simply sticked together:
Create a skeleton for a new component
Place subcomponents directly from the hierarchy browser
Automatically connect all subcomponents and create the ports for
the new component (based on names of actual parameters)
Automatic generation of a components package (package containing
component declarations for all entities).
Port Translation
Reverse direction of ports (useful for testbenches).
Subprogram Translation
Copy/paste of subprogram interfaces (similar to port translation).
Code Filling
Condense code using code-sensitive block filling (e.g. sensitivity
lists or port maps).
Code Statistics
Calculate number of code lines and statements in a buffer.
Enhanced Features
Testbench Generation
Enhanced templates and user option default values.
Highlighting
GNU Emacs 21: `lazy-lock-mode' is not used anymore (built-in
`jit-lock-mode' is faster).
Automatic buffer highlighting is now controlled by option
`global-font-lock-mode' (GNU Emacs).
(Important: You MUST customize
this option in order to turn automatic buffer highlighting on.)
And many other minor fixes and enhancements.
Remarks
Find more detailed information about new/changed user options and other
important changes in the online release notes (see VHDL Mode menu).
Built-in function for generating Makefiles. Based on actual file
dependencies obtained from the hierarchy browser.
Customizable for every compiler (option `vhdl-compiler-alist').
Can also be run non-interactively from the terminal command line.
Not supported: dependencies between different design
libraries.
Enhanced Features
Hierarchy Browser
All projects are displayed simultaneously.
Includes more information and is fully case-insensitive.
Limit the depth of hierarchy displaying (see Speedbar menu).
VHDL configurations (also hierarchical) are now considered, except
for multilevel configurations (i.e. a single configuration that goes
down more than one level).
Simple design consistency checks are performed.
Hierarchy information is incrementally updated upon saving changed
files.
Hierarchy information is cached in a file between Emacs sessions.
Project
Better customization of projects (option `vhdl-project-alist').
Allows the specification of a library name, compile
options/exceptions and directory, and the Makefile name. All of them
can contain a compiler-dependent string in order to allow easy
multi-platform use within one project.
Project setups can now be exported and imported as well as
automatically loaded and activated at startup.
Compile
Better customization of compilers (option `vhdl-compiler-alist').
Allows the insertion of the library name of the current project into
the compile options.
Port Pasting
Paste input ports as internal signal initializations.
Testbench
Include a testbench configuration.
Alignment
Enhanced and additional functions, changed key bindings.
A more intelligent line grouping results in nicer alignment of
regions and buffers. Alignment of inline comments is more
intelligent.
User Options (Customization)
Faster access to user options (custom variables) via "Options" menu
entry.
See also the changes/additions in the online documentation (marked with
a `|' at the beginning of lines).
Remarks
User Options
Find the list of new and changed user options in the online release
notes (see VHDL Mode menu).
There, see the note about re-customization of options
`vhdl-compiler-alist' and `vhdl-project-alist' in order to take full
advantage of the new features.
Installation
Install the included patches `speedbar.el' (together with `dframe.el'
and `sb-image.el'), `hideshow.el', and `itimer.el' (XEmacs only).
See the INSTALL file for details.
Release Notes 3.30
Features
Hide/Show:
Massively enhanced usage of `hideshow.el'.
Allows hiding of blocks, processes, subprograms, component declarations
and instantiations, generic/port clauses, and configurations
declarations. Limited functionality available in XEmacs (old
`hideshow.el' package).
Code updating:
Automatically update the sensitivity list of processes.
Code fixing:
Fix closing parenthesis of generic/port clauses.
Port pasting:
Include group comments, empty lines and type (instantiations).
Hierarchy scanning:
Size limits to prevent scanning of large netlist files.
Word completion for all predefined VHDL words (keywords, types, etc.).
Highlighting of forbidden words (e.g. Verilog keywords).
Minor enhancements and bug fixes.
Release Notes 3.23 beta
VHDL'93 syntax.
Insertion of user-specified models.
Port translation and testbench generation.
Source file compilation fully customizable.
Speedbar support for file browsing.
Enhanced template generators (e.g. process with synchronous reset/without
reset).
Enhanced highlighting (e.g. signals and constants), optimized color set
for dark background.
Enhanced customization.
Release Notes 3.21
Enhanced line functions.
Fixed some minor bugs.
Added installation notes for Windows NT/95.
Release Notes 3.20
Eliminated variables `vhdl-print-paper-type' and `vhdl-print-with-{fonts,colors}'.
Use variables `ps-paper-type' and `ps-print-color-p' instead.
Added variable `vhdl-use-default-faces' for fontification on monochrome
monitors and printing.
Added comment insertion to AliAS, ATTRIBUTE, TYPE, and SUBTYPE templates.
Made customization of date format in file headers more flexible.
Made VHDL Mode compatible with XEmacs 20.X.
VHDL Mode is now part of GNU Emacs.
Version 3.19 will be included in the next GNU Emacs release. Newer
versions of VHDL Mode are still distributed on this site.
Release Notes 3.18
Ikos VHDL compiler for source code analysis added.
Hiding code of VHDL processes and blocks (`hideshow.el') added.
Use of VHDL compiler options added.
Case fixing accelerated.
VHDL file headers made customizable.
Alignment functions added.
Some indentation and other bugs fixed.
Release Notes 3.15 (changes since 1.10 and 2.74)
Version numbers changed from 1.XX and 2.XX to 3.XX.
New customization implemented using `custom.el'. Allows local (individual)
and global (site-wide) customization (read instructions in INSTALL file).
If upgrading from 1.10, delete all variable settings for VHDL Mode in your
.emacs file and perform customization using the `Customize' menu entry
in the VHDL menu.
Changed key binding prefix for VHDL templates from C-c to C-c C-t (can
be customized in order the keep the old key bindings).
Indentation engine now understands "direct instantiation".
GNU Emacs 19 is not supported anymore (use VHDL Mode 3.10 or upgrade to
GNU Emacs 20).
Included Vantage and Viewlogic VHDL compilers for source code analysis.