GALS System Design:
Side Channel Attack Secure Cryptographic Accelerators

Bibliography

Frank Kagan Gurkaynak
 
<kgf@ee.ethz.ch>

 
Disclaimer:
This is the www enabled version of my thesis. This has been converted from the sources of the original file by using TTH, some perl and some hand editing. There is also a PDF. This is essentially as it is, but includes formatting for A4, and some of the color pictures from the presentation.

Contents

Bibliography

[AG02]

Mehdi-Laurent Akkar and Christophe Giraud, An Implementation of DES and AES, Secure against some Attacks, CHES '01: Revised Papers from the 3th International Workshop on Cryptographic Hardware and Embedded Systems, 2002, pp. 309-318.

[And93]

Ross Anderson, Why Cryptosystems Fail, "CCS '93: Proceedings of the 1st ACM Conference on Computer and Communications Security" (New York, NY, USA), ACM Press, 1993, pp. 215-227.

[BB04]

Davide Bertozzi and Luca Benini, Xpipes: a Network-on-Chip Architecture for Gigascale Systems-on-Chip, IEEE Circuits and Systems Magazine 4 (2004), 18-31.

[BC97]

David S. Bormann and Peter Y.K. Cheung, Asynchronous Wrapper for Heterogeneous Systems, Proc. International Conf. Computer Design (ICCD), October 1997.

[BCV⁺05]

E. Beigne, F. Clermidy, P. Vivet, A. Clouard, and M. Renaudin, An Asynchronous NOC Architecture Providing Low Latency Service and its Multi-Level Design Framework, Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, IEEE Computer Society Press, March 2005, pp. 54-63.

[BDBR05]

Swarup Bhunia, Animesh Datta, Nilanjan Banerjee, and Kaushik Roy, GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks, IEEE Trans. Comput. 54 (2005), no. 6, 752-766.

[BGK04]

Johannes Blömer, Jorge Guajardo, and Volker Krummel, Provably Secure Masking of AES, Selected Areas in Cryptography: 11th International Workshop, SAC 2004, 2004, pp. 69-83.

[BPtB02]

Kees van Berkel, Ad Peeters, and Frank te Beest, Adding Synchronous and LSSD Modes to Asynchronous Circuits, Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, April 2002, pp. 161-170.

[CCD00]

Christophe Clavier, Jean-Sebastien Coron, and Nora Dabbous, Differential Power Analysis in the Presence of Hardware Countermeasures, CHES '00: Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems, Springer-Verlag, 2000, pp. 252-263.

[Cha84]

Daniel M. Chapiro, Globally-Asynchronous Locally-Synchronous Systems, Ph.D. thesis, Stanford University, October 1984.

[CKK⁺97]

J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev, Petrify: a Tool for Manipulating Concurrent Specifications and Synthesis of Asynchronous Controllers, IEICE Transactions on Information and Systems E80-D (1997), no. 3, 315-325.

[CMSV01]

Luca P. Carloni, Kenneth L. McMillan, and Antonio L. Sangiovanni-Vincentelli, Theory of Latency-Insensitive Design, IEEE Transactions on Computer-Aided Design 20 (2001), no. 9, 1059-1076.

[CSB92]

Anantha P. Chandrakasan, S. Scheng, and Robert W. Brodersen, Low-Power CMOS Digital Design, IEEE Journal of Solid-State Circuits 27 (1992), no. 4, 473-484.

[CZ05]

Atanu Chattopadhyay and Zeljko Zilic, GALDS: A Complete Framework for Designing Multiclock ASICs and SoCs, IEEE Transactions on VLSI Systems 13 (2005), no. 6, 641-654.

[FML⁺04]

Jacques J.A. Fournier, Simon Moore, Huiyun Li, Robert Mullins, and George Taylor, Security Evaluation of Asynchronous Circuits, CHES '03: Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems, Springer-Verlag, 2004, pp. 137-151.

[FNT⁺99]

R. M. Fuhrer, S. M. Nowick, M. Theobald, N. K. Jha, B. Lin, and L. Plana, Minimalist: An Environment for the Synthesis, Verification and Testability of Burst-mode Asynchronous Machines, Tech. Report TR CUCS-020-99, Columbia University, NY, July 1999.

[GBG⁺04]

F. K. Gürkaynak, A. Burg, D. Gasser, F. Hug, N. Felber, H. Kaeslin, and W. Fichtner, A 2Gb/s Balanced AES Crypto-Chip Implementation, Proc. of the Great Lakes Symposium on VLSI, ACM Press, April 2004, pp. 39-44.

[Gin03]

Ran Ginosar, Fourteen Ways to Fool Your Synchronizer, Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, IEEE Computer Society Press, May 2003, pp. 89-96.

[GOK⁺05]

Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, and Wolfgang Fichtner, Design Challenges for a Differential Power Analysis Aware GALS based AES Crypto-ASIC, Proceedings of the 2nd Int. Workshop on Formal Methods For Globally Asynchronous Locally Synchronous Architectures FMGALS2005, July 2005.

[GOV03a]

Frank K. Gürkaynak, Stephan Oetiker, and Thomas Villiger, GALS Bus Test Chip: Shir Khan, Technical Report 11/2003, Integrated Systems Laboratory, ETH Zurich, Switzerland, 2003.

[GOV⁺03b]

Frank K. Gürkaynak, Stephan Oetiker, Thomas Villiger, Norbert Felber, Hubert Kaeslin, and Wolfgang Fichtner, On the GALS Design Methodology of ETH Zurich, Proceedings of the Formal Methods For Globally Asynchronous Locally Synchronous (GALS)Architecture FMGALS2003, September 2003, pp. 181-189.

[GT03]

Jovan Dj. Golic and Christophe Tymen, Multiplicative Masking and Power Analysis of AES, CHES '02: Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems, Springer-Verlag, 2003, pp. 198-212.

[GVO⁺02]

Frank K. Gürkaynak, Thomas Villiger, Stephan Oetiker, Norbert Felber, Hubert Kaeslin, and Wolfgang Fichtner, A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems, Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, April 2002, pp. 181-189.

[HBB95]

Henrik Hulgaard, Steven M. Burns, and Gaetano Borriello, Testing Asynchronous Circuits: A Survey, Integration, the VLSI journal 19 (1995), no. 3, 111-131.

[IKM00]

T. Ichikawa, T. Kasuya, and M. Matsui, Hardware Evaluation of the AES Finalists, Proc. 3rd AES Candidate Conf., New York, April 2000, pp. 279-285.

[IM02]

Anoop Iyer and Diana Marculescu, Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors, Proceedings of the 29th Annual International Symposium on Computer Architecture, May 2002, pp. 158 - 168.

[JT03]

Axel Jantsch and Hannu Tenhunen (eds.), Networks on Chip, Kluwer Academic Publishers, Hingham, MA, USA, 2003.

[KB95]

Ajay Khoche and Erik Brunvand, Testing Self-Timed Circuits using Partial Scan, Asynchronous Design Methodologies, IEEE Computer Society Press, May 1995, pp. 160-169.

[KGS05]

M. Krstic, E. Grass, and C. Stahl, Request-driven GALS Technique for Wireless Communication System, Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, March 2005, pp. 76-85.

[KJJ99]

Paul Kocher, Joshua Jaffe, and Benjamin Jun, Differential Power Analysis, Lecture Notes in Computer Science 1666 (1999), 388-397.

[KL02]

S.-M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design, McGraw Hill, 2002.

[KMB03]

N. S. Kim, T. Mudge, and R. Brown, A 2.3 Gb/s Fully Integrated and Synthesizable AES Rijndael Core, Proc. IEEE Custom Integrated Circuits Conference, September 2003, pp. 193-196.

[Koc96]

Paul C. Kocher, Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems, Lecture Notes in Computer Science 1109 (1996), 104-113.

[KPWK02]

Joep Kessels, Ad Peeters, Paul Wielage, and Suk-Jin Kim, Clock Synchronization through Handshake Signalling, Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, April 2002, pp. 59-68.

[LT02]

C.-C. Lu and S.-Y. Tseng, Integrated Design of AES (Advanced Encryption Standard) Encrypter and Decrypter, Proc. Application-Specific Systems, Architectures and Processors, July 2002, pp. 277-285.

[LTG⁺02]

A. K. Lutz, J. Treichler, F. K. Gürkaynak, H. Kaeslin, G. Basler, A. Erni, S. Reichmuth, P. Rommens, S. Oetiker, and W. Fichtner, 2 Gb/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis, Proc. Cryptographic Hardware and Embedded Systems - CHES 2002, LNCS 2523, Springer-Verlag, August 2002, pp. 144-158.

[MAK00]

S. Moore, R. Anderson, and M. Kuhn, Improving Smartcard Security using Self-Timed Circuit Technology, 2000.

[Man04]

Stefan Mangard, Hardware Countermeasures against DPA ? A Statistical Analysis of Their Effectiveness, Proceedings of the RSA Conference 2005 Cryptographers' Track (CT-RSA 2004), 2004, pp. 222-235.

[MH91]

Alain J. Martin and Pieter J. Hazewindus, Testing Delay-Insensitive Circuits, Advanced Research in VLSI (Carlo H. Séquin, ed.), MIT Press, 1991, pp. 118-132.

[MM03]

M. McLoone and J. V. McCanny, Rijndael FPGA Implementations Utilising Look-Up Tables, Journal of VLSI Signal Processing 34 (2003), no. 3, 261-275.

[MNT⁺04]

Mikael Millberg, Erland Nilsson, Rikard Thid, Shashi Kumar, and Axel Jantsch, The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip, VLSID '04: Proceedings of the 17th International Conference on VLSI Design (Washington, DC, USA), IEEE Computer Society, 2004, p. 693.

[MPG05]

S. Mangard, T. Popp, and B. M. Gammel, Side-Channel Leakage of Masked CMOS Gates, Proceedings of the RSA Conference 2005 Cryptographers' Track (CT-RSA 2005), 2005.

[MTMR02]

Simon Moore, George Taylor, Robert Mullins, and Peter Robinson, Point to Point GALS Interconnect, Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, April 2002, pp. 69-75.

[Mut01]

Jens Muttersbach, Globally-Asynchronous Locally-Synchronous Architectures for VLSI Systems, Ph.D. thesis, ETH, Zurich, 2001.

[MVF00]

Jens Muttersbach, Thomas Villiger, and Wolfgang Fichtner, Practical Design of Globally-Asynchronous Locally-Synchronous Systems, Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, April 2000, pp. 52-59.

[MvOV96]

Alfred J. Menezes, Paul C. van Oorschot, and Scott A. Vanstone, Handbook of Applied Cryptography, CRC Press, 1996.

[MZK⁺99]

Eric Jan Marinissen, Yervant Zorian, Rohit Kapur, Tony Taylor, and Lee Whetsel, Towards a Standard for Embedded Core Test: An Example, Proceedings of the International Test Conference, September 1999, pp. 616 - 627.

[Nat99]

National Institute of Standards and Technology (NIST), Data Encryption Standard (DES), FIPS Publication 46-3 (1999).

[Nat01a]

, Advanced Encryption Standard (AES), FIPS Publication 197 (2001).

[Nat01b]

, Recommendation for Block Cipher Modes of Operation, Methods and Techniques, FIPS Publication SP 800-38A 2001 ED (2001).

[NCM⁺02]

Kevin J. Nowka, Gary D. Carpenter, Eric W. MacDonald, Hung C. Ngo, Bishop C. Brock, Koji I. Ishii, Tuyet Y. Nguyen, and Jeffrey L. Burns, A 32-bit PowerPC System-on-a-Chip With Support for Dynamic Voltage Scaling and Dynamic Frequency Scaling, IEEE Journal of Solid-State Circuits 37 (2002), no. 11, 1441-2447.

[OGOP04]

S. B. Ors, F. K. Gürkaynak, E. Oswald, and B. Preneel, Power-Analysis Attacks on an ASIC AES Implementation, Proc. of International Conference on Information Technology (ITCC): Special Track on Embedded Cryptographic Hardware, April 2004, pp. 546-552.

[OGV⁺03]

Stephan Oetiker, Frank K. Gürkaynak, Thomas Villiger, Hubert Kaeslin, Norbert Felber, and Wolfgang Fichtner, Design Flow for a 3-million Transistor GALS Test Chip, Handouts of the Third Asynchronous Circuit Design Workshop, ACiD 2003, Heraklion, Greece, January 2003.

[OVG⁺02]

Stephan Oetiker, Thomas Villiger, Frank K. Gürkaynak, Hubert Kaeslin, Norbert Felber, and Wolfgang Fichtner, High Resolution Clock Generators for Globally-Asynchronous Locally-Synchronous Designs, Handouts of the Second ACiD-WG Workshop of the European Commission's Fifth Framework Programme, Munich, Germany, January 2002.

[PF95]

O. A. Petlin and S. B. Furber, Scan Testing of Micropipelines, Proc. IEEE VLSI Test Symposium, May 1995, pp. 296-301.

[PGH⁺04]

N. Pramstaller, F. K. Gürkaynak, S. Haene, H Kaeslin, N. Felber, and W. Fichtner, DPA Resistant AES Crypto-Chip Design, Proc. European Solid-State Circuits Conference (ESSCIRC), IEEE Press, 2004, pp. 307-310.

[Ron99]

Marly Roncken, Defect-Oriented Testability for Asynchronous IC's, Proceedings of the IEEE 87 (1999), no. 2, 363-375.

[RSA78]

R. L. Rivest, A. Shamir, and L. Adleman, A method for obtaining digital signatures and public-key cryptosystems, Communications of the ACM 21 (1978), no. 2, 120-126.

[RVFG05]

Dobkin Rostislav, Victoria Vishnyakov, Eyal Friedman, and Ran Ginosar, An Asynchronous Router for Multiple Service Levels Networks on Chip, Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, IEEE Computer Society Press, March 2005, pp. 44-53.

[SAM⁺04]

G. Semeraro, D. H. Albonesi, G. Magklis, M. L. Scott, S. G. Dropsho, and S. Dwarkadas, Hiding Synchronization Delays in GALS Processor Microarchitecture, Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, IEEE Computer Society Press, April 2004, pp. 159-169.

[SF01]

Jens Sparsø and Steve Furber (eds.), Principles of Asynchronous Circuit Design: A Systems Perspective, Kluwer Academic Publishers, 2001.

[SLHW03]

C.-P. Su, T.-F. Lin, C.-T. Huang, and C.-W. Wu, A Highly Efficient AES Cipher Chip, Proc. of Asia and South Pasific Design Automation Conference ASP-DAC 2003, January 2003, pp. 561-562.

[SMBY05]

Danil Sokolov, Julian Murphy, Alex Bystrov, and Alex Yakovlev, Design and Analysis of Dual-Rail Circuits for Security Applications, IEEE Transactions on Computers 54 (2005), no. 4, 449-460.

[Smi04]

Scott F. Smith, An Asynchronous GALS Interface with Applications, In Proc. IEEE Workshop on Microelectronics and Electron Devices, 2004, pp. 41-44.

[SMTM01]

A. Satoh, S. Morioka, K. Takano, and S. Munetoh, A Compact Rijndael Hardware Architecture with S-Box Optimization, Proc. ASIACRYPT 2001, LNCS 2248, Springer-Verlag, 2001, pp. 239-254.

[TV03]

Kris Tiri and Ingrid Verbauwhede, Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology, CHES '02: Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems, 2003, pp. 125-136.

[Vil05]

Thomas Villiger, Multi-point Interconnects for Globally-Asynchronous Locally-Synchronous Systems, Ph.D. thesis, ETH, Zurich, 2005.

[VSK03]

I. Verbauwhede, P. Schaumont, and H. Kuo, Design and Performance Testing of a 2.29-GB/s Rijndael Processor, IEEE Journal of Solid-State Circuits 38 (2003), no. 3, 569-572.

[WBRF00]

Bryan Weeks, Mark Bean, Tom Rozylowicz, and Chris Ficke, Hardware Performance Simulations of Round 2 Advanced Encryption Standard Algorithms, Proc. 3rd AES Candidate Conf., New York, April 2000, pp. 286-304.

[Wie95]

Rik van de Wiel, High-Level Test Evaluation of Asynchronous Circuits, Asynchronous Design Methodologies, IEEE Computer Society Press, May 1995, pp. 63-71.

[WOL02]

J. Wolkerstorfer, E Oswald, and M. Lamberger, An ASIC implementation of the AES S-boxes, Proc. RSA Security Conf. San Jose, CA, February 2002, pp. 67-78.

[YD99a]

Kenneth Y. Yun and David L. Dill, Automatic Synthesis of Extended Burst-Mode Circuits: Part I (Specification and Hazard-Free Implementation) , IEEE Transactions on Computer-Aided Design 18 (1999), no. 2, 101-117.

[YD99b]

, Automatic Synthesis of Extended Burst-Mode Circuits: Part II (Automatic Synthesis), IEEE Transactions on Computer-Aided Design 18 (1999), no. 2, 118-132.

[YFP03]

Z. C. Yu, S. B. Furber, and L. A. Plana, An Investigation into the Security of Self-Timed Circuits, Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, IEEE Computer Society Press, May 2003, pp. 206-215.